JPH09307437A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a frequency lock in time at the initial operation at application of power by providing a charging means charging a capacitor of a loop filter for a prescribed period when a reset signal is valid. SOLUTION: The PLL circuit is provided with a charging means 7 to charge a capacitor of a loop filter 3 for a prescribed time when a reset signal RST from a reset circuit is valid in interlocking with the reset circuit at application of power. Thus, the capacitor of the loop filter 3 is charged for a prescribed time at application of power (at reset) so that its voltage almost reaches a specified voltage of a voltage controlled oscillator 4 corresponding to a phase lock frequency thereby allowing a voltage of the voltage controlled oscillator 4 to reach the specified voltage (operating point) quickly. When the prescribed time elapses, a charging element (P-channel transistor(TR)) is nonconductive and reaches a state similar to that it is disconnected from the loop filter 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit that can be used in, for example, an LSI clock circuit or a communication device.

[0002]

2. Description of the Related Art Conventionally, a phase locked loop circuit (hereinafter referred to as a PLL circuit) as shown in FIG. 14 has been known. Referring to FIG. 14, the PLL circuit generally includes a signal generator 100, a first divider 102, a second divider 6,
Phase comparator 1, charge pump 2, low-pass filter
(LPF) 3 and voltage controlled oscillator (VCO) 4.

In this PLL circuit, first, the signal generator 1
The reference frequency signal c obtained by dividing the signal of 00 by the first divider 102 and the comparison frequency signal obtained by dividing the output signal of the VCO 4 by the value set by the frequency setting signal a by the second divider 6 d and d are input to the phase comparator 1 to obtain phase difference outputs based on the frequency and phase difference between the reference frequency signal c and the comparison frequency signal d.

Next, these two phase difference outputs from the phase comparator 1 are input to the charge pump 2 and the low-pass filter 3 to be smoothed (the low-pass filter 3 performs waveform shaping to cut high frequency components), and the VCO 4 A control voltage for controlling the oscillation frequency is generated, and the VCO 4 determines the oscillation frequency based on the output voltage (control voltage) from the LPF 3. Then, the output signal of the VCO 4 becomes an input of the second frequency divider 6 and forms a feedback loop.

By forming the feedback loop in this way, the output signal of the VCO 4 tries to have a frequency that is a frequency division multiple of the second frequency divider 102 of the reference frequency signal c, and becomes equal to the reference frequency signal c. Since an attempt is made to eliminate the phase difference, it becomes possible to output a set frequency signal in synchronization with the reference frequency signal c.

[0006]

By the way, the above-described conventional phase-locked loop circuit (PLL circuit) is used in the VCO in the initial synchronous operation such as when the power is turned on (at the time of reset).
Since the control voltage applied to 4 is uncertain, the initial control voltage is
There is a problem that it takes a long time to achieve synchronization when the control voltage is far from the required frequency.

That is, the above-described conventional PLL circuit has a problem that the frequency pull-in time becomes long in the initial synchronization operation such as when the power is turned on (at the time of reset).

In order to avoid such a problem, for example,
Techniques such as those disclosed in JP-A-6-61852 and JP-A-6-303131 have been proposed. JP-A-6
In the technique shown in No. 61852, the PLL of FIG.
In the circuit configuration, further, control voltage information (digital data) of the voltage controlled oscillator corresponding to the frequency used in advance.
Or a conversion circuit for converting the stored control voltage information (digital data) corresponding to the set frequency into a voltage and applying it to the voltage controlled oscillator 4 at the end of frequency setting, or using in advance. The control voltage of the voltage controlled oscillator 4 corresponding to the frequency to be obtained is selectively obtained by resistance voltage division, and the control voltage corresponding to the set frequency is selected and applied to the voltage controlled oscillator 4 at the end of frequency setting. By providing a circuit, even when the control voltage of the voltage controlled oscillator is significantly different from the set frequency when the power is turned on, the frequency pull-in time is shortened, and the lock-up time is ultimately shortened. are doing.

In Japanese Patent Laid-Open No. 6-303131, P
As the LL circuit, two loops, a loop I having a high phase comparison frequency and a loop II having a low phase comparison frequency, are provided, and the loop II having a low phase comparison frequency has a response speed sufficiently higher than that of the loop I having a high phase comparison frequency. For example, two sets of phase comparators and low-pass filters (loop filters) with different frequency pull-in characteristics are prepared, and one of them is selected and used depending on the case to shorten the frequency pull-in time. You can hide it.

However, in the technique disclosed in Japanese Unexamined Patent Publication No. 6-61852, the PLL circuit configured as shown in FIG. 14 is further provided with a memory element for storing a control voltage of the voltage controlled oscillator corresponding to a frequency to be used in advance as a digital value. , A D / A converter for converting the stored control voltage (digital value) into an analog voltage and applying it to the voltage controlled oscillator is required, or control of the voltage controlled oscillator corresponding to the frequency used in advance. A resistance divider for voltage-dividing the voltage and a selection circuit for selecting a control voltage corresponding to the set frequency and applying it to the voltage controlled oscillator are required, and both of them have a drawback that the circuit scale becomes large. Further, in the technique of Japanese Patent Laid-Open No. 6-303131, it is necessary to prepare two sets of a phase comparator and a low pass filter (loop filter), which has a drawback that the circuit scale becomes large.

That is, although any of the above-mentioned techniques is suitable for applications with a high frequency switching frequency such as mobile communication, in order to use it in applications where the frequency is almost constant, such as the clock circuit of a CPU, There was a problem that the circuit scale etc. became too large.

The present invention is a phase-locked loop circuit capable of easily shortening the frequency pull-in time in the initial operation at the time of power-on and rapidly obtaining a stable steady state without increasing the circuit scale or the like. Is intended to provide.

[0013]

In order to achieve the above object, the invention according to claim 1 is a frequency dividing means for generating a frequency dividing frequency signal, a reference frequency signal and a frequency dividing frequency signal from the frequency dividing means. Phase comparison means for generating a phase difference output based on the frequency and the phase difference between the voltage control oscillation means and the voltage control oscillation means, and a control voltage for controlling the oscillation frequency of the voltage control oscillation means based on the phase difference output from the phase comparison means. In a phase-locked loop circuit having a control voltage generating means and applying an output signal from the voltage controlled oscillating means to the frequency dividing means to form a feedback loop, the control voltage generating means supplies the control voltage to the voltage controlled oscillating means. A loop filter for shaping the waveform and giving it, and a charging means for charging the capacitor of the loop filter for a predetermined period when the reset signal becomes effective are provided. It is.

According to a second aspect of the present invention, in the phase-locked loop circuit according to the first aspect, the capacitor of the loop filter is charged up to the voltage of the voltage controlled oscillation means corresponding to the phase locked frequency for a predetermined period. It is characterized by being set to a time sufficient for.

According to the third aspect of the invention, the frequency dividing means for generating the frequency dividing frequency signal and the phase difference output based on the frequency and the phase difference between the reference frequency signal and the frequency dividing frequency signal from the frequency dividing means. The voltage control oscillator includes: a phase comparison unit for generating the voltage control oscillation unit; and a control voltage generation unit for generating a control voltage for controlling the oscillation frequency of the voltage control oscillation unit based on the phase difference output from the phase comparison unit. In a phase-locked loop circuit in which a feedback loop is formed by applying an output signal from the means to the frequency dividing means, the control voltage generating means includes a loop filter element for waveform-shaping the control voltage to the voltage controlled oscillating means. , A switch means for variably setting a filter constant determined by the loop filter element, and by switching the switch means, a different loop constant is provided. It is characterized in that it is capable of forming a phase control loop having.

The invention according to claim 4 is the phase-locked loop circuit according to claim 3, wherein the loop filter element has a capacitor and a resistor, and the switch means has a resistance value of the resistance of the loop filter element. It is characterized in that it is configured to be variable.

According to a fifth aspect of the present invention, in the phase-locked loop circuit according to the third aspect, the loop filter element has a capacitor and a resistor, and the switch means has a capacitance value of the capacitor of the loop filter element. It is characterized in that it is configured to be variable.

According to a sixth aspect of the invention, in the phase-locked loop circuit according to the third aspect, the loop filter element has a capacitor and a resistor, and the switch means has a resistance value of the resistance of the loop filter element. And the capacitance value of the capacitor are variable.

The invention according to claim 7 is the phase locked loop circuit according to any one of claims 3 to 6, characterized in that the control voltage generating means is formed by an IC. There is.

The invention according to claim 8 is the phase-locked loop circuit according to claim 7, wherein the capacitor of the loop filter element formed inside the IC is a channel undoped capacitor. .

[0021] According to a ninth aspect of the present invention, a frequency dividing means for generating a frequency dividing frequency signal and a phase difference output based on a frequency and a phase difference between the reference frequency signal and the frequency dividing frequency signal from the frequency dividing means. The voltage control oscillator includes: a phase comparison unit for generating the voltage control oscillation unit; and a control voltage generation unit for generating a control voltage for controlling the oscillation frequency of the voltage control oscillation unit based on the phase difference output from the phase comparison unit. In a phase-locked loop circuit in which a feedback loop is formed by applying an output signal from the means to the frequency dividing means, the control voltage generating means includes a loop filter element for waveform-shaping the control voltage to the voltage controlled oscillating means. , The switch means for variably setting the filter constant determined by the loop filter element and forming the phase control loop having different loop constants, and the reset signal Predetermined period of time when it is effective, is characterized by comprising a charging means for charging the capacitor of the loop filter elements.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a charge pump 2 and a low-pass filter (loop filter) 3 of the conventional general PLL circuit shown in FIG. Referring to FIG. 1, a loop filter (low-pass filter) 3 of a general PLL circuit has constant (fixed) resistance values of resistors 3a and 3b and a capacitance value of a capacitor 3c.

Low-pass filter of PLL circuit of FIG.
When the (loop filter) 3 has the configuration of FIG. 1, the frequency pull-in time is defined by the constants (resistance value, capacitance value) of the loop filter (low-pass filter) 3, but a general PLL circuit Since the resistance values of the resistors 3a and 3b and the capacitance value of the capacitor 3c are fixed as described above, the frequency pull-in time is also constant. That is, in the general PLL circuit shown in FIG. 14, since the constants (resistance value, capacitance value) of the loop filter (low-pass filter) 3 that defines the frequency pull-in time are fixed,
It is considered that a certain frequency pull-in time is required in the initial synchronous operation at power-on (at reset), and a considerable time is required until a stable steady state is obtained.

The inventor of the present application firstly, when the loop filter 3 of the PLL circuit has a low-pass filter configuration with a fixed constant as shown in FIG. 1, the frequency in the initial synchronous operation at power-on (at reset). In order to reduce the pull-in time, it has been noted that the capacitor 3c of the loop filter (low-pass filter) 3 may be charged to a predetermined voltage when the power is turned on (at reset).

FIG. 2 is a diagram showing a first configuration example of the phase locked loop circuit (PLL circuit) according to the present invention. In FIG. 2, the same parts as those in FIG. 14 are designated by the same reference numerals. In the PLL circuit of FIG. 2, the loop filter 3
When a constant low-pass filter similar to that shown in FIG. 14 (FIG. 1) is used in FIG. 14, the reset signal R from the reset circuit is interlocked with the reset circuit (not shown) when the power is turned on.
Loop filter 3 for a predetermined period when ST becomes valid
Charging means 7 for charging the capacitor 3c is further provided.

FIG. 3 is a diagram showing a configuration example of the charging means 7 of the PLL circuit of FIG. In the example of FIG. 3, the charging means 7 includes a one-shot circuit 8 that generates a pulse of a predetermined period Tc based on the reset signal RST, and a predetermined period Tc when a pulse of the predetermined period Tc is input from the one-shot circuit 8.
It has a charging element 9 that is turned on in the middle and charges the capacitor 3c of the loop filter 3 during this period Tc. Note that in the example of FIG. 3, the charging element 9 is composed of a P-channel transistor.

That is, in the example of FIG. 3, the charging means 7 is
When the reset signal RST is generated from the reset circuit (not shown), the P-channel transistor as the charging element 9 is turned on during the predetermined period Tc by the pulse of the predetermined period Tc generated based on the reset signal RST. , The power supply voltage V _DD is supplied to the capacitor 3c of the loop filter 3 via the P-channel transistor 9, and the capacitor 3c
Is configured to charge. Here, during the predetermined period Tc, the voltage controlled oscillator 4 corresponding to the frequency at which the voltage of the capacitor 3c of the loop filter 3 is phase locked.
Is generated by the one-shot circuit 8 so that it takes time to be charged until the specified voltage (operating point) is reached.

Next, the operation of the PLL circuit configured as shown in FIGS. 2 and 3 will be described. The PLL circuit of FIG. 2 also basically operates in the same manner as the PLL circuit shown in FIG.
That is, when this PLL circuit is used for a clock circuit of an LSI, for example, when the power is turned on (at the time of reset)
First, the PLL circuit performs a frequency pull-in operation and a phase pull-in operation. More specifically, in the phase comparator 1, the reference frequency signal c and P divided by the frequency divider 6 are used.
The frequency and phase of the comparison frequency signal d of the LL loop are compared, a signal based on these frequency and phase difference is generated and given to the charge pump 2 and the loop filter 3,
In the charge pump 2 and the loop filter 3, the phase difference signal generated by the phase comparator 1 is smoothed.
(The loop filter 3 performs waveform shaping for cutting high frequency components), and supplies this to the voltage controlled oscillator 4 as a control voltage. In the voltage controlled oscillator 4, the loop filter 3
Signal (control voltage for controlling the oscillation frequency of the voltage-controlled oscillator 4) to generate a signal of a specified oscillation frequency and give it to the frequency divider 6. In the frequency divider 6, the signal generated by the voltage-controlled oscillator 4 is generated. The signal (high frequency signal) is divided and supplied again to the phase comparator 1. As a result, the phase comparator 1 compares the reference frequency signal c with the frequency-divided signal d from the voltage controlled oscillator, and creates a signal corresponding to the difference between the two.
Again, the operation of giving to the charge pump 2 and the loop filter 3 is repeated, and the voltage controlled oscillator 4 can generate and output a clock having a specified frequency.

By the way, normally, the operating point (specified voltage) of the voltage controlled oscillator 4 when generating a clock of a specified frequency is
In order to make the range wide, and in order to operate in a place with good linearity, it is often set to about 1/2 of the power supply voltage V _DD , and the pumping by the charge pump 2 is performed until the specified voltage is reached. However, as described above, it takes a considerable time to reach the specified voltage only by the pumping by the charge pump 2.

Therefore, in the PLL circuit of FIGS. 2 and 3, for example, when the power is turned on, the charging element connected to the one-shot circuit 8 linked to the reset signal RST is connected.
(P-channel transistor) 9 is turned on for a predetermined period Tc
By doing so, the power supply voltage V _DD is supplied to the capacitor 3c of the loop filter 3 via the charging element 9 to charge the capacitor 3c, and the voltage of the voltage controlled oscillator 4 is quickly increased to the specified voltage (for example, V _DD / It is possible to reach 2). At this time, as described above, the predetermined period Tc is set to a time sufficient for charging until the voltage of the capacitor 3c of the loop filter 3 reaches the specified voltage of the voltage controlled oscillator corresponding to the frequency at which the phase is locked. , Generated by the one-shot circuit 8.

In this way, at power-on (at reset)
For a predetermined period Tc, the capacitor 3c of the loop filter 3 is charged until the voltage reaches a specified voltage of the voltage controlled oscillator 4 corresponding to the frequency at which the phase is locked, and the voltage of the voltage controlled oscillator 4 is charged. Promptly regulated voltage
It is possible to reach the (operating point). Predetermined period Tc
Then, during this period, when the voltage of the voltage controlled oscillator quickly reaches the specified voltage as described above, the PLL circuit enters the steady state. When the predetermined period Tc has elapsed, the charging element (P-channel transistor) 9 is turned off,
The same state as when separated from the loop filter 3 is obtained. Therefore, when the PLL circuit enters the steady state,
The charging of the capacitor 3c of the loop filter 3 is stopped.

Although the P-channel transistor is used as the charging element 9 in the above example, an element such as a transmission gate may be used instead.
FIG. 4 is a diagram showing another configuration example of the charging means 7 of the PLL circuit of FIG. In the example of FIG. 4, the charging means 7 uses a transmission gate as the charging element 9 instead of the P-channel transistor of FIG. That is, in the example of FIG. 4, the transmission gate 9 is
When the reset signal RST is generated, the one-shot circuit 8 generates a pulse for a predetermined period Tc based on the reset signal RST to bring the power supply voltage V _DD into a conductive state for a predetermined period Tc, and the power supply voltage V _DD to the capacitor of the loop filter 3. Three
c to charge the capacitor 3c. Also in FIG. 4, the predetermined period Tc is sufficient to charge the voltage of the capacitor 3c of the loop filter 3 until it reaches the specified voltage (operating point) of the voltage-controlled oscillator 4 corresponding to the frequency at which the phase is locked. So that
It is generated by the one-shot circuit 8.

As described above, even when the transmission gate is used as the charging element 9, the transmission gate 9 connected to the one-shot circuit 8 is turned on for a predetermined period Tc, so that the capacitor 3c of the loop filter 3 is turned on. By charging, the voltage of the voltage controlled oscillator 4 can quickly reach the specified voltage (operating point).

In other words, in the examples of FIGS. 2 to 4, the capacitor 3c in the loop filter (IC) 3 is charged by the charging means 7 for a predetermined period when the power is turned on (or at the time of resetting), and the frequency pull-in is performed. Can be speeded up.

In the configuration examples of FIGS. 2 to 4 described above, the charging means 7 can be easily attached to the existing (conventional general) PLL circuit. That is,
When the loop filter 3 of the existing PLL circuit is composed of one IC, the charging means 7 need only be attached (externally attached) to this loop filter (IC) 3 with one contact. Further, when the existing PLL circuit is not used, the charging means 7 can be provided in the loop filter (IC) 3. For example, a loop filter element
In addition to (3a, 3b, 3c), the loop filter 3 including the charging means 7 can be configured as, for example, one IC.

FIG. 5 is a diagram showing a second configuration example of the phase locked loop circuit (PLL circuit) according to the present invention. In FIG. 5, for convenience, only the charge pump 2, the loop filter 3, and the voltage controlled oscillator 4 are shown.
In the PLL circuit of FIG.
Low-pass filter with fixed constants similar to (Fig. 1) (loop filter element (resistor 3a, resistor 3b, capacitor 3c))
And a switch means 1 for variably setting a filter constant determined by the loop filter elements 3a, 3b, 3c.
1 are provided, and by switching the switch means 11, it is possible to form a phase control loop having different loop constants. That is, a plurality of loop filter elements having different loop constants are formed in the loop filter, and switching control of these elements is incorporated into the phase control loop.

FIG. 6 is a diagram showing a specific example of the switch means 11 of FIG. In the example of FIG. 6, the switch means 11 includes at least one resistor R _{1 to} R _n (n ≧ 1) connected in series between the resistor 3 b and the capacitor 3 c and each resistor R _{1 to} R. a transmission gate S ₁ to S _n which are connected in parallel respectively to _n, transmission gates S ₁ ~
The controller 12 controls the conduction of S _n .

In the configuration of FIG. 6, the resistor 3b is
In order to shorten the frequency pull-in time, the resistance value of the loop filter is set to a small value, that is, the damping factor of the loop filter becomes small when the resistors R _{1 to} R _n are not provided. There is.

The controller 12 also controls the transmission gates S _{1 to} S _n when the power is turned on or reset.
Transmission gate S ₁ to switch ON
It adapted to provide a control signal CTL ₁ ~CTL _n to to S _n.

In the configuration of FIG. 6, the transmission gate S of the loop filter 3 is controlled for a predetermined period under the control of the controller 12 at the time of power-on or reset.
₁ to S _n is (a conductive state) ON next, substantially, switched to a state where the resistance R ₁ to R _n are shorted. As a result, the loop filter 3 has the loop filter elements 3a, 3
The voltage control oscillator 4 is controlled by a constant determined by the loop filter elements 3a, 3b, 3c, which is equivalent to that constituted by only b, 3c. In this case, the resistor 3b
Is set to a value such that its resistance value is small and the damping factor of the loop filter is small, so
The frequency pull-in time can be shortened.

After the lapse of the predetermined period, the controller 12 turns off the transmission gates S _{1 to} S _n .
Switch to As a result, the loop filter 3, substantially, the loop filter elements 3a, 3b, resistors R ₁ ~ to 3c
It switches to the one configured by adding R _n . Here, the predetermined period is set to a period sufficient for the voltage from the loop filter 3 to reach the specified voltage of the voltage controlled oscillator corresponding to the frequency at which the phase is locked. Therefore, after the lapse of the predetermined period, it is considered that the PLL circuit is in the steady state, and the controller 12 causes the transmission gate S ₁
By turning OFF ~ S _n , the loop filter 3 substantially causes the loop filter elements 3a, 3b, 3c to have the resistance R.
_{1 to} R _n are added (resistors R _{1 to} R _n are serially added to the resistor 3b), the damping factor of the loop filter 3 is increased, and the loop filter 3 can be stabilized. . That is, if the damping factor remains small, it is unstable and the jitter increases. Therefore, after it is considered that the steady state is reached, the resistors R _{1 to} R _n are further serially loaded to increase the damping factor. Stabilize the circuit.

As described above, in the example of FIG. 6, the switch means 11 is configured so that the capacitance value of the capacitor 3c of the loop filter element is fixed / invariable and the resistance value of the resistor 3b is substantially variable. Therefore, by substantially reducing the resistance value of the resistor 3b of the loop filter element to reduce the damping factor for a predetermined period, it is possible to speed up the frequency pull-in. That is, also with the configuration of FIG. 6, it is possible to speed up the frequency pull-in without increasing the circuit scale to a large extent.

FIG. 7 is a diagram showing another specific example of the switch means 11 of FIG. In the example of FIG. 7, the switch means 11 has at least one capacitor C _{1 to} C _m , the controller 14, and the conduction controlled by the controller 14, and connects the capacitors C _{1 to} C _m in parallel with the capacitor 3c. a transmission gate F ₁ to F _m for or disconnected from the capacitor 3c, a voltage follower 15 for charging the capacitor C ₁ -C _m, or to connect the capacitor C ₁ -C _m and voltage follower 15, or disconnect Transmission gate F ₁ ^{* to} F for
It is composed of _m ^* and.

In the configuration of FIG. 7, the capacitor 3
In order to shorten the frequency pull-in time, c is set to a value with a small capacitance value, that is, a value that reduces the damping factor of the loop filter when the capacitors C _{1 to} C _m are not provided. Has been done.

The controller 14 also controls the transmission gates F _{1 to} F _m when the power is turned on or reset.
Transmission gate F ₁ to switch to ON
It adapted to provide a control signal CTL ₁ ~CTL _m in to F _m.

Further, the transmission gates F ₁ ^{* to} F
_m ^* is adapted to be switched controlled with opposite polarity to the transmission gate F ₁ to F _m. That is, when the transmission gates F _{1 to} F _m are ON, the transmission gates F ₁ ^{* to} F _m ^* are switched to OFF,
When the transmission gates F _{1 to} F _m are off,
The transmission gates F ₁ ^{* to} F _m ^* can be turned on.

In the configuration of FIG. 7, when the power is turned on or reset, the transmission gates F _{1 to} F _m are turned off (non-conducting state) and the capacitors C _{1 to} C _m are controlled by the controller 14 for a predetermined period. Switches to a state of being separated from the loop filter 3. As a result, the loop filter 3 has the loop filter elements 3a, 3
It becomes equivalent to that constituted by b and 3c, and the voltage controlled oscillator is controlled by the constants determined by the loop filter elements 3a, 3b and 3c. In this case, the capacitor 3c
Is set to a value such that its capacitance value is small and the damping factor of the loop filter is small, so
The frequency pull-in time can be shortened. Further, during the period in which the transmission gates F _{1 to} F _m are off and the above operation is performed, the transmission gate F
₁ ^* to F _m ^* is a ON, therefore, the capacitor C ₁
While C _m is disconnected from the capacitor 3c,
The capacitors C _{1 to} C _m are charged to a specified voltage by the voltage follower 15.

After the lapse of the predetermined period, the controller 12 turns on the transmission gates F _{1 to} F _m . Also, the transmission gate F ₁ ^{* to} F _m ^*
To OFF. Thereby, the capacitors C _{1 to} C _m
, The loop filter 3 is substantially switched to the one in which the pre-charged capacitors C _{1 to} C _m are added to the loop filter elements 3a, 3b, 3c. That is, it switched to the one capacitor C ₁ -C _m is connected in parallel with the capacitor 3c. Here, the predetermined period is set to a period sufficient for the voltage from the loop filter 3 to reach the specified voltage of the voltage controlled oscillator corresponding to the frequency at which the phase is locked. Therefore, when the above-mentioned predetermined period elapses, PL
The L circuit is considered to be in a steady state, and the controller 1
2 turns ON the transmission gates F _{1 to} F _m , the loop filter 3 is switched to a capacitor in which the capacitors C _{1 to} C _m are connected in parallel.

By the way, in the steady state, if the capacitance of the capacitor remains small, the damping factor is small and unstable, and when the charge pump signal is converted to a direct current, a high frequency component cannot be removed sufficiently. . Therefore, in the example of FIG. 7, when the transmission gates F _{1 to} F _m are OFF and the capacitors C _{1 to} C _m are separated from the capacitor 3 c, the capacitors C ₁ to
C _m is precharged to a specified voltage by the voltage follower 15, the transmission gates F _{1 to} F _m are turned on, and the voltage controlled oscillator 4 is controlled by the specified voltage, that is, the PLL circuit enters a steady state. When the capacitors C ₁ to C are charged to a specified voltage in advance by the voltage follower 15,
By adding _m in parallel to the capacitor 3c, the damping factor can be increased, stabilization can be achieved, and the charge pump signal can be sufficiently converted to DC. In the example of FIG. 7, all the capacitors are not provided with the control of the transmission gates F _{1 to} F _m ,
Was provided a capacitor 3c that are not controlled by the transmission gate, and to produce a signal voltage follower, the transmission gates F ₁ to F _m are all O
This is to prevent one terminal of the resistor 3b on the capacitor side from being in a floating state when it becomes FF.

As described above, in the example of FIG. 7, the switch means 11 keeps the resistance values of the resistors 3a and 3b of the loop filter element fixed / invariable and makes the capacitance value of the capacitor 3c substantially variable. Is configured for a predetermined period,
By substantially reducing the capacitance value of the capacitor 3c of the loop filter element to reduce the damping factor,
It is possible to speed up frequency acquisition. That is, also with the configuration of FIG. 7, it is possible to increase the frequency pulling speed without increasing the circuit scale to a large extent.

FIG. 8 is a diagram showing still another specific example of the switch means 11 of FIG. 5. In the example of FIG. 8, the switch means 11 is a combination of the configuration of FIG. 6 and FIG. Has become. That is, the transmission gate S
₁ to S _m, and has a loop filter provided with the both resistors and capacitors are controlled by the F ₁ to F _m.

In the example of FIG. 8, both the resistance value of the resistor 3b and the capacitance value of the capacitor 3c of the loop filter element can be made substantially variable. For example, during a predetermined period, the loop filter 3 is set to the loop filter elements 3a, 3
b, 3c, the frequency pull-in time is shortened by a small damping factor, and after a lapse of a predetermined period, the loop filter elements 3a, 3b, 3c have resistors R _{1 to} R _n and capacitors C ₁ to. _Cm can be further loaded to further improve the stability in the steady state.

In the configuration examples of FIGS. 5 to 8, the switch means 11 is provided in the loop filter 3. In this case, the entire loop filter 3 including the switch means 11 should be configured by one IC. You can However, the switch means 11 does not necessarily have to be provided in the loop filter 3, and the switch means 11 may be provided in the existing (conventional general) PL.
It can be easily provided externally to the loop filter 3 of the L circuit.

It is also possible to combine the first configuration example and the second configuration example. FIG. 9 is a diagram showing a combination of the example of FIG. 4 and the example of FIG. 7. That is, in the configuration example of FIG. 9, when the reset signal becomes effective, a charging unit 7 that charges the capacitor 3c of the loop filter 3 for a predetermined period Tc and a plurality of loop filter elements having different loop constants are formed. In addition, it is configured to include both of the switching means 11 which is switch-controlled to be incorporated in the phase control loop. In other words, the present invention may have at least one function of the first configuration example shown in FIG. 1 and the second configuration example shown in FIG.

Further, in the above-mentioned respective configuration examples (configuration examples of FIGS. 1 to 9), when the loop filter 3 is constituted by, for example, an IC, the capacitor 3c of the loop filter 3 and further the capacitors C _{1 to} C _m are Although it can be formed as a channel-doped capacitor, it is even better to form as a channel-undoped capacitor. FIG. 10 and FIG. 11 show the device structure and CV characteristics of the channel-doped capacitor, respectively. In addition, FIG. 12 and FIG. 13 show the device structure and CV characteristics of a channel undoped capacitor, respectively.

First, referring to FIGS. 10 and 11, a normal channel-doped capacitor has, for example, an n-type well region in which a channel region CH doped with a predetermined impurity is further formed. However, the channel-doped capacitor has a large capacitance value when the gate bias is in the vicinity of 0 [V] due to the bias dependency as shown in FIG. 11A. Therefore, when such a channel-doped capacitor is used in a PLL circuit, P
The stability of the LL circuit deteriorates.

On the other hand, referring to FIGS. 12 and 13, in the channel undoped type capacitor (capacitor in which the channel region is not formed as in FIG. 12), as shown in FIG. Is approximately 0 [V]), the capacitance value is almost constant. Therefore, by using such a channel undoped capacitor in the PLL circuit, the PLL circuit can be operated stably. In this way, when the loop filter 3 is constituted by, for example, an IC, the capacitor 3c of the loop filter 3 and further the capacitor C ₁
Although C _m can be formed as a channel-doped capacitor, it is even better to be formed as a channel-undoped capacitor.

In the above example, the PLL circuit of the present invention has been described as being used for the clock circuit of the LSI, but it can be applied to various applications other than the clock circuit, for example, a communication device. Further, in the above example, the lag lead type is used as the loop filter 3,
The loop filter 3 is not limited to the lag lead type, and any type can be used.

[0059]

As described above, according to the first to ninth aspects of the present invention, the frequency pull-in time at power-on or reset is shortened without increasing the circuit scale to a large extent. Moreover, it is possible to obtain a PLL circuit that operates stably in the steady state.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a charge pump and a low-pass filter (loop filter) of a conventional general PLL circuit.

FIG. 2 is a phase-locked loop circuit (P
It is a figure which shows the 1st structural example of a (LL circuit).

FIG. 3 is a diagram showing a configuration example of a charging means of the PLL circuit of FIG.

FIG. 4 is a diagram showing another configuration example of the charging means of the PLL circuit of FIG.

FIG. 5 is a phase-locked loop circuit (P
It is a figure which shows the 2nd structural example of a (LL circuit).

FIG. 6 is a diagram showing a specific example of the switch means of FIG.

FIG. 7 is a diagram showing another specific example of the switch means of FIG.

FIG. 8 is a diagram showing another specific example of the switch means of FIG.

FIG. 9 is a phase-locked loop circuit (P
It is a figure which shows the other structural example of (LL circuit).

FIG. 10 is a diagram showing a device structure of a channel-doped capacitor.

FIG. 11 is a diagram showing CV characteristics of a channel-doped capacitor.

FIG. 12 is a diagram showing a device structure of a channel undoped capacitor.

FIG. 13 C-V of channel undoped capacitor
It is a figure showing a characteristic.

FIG. 14 is a diagram showing a conventional phase-locked loop circuit.

[Explanation of symbols]

1 phase comparator 2 charge pump 3 loop filter 3a, 3b loop filter element (resistor) 3c loop filter element (capacitor) 4 voltage controlled oscillator 6 second frequency divider 7 charging means 8 one-shot circuit 9 charging element 11 switch means 12, 14 controller 100 signal generator 102 first divider R ₁ to R _n resistance C ₁ -C _n capacitors S ₁ to S _n transmission gate F ₁ to F _m transmission gates F ₁ ^* to F _m ^* transmission Gate

Claims (9)

[Claims] 1. A frequency division means for generating a frequency division frequency signal,
Phase comparison means for generating a phase difference output based on the frequency and phase difference between the reference frequency signal and the frequency division frequency signal from the frequency division means, a voltage control oscillation means, and a voltage control based on the phase difference output from the phase comparison means. In a phase-locked loop circuit having a control voltage generating means for generating a control voltage for controlling the oscillation frequency of the oscillating means, and giving an output signal from the voltage controlled oscillating means to the frequency dividing means to form a feedback loop, The control voltage generating means includes a loop filter for waveform-shaping the control voltage to the voltage controlled oscillating means and a charging means for charging a capacitor of the loop filter for a predetermined period when a reset signal becomes effective. And a phase-locked loop circuit. 2. The phase-locked loop circuit according to claim 1, wherein the predetermined period is set to a time sufficient to charge the capacitor of the loop filter up to the voltage of the voltage-controlled oscillation means corresponding to the phase-locked frequency. A phase-locked loop circuit characterized by that. 3. Dividing means for generating a divided frequency signal,
Phase comparison means for generating a phase difference output based on the frequency and phase difference between the reference frequency signal and the frequency division frequency signal from the frequency division means, a voltage control oscillation means, and a voltage control based on the phase difference output from the phase comparison means. In a phase-locked loop circuit having a control voltage generating means for generating a control voltage for controlling the oscillation frequency of the oscillating means, and giving an output signal from the voltage controlled oscillating means to the frequency dividing means to form a feedback loop, The control voltage generation means has a loop filter element for waveform-shaping the control voltage to the voltage controlled oscillation means, and a switch means for variably setting a filter constant determined by the loop filter element. A phase control loop characterized in that a phase control loop having different loop constants can be formed by switching the means. Loop circuit. 4. The phase-locked loop circuit according to claim 3, wherein the loop filter element has a capacitor and a resistance, and the switch means makes the resistance value of the resistance of the loop filter element variable. Phase-locked loop circuit characterized by being configured. 5. The phase-locked loop circuit according to claim 3, wherein the loop filter element has a capacitor and a resistor, and the switch means makes the capacitance value of the capacitor of the loop filter element variable. Phase-locked loop circuit characterized by being configured. 6. The phase-locked loop circuit according to claim 3, wherein the loop filter element has a capacitor and a resistor, and the switch means has a resistance value of the resistance of the loop filter element and a capacitance value of the capacitor. And a phase-locked loop circuit characterized by being configured to be variable. 7. The phase-locked loop circuit according to claim 3, wherein the control voltage generating means is formed by an IC. 8. The phase-locked loop circuit according to claim 7, wherein the capacitor of the loop filter element formed inside the IC is a channel undoped type capacitor. 9. A frequency division means for generating a frequency division frequency signal,
Phase comparison means for generating a phase difference output based on the frequency and phase difference between the reference frequency signal and the frequency division frequency signal from the frequency division means, a voltage control oscillation means, and a voltage control based on the phase difference output from the phase comparison means. In a phase-locked loop circuit having a control voltage generating means for generating a control voltage for controlling the oscillation frequency of the oscillating means, and giving an output signal from the voltage controlled oscillating means to the frequency dividing means to form a feedback loop, The control voltage generating means variably sets a filter constant determined by the loop filter element and a loop filter element for waveform-shaping the control voltage to the voltage controlled oscillating means, and a phase control loop having different loop constants. Switch means for forming and charging the capacitor of the loop filter element for a predetermined period when the reset signal becomes valid. Phase-locked loop circuit characterized by comprising a charging means for.