JP2017195456A - PLL frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer capable of achieving a desired transfer function with ease.SOLUTION: A PLL frequency synthesizer 1 comprises a reference oscillator 10, a phase comparator 20, a charge pump 30, a loop filter 40, a voltage-controlled oscillator 50, a frequency divider 60, a setting unit 70, a detector 80, and a controller 90. The detector 80 detects a change speed of a control voltage value at the time when a constant current outputted from the charge pump 30 is inputted to the loop filter 40. The controller 90 adjusts a charge and discharge current Icp outputted from the charge pump 30, characteristics of the loop filter 40, or characteristics of the voltage-controlled oscillator 50, on the basis of the detection result by the detector 80.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a PLL frequency synthesizer.

  In general, a PLL (Phase Locked Loop) frequency synthesizer includes a voltage controlled oscillator (VCO), a phase comparison unit, a charge pump, and a loop filter, which constitute a loop. The PLL frequency synthesizer can output an oscillation signal having a frequency obtained by multiplying the frequency of the reference oscillation signal by a constant.

  The PLL frequency synthesizer operates as follows. A control voltage value is input to the voltage controlled oscillator, and an oscillation signal having a frequency corresponding to the control voltage value is output from the voltage controlled oscillator. An oscillation signal output from the voltage controlled oscillator or a signal obtained by dividing the oscillation signal is input to the phase comparison unit as a feedback oscillation signal. A reference oscillation signal is also input to the phase comparison unit. The phase comparator detects the phase difference between the feedback oscillation signal and the reference oscillation signal, and outputs a phase difference signal representing the detected phase difference.

  A charge / discharge current corresponding to the phase difference represented by the phase difference signal is output from the charge pump that receives the phase difference signal. This charge / discharge current is input to the loop filter. For example, the loop filter includes a resistor and a capacitive element connected in series with each other, and also includes another capacitive element provided in parallel thereto. The control voltage value output from the loop filter is input to the voltage controlled oscillator. In this way, an oscillation signal having a frequency obtained by multiplying the frequency of the reference oscillation signal by a constant is output from the PLL frequency synthesizer.

  The transfer function of the PLL frequency synthesizer configured as described above has a characteristic based on the resistance value of the resistor of the loop filter and the capacitance value of the capacitive element, the characteristic of the voltage controlled oscillator (between the control voltage value and the frequency of the oscillation signal). Relationship) and the charge / discharge current of the charge pump. For example, when a resistor and a capacitive element are formed on a semiconductor substrate, the resistance value of the resistor may vary by about ± 15%, and the capacitance value of the capacitive element may vary by about ± 10%. If there is such a variation in characteristics, the actual transfer function of the PLL frequency synthesizer may not have the cutoff frequency and peak gain as designed, and may not satisfy the required specifications.

  Patent Documents 1 and 2 disclose inventions intended to solve such problems. The invention disclosed in Patent Document 1 monitors a control voltage value input to a voltage controlled oscillator, compares the control voltage value with a reference voltage value, and determines the output current of the charge pump based on the comparison result. Adjust the characteristics of the voltage controlled oscillator. The invention disclosed in Patent Document 2 adjusts the characteristics of a voltage controlled oscillator using a frequency divider that divides an oscillation signal output from a voltage controlled oscillator to generate a feedback oscillation signal.

US Pat. No. 7,772,930 US Pat. No. 8,483,985

  In the invention disclosed in Patent Document 1, the reference voltage value may vary due to variations in the characteristics of resistors and the like, and the variation in the reference voltage affects the adjustment result. Therefore, the actual transfer function of the PLL frequency synthesizer It is not easy to make it as designed.

  In the invention disclosed in Patent Document 2, since the characteristics of the voltage controlled oscillator are adjusted using a frequency divider, the frequency of the oscillation signal changes due to the adjustment. It may be necessary to set a division ratio that cannot be realized by the frequency divider. Further, when it is desired to make the frequency of the output oscillation signal the same as the frequency of the reference oscillation signal, the frequency of the oscillation signal varies by inserting a frequency divider for adjustment.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a PLL frequency synthesizer that can easily realize a desired transfer function.

  The PLL frequency synthesizer of the present invention includes: (1) a voltage controlled oscillator that inputs a control voltage value and outputs an oscillation signal having a frequency corresponding to the control voltage value; and (2) an oscillation signal output from the voltage controlled oscillator. Alternatively, a signal obtained by dividing the oscillation signal is input as a feedback oscillation signal, and a reference oscillation signal is also input, and a phase difference between the feedback oscillation signal and the reference oscillation signal is detected to represent this phase difference. A phase comparator that outputs a phase difference signal; and (3) a charge pump that inputs a phase difference signal output from the phase comparator and outputs a charge / discharge current corresponding to the phase difference represented by the phase difference signal; (4) a loop filter that includes a capacitive element that is charged / discharged by inputting a charge / discharge current output from the charge pump, and that outputs a control voltage value that is increased or decreased according to the charge / discharge amount to the voltage controlled oscillator; 5) Charge Po A detector that detects the rate of change of the control voltage value when the charge / discharge current output from the controller is input to the loop filter, and (6) the charge / discharge output from the charge pump based on the detection result of the detector A control unit that adjusts the current, the characteristics of the loop filter, or the characteristics of the voltage controlled oscillator.

  In the present invention, it is preferable that the detection unit detects the change speed of the control voltage value using the reference oscillation signal. It is preferable that the apparatus further includes a setting unit that sets the control voltage value to a predetermined value, and the detection unit detects a change speed of the control voltage value from the predetermined value. The setting unit preferably includes an amplifier having a voltage follower configuration.

  In the present invention, the charge pump includes a plurality of current sources provided in parallel, and the control unit outputs the current from the charge pump by changing the number of current sources to be used among the plurality of current sources of the charge pump. It is preferable to adjust the charging / discharging current. The loop filter includes a resistor that inputs a charge / discharge current output from the charge pump to the first end, and a capacitive element connected to the second end of the resistor, and the detection unit includes a first resistor of the resistor. It is preferable to detect the rate of change in the control voltage value by monitoring the potential at the end or the second end. The loop filter includes a resistor that inputs a charging / discharging current output from the charge pump to the first end, and a capacitive element that is connected to the second end of the resistor. It is also preferable that the potential at the first end or the second end is set to a predetermined value, and the detection unit monitors the potential at the first end or the second end of the resistor to detect the change rate of the control voltage value. is there.

  In the present invention, the loop filter connects the first capacitor element, the second capacitor element having a capacitance value larger than the capacitance value of the first capacitor element, and the first capacitor element and the second capacitor element in parallel with each other. And the switch detects the rate of change of the control voltage value and adjusts the control unit in a state where the second capacitive element is disconnected by the switch. It is preferable to connect the second capacitor element in parallel to the first capacitor element.

  In the present invention, the charge pump includes a first charge pump and a second charge pump, and the loop filter has a capacitor connected to the output terminal of the first charge pump and a voltage value corresponding to the voltage value of the capacitor. An output amplifier; and a resistor having a first end connected to the output end of the amplifier and a second end connected to the output end of the second charge pump. The control voltage value is voltage-controlled from the second end. It is preferable that the control unit adjusts the charge / discharge current output from the first charge pump.

  In the present invention, the voltage controlled oscillator includes a capacitive element having a capacitance value that changes according to the control voltage value, and is an LC-VCO type that outputs an oscillation signal having a frequency according to the capacitance value of the capacitive element. It is preferable that the control unit adjusts the characteristics of the voltage controlled oscillator by changing the dependency of the capacitance value of the capacitive element on the control voltage value.

  In the present invention, the voltage controlled oscillator has a configuration in which a plurality of inverter circuits are connected in a ring shape, and is a Ring-VCO type that outputs an oscillation signal having a frequency corresponding to the current supplied to these inverter circuits. It is preferable that the control unit adjusts the characteristics of the voltage controlled oscillator by changing the dependency of the current supply amount to the inverter circuit on the control voltage value.

  The PLL frequency synthesizer of the present invention can easily realize a desired transfer function even if PLL parameters (for example, resistance value, capacitance value, charge pump current, etc.) do not become a desired value due to manufacturing variations. it can.

FIG. 1 is a diagram showing a configuration of a PLL frequency synthesizer 1. FIG. 2 is a diagram showing a phase domain model of the PLL frequency synthesizer 1. FIG. 3 is a diagram for explaining an example of the adjustment operation by the control unit 90 of the PLL frequency synthesizer 1. FIG. 4 is a diagram illustrating a configuration example of the setting unit 70 and the detection unit 80. FIG. 5 is a diagram illustrating a configuration example of the charge pump 30. FIG. 6 is a diagram illustrating a configuration example of the loop filter 40. FIG. 7 is a diagram illustrating another configuration example of the loop filter 40. FIG. 8 is a diagram showing still another configuration of the loop filter 40. FIG. 9 is a diagram illustrating the state machine SCPCC. FIG. 10 is a table summarizing output settings in each state in the state machine SCPCC. FIG. 11 is a diagram illustrating the state machine SCPCCNT. FIG. 12 is a table summarizing output settings in each state in the state machine SCPCCNT. FIG. 13 is a diagram showing the slate machine SCPCTL. FIG. 14 is a diagram illustrating the state machine SCSG. FIG. 15 is a table summarizing output settings in each state in the state machine SCSG. FIG. 16 is a diagram illustrating a configuration example of the loop filter 40. FIG. 17 is a diagram illustrating a configuration example of the loop filter 40. FIG. 18 is a diagram illustrating a configuration example of the loop filter 40.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. The present invention is not limited to these exemplifications, but is defined by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

  FIG. 1 is a diagram showing a configuration of a PLL frequency synthesizer 1. The PLL frequency synthesizer 1 includes a reference oscillator 10, a phase comparison unit 20, a charge pump 30, a loop filter 40, a voltage control oscillator 50, a frequency divider 60, a setting unit 70, a detection unit 80, and a control unit 90.

  The reference oscillator 10 includes a crystal resonator, for example, and outputs a reference oscillation signal having a constant frequency stabilized with high accuracy to the phase comparison unit 20. The phase comparison unit 20 inputs this reference oscillation signal. In addition, the phase comparison unit 20 receives the feedback oscillation signal output from the frequency divider 60. The phase comparison unit 20 detects a phase difference between the feedback oscillation signal and the reference oscillation signal, and outputs a phase difference signal representing this phase difference to the charge pump 30. The phase difference signal indicates which phase of the reference oscillation signal or the feedback oscillation signal is advanced.

  The charge pump 30 receives the phase difference signal output from the phase comparison unit 20 and outputs a charge / discharge current corresponding to the phase difference represented by the phase difference signal to the loop filter 40. The charge / discharge current output from the charge pump 30 to the loop filter 40 has a different polarity depending on which phase of the reference oscillation signal and the feedback oscillation signal is advanced. The loop filter 40 includes a capacitive element that is charged and discharged by inputting the charge / discharge current output from the charge pump 30, and outputs a control voltage value that is increased or decreased according to the charge / discharge amount to the voltage controlled oscillator 50. The loop filter 40 includes a resistor in addition to the capacitive element.

  The voltage controlled oscillator 50 receives the control voltage value output from the loop filter 40 and outputs an oscillation signal having a frequency corresponding to the control voltage value. The frequency divider 60 receives the oscillation signal output from the voltage controlled oscillator 50, divides the oscillation signal by N, generates a feedback oscillation signal, and outputs the feedback oscillation signal to the phase comparison unit 20.

  The phase comparison unit 20, the charge pump 30, the loop filter 40, the voltage controlled oscillator 50, and the frequency divider 60 constitute a loop. In this loop, charge / discharge current is input from the charge pump 30 to the loop filter 40 so that the phase difference between the reference oscillation signal input to the phase comparison unit 20 and the feedback oscillation signal is small. When the operation of this loop is stable, the oscillation signal output from the voltage controlled oscillator 50 has a frequency that is N times the frequency of the reference oscillation signal. The frequency divider 60 may not be provided, and in this case, the oscillation signal output from the voltage controlled oscillator 50 has the same frequency as the frequency of the reference oscillation signal.

  Details of the setting unit 70, the detection unit 80, and the control unit 90 will be described later.

  FIG. 2 is a diagram showing a phase domain model of the PLL frequency synthesizer 1. The open loop characteristic H (s) of the PLL frequency synthesizer 1 is expressed by the following equation (1). Kvco indicates the characteristic of the voltage controlled oscillator 50 (dependence of the frequency of the oscillation signal on the control voltage value). Kp is a proportional term of the loop filter 40 and is expressed by the following equation (2). Ki is an integral term of the loop filter 40 and is expressed by the following equation (3). R is the resistance value of the resistor of the loop filter 40. C is a capacitance value of the capacitive element of the loop filter 40.

  Icpp is a current that contributes to the proportional term in the charge / discharge current Icp supplied from the charge pump 30 to the loop filter 40. Icpi is a current that contributes to the integral term in the charge / discharge current Icp supplied from the charge pump 30 to the loop filter 40. Usually, there may be a relationship of the following formula (4).

  Generally, the current output from the charge pump 30 is generated based on a voltage value Vref supplied from a BGR (Band Gap Reference) block. The charge / discharge current Icp applied from the charge pump 30 to the loop filter 40 is expressed by the following equation (5).

  When this equation (5) is used, the above equation (2) becomes the following equation (6). As can be seen from the equation (6), the proportional term Kp of the loop filter 40 does not depend on either the resistance value R or the capacitance value C. Since the voltage value Vref supplied from the BGR block is excellent in stability, the proportional term Kp of the loop filter 40 is excellent in stability.

  Further, when the above equation (5) is used, the above equation (3) becomes the following equation (7). As can be seen from the equation (7), the integral term Ki of the loop filter 40 depends on both the resistance value R and the capacitance value C. Therefore, when the resistance value R or the capacitance value C varies, the integral term Ki of the loop filter 40 also varies.

  When the open loop characteristic H (s) of the PLL frequency synthesizer 1 fluctuates due to the variation of the resistance value R or the capacitance value C in this way, the actual transfer function of the PLL frequency synthesizer 1 has a cutoff frequency or peak as designed. It may not have gain and may not meet the required specifications. In order to solve such problems, the PLL frequency synthesizer 1 of the present embodiment includes a setting unit 70, a detection unit 80, and a control unit 90, and facilitates the realization of a desired transfer function.

  The detection unit 80 detects the change speed of the control voltage value when a constant current output from the charge pump 30 is input to the loop filter 40. The detector 80 may measure the control voltage values V1 and V2 at any two times t1 and t2. The detection unit 80 may measure a time t2 at which the control voltage value changes by a predetermined ΔV and becomes V2 after the setting unit 70 sets the control voltage value to the initial value V1 at the time t1. Further, the detection unit 80 may measure the control voltage value V2 at time t2 after a fixed time Δt has elapsed from time t1 when the setting unit 70 sets the control voltage value to the initial value V1. In either case, the change rate ΔV / Δt of the control voltage value is expressed by the following equation (8).

  The control unit 90 controls the overall operation of the PLL frequency synthesizer 1. In particular, the control unit 90 determines the charge / discharge current Icp output from the charge pump 30 and the characteristics of the loop filter 40 (particularly the resistance value R of the resistor and the capacitance value C of the capacitive element) based on the detection result by the detection unit 80. Characteristic) or the characteristic Kvco of the voltage controlled oscillator 50 (dependence of the frequency of the oscillation signal on the control voltage value) is adjusted.

  FIG. 3 is a diagram for explaining an example of the adjustment operation by the control unit 90 of the PLL frequency synthesizer 1. In this figure, the horizontal axis indicates time, and the vertical axis indicates the control voltage value. Further, in this figure, each of the three straight lines A, B, and C indicates a change speed of the control voltage value different from each other. Assuming that the change speed of the control voltage value indicated by the straight line A is preferable, the change speed of the control voltage value indicated by the straight line B is slow, and the change speed of the control voltage value indicated by the straight line C is fast. The control unit 90 performs adjustment so that a preferable change speed of the control voltage value indicated by the straight line A is obtained.

  An example of the adjustment operation by the control unit 90 of the PLL frequency synthesizer 1 is as follows. In the first step, the control unit 90 causes the setting unit 70 to set the control voltage value to V1. In the subsequent second step, the control unit 90 outputs the phase difference signal from the phase comparison unit 20 over a certain time Δt, and supplies the loop filter 40 with the constant current Icp output from the charge pump 30. In the second step to be performed first, the current amount is set to a minimum value that can be set.

  In the subsequent third step, the control unit 90 acquires the control voltage value measured by the detection unit 80 after the end of the second step. In the fourth step, when the control unit 90 determines that the control voltage value measured in the third step does not exceed the predetermined value V2, the control unit 90 increases the set value of the current Icp and the first step and thereafter. repeat. When the control unit 90 determines that the control voltage value measured in the third step exceeds the predetermined value V2, the control unit 90 ends the adjustment operation.

  In this operation example, the initial value of the current Icp is gradually increased as the settable minimum value, but the present invention is not limited to this. The current Icp may be gradually decreased with the initial value of the current Icp as a maximum value that can be set. Further, if the initial value of the current Icp is an arbitrary value, and the control voltage value measured in the third step at this initial value is less than the predetermined value V2, the current Icp is gradually increased. Sometimes, if the control voltage value measured in the third step exceeds the predetermined value V2, the current Icp may be gradually decreased.

  The time Δt during which the current is supplied from the charge pump 30 to the loop filter 40 can be monitored using a counter that counts the pulses of the reference oscillation signal (or other signal with a stable frequency) output from the reference oscillator 10. it can. That is, the time Δt can be obtained from the following equation (9) from the count value M by the counter and the frequency F of the reference oscillation signal.

  The current Icpi supplied from the charge pump 30 to the loop filter 40 is a voltage difference ΔV between the time Δt during which current is supplied from the charge pump 30 to the loop filter 40, the initial value V1 of the control voltage value, and the predetermined value V2 at the end of adjustment. And the capacitance value C of the capacitive element of the loop filter 40 is expressed by the following (10). Using this equation (10), the above equation (3) becomes the following equation (11).

  Since the voltage difference ΔV is generated by the BGR block, the variation is small. Since the time Δt is obtained using the reference oscillation signal output from the reference oscillator 10, the variation is small. Equation (11) does not depend on either the resistance value R or the capacitance value C. By adjusting the current Icpi, the change rate of the control voltage value can be set to a desired value, and the integral term Ki can be set to the desired value.

  FIG. 4 is a diagram illustrating a configuration example of the setting unit 70 and the detection unit 80. The setting unit 70 includes an amplifier 71 and a switch 72. The amplifier 71 has two input ends and one output end, the voltage value V1 is input to one input end, and the other input end is connected to the output end. The amplifier 71 has a voltage follower configuration. The first end of the switch 72 is connected to the output end of the amplifier 71, and the second end of the switch 72 is connected to a location where the control voltage value should be set to V1. The opening / closing operation of the switch 72 is controlled by a VCFIXp signal output from the control unit 90.

  The detection unit 80 includes an amplifier 81. The amplifier 81 has two input ends and one output end, the voltage value V2 is input to one input end, the control voltage value is input to the other input end, and the VCH signal is output from the output end to the control unit 90. Output to. The amplifier 81 sets the VCH signal to a low level if the control voltage value is equal to or lower than V2, and sets the VCH signal to a high level if the control voltage value exceeds V2.

  The control unit 90 sets the control voltage value to the initial value V1 by turning on the switch 72 of the setting unit 70 for a certain period by the VCFIXp signal. The control unit 90 turns the switch 72 to the OFF state at time t1, and detects the level of the VCH signal output from the amplifier 81 of the detection unit 80 at the subsequent time t2. Based on the level of the VCH signal, the control unit 90 can determine whether the change rate of the control voltage value is larger or smaller than the target value.

FIG. 5 is a diagram illustrating a configuration example of the charge pump 30. The charge pump 30 includes current sources 31 _{1 to} 31 _K , current sources 32 _{1 to} 32 _K , switches 33 _{1 to} 33 _K , switches 34 _{1 to} 34 _K , a switch 35, and a switch 36. K is an integer of 2 or more, and k is an integer of 1 or more and K or less.

The current source 31 _k and the switch 33 _k are connected in series with each other and are provided between the high-potential power supply potential and the switch 35. The current source 32 _k and the switch 34 _k are connected in series to each other and are provided between the low-potential ground potential and the switch 36. A connection point between the switch 35 and the switch 36 is connected to the loop filter 40.

The open / close states of the switches 33 _{1 to} 33 _K and the switches 34 _{1 to} 34 _K are set by a CPSetting signal output from the control unit 90. The opening / closing operation of each of the switch 35 and the switch 36 is controlled by a phase difference signal (UP signal, DOWN signal) output from the phase comparison unit 20. The switches 35 and 36 are not turned on at the same time.

When the switch 35 is on, the capacitive element of the loop filter 40 is charged. The amount of charge at that time corresponds to the number of switches that are in the on state among the switches 33 _{1 to} 33 _K. Further, when the switch 36 is in the on state, the capacitive element of the loop filter 40 is discharged. The amount of discharge at that time corresponds to the number of switches that are in the ON state among the switches 34 _{1 to} 34 _K.

Control unit 90, by CPSetting signal, while adjusting the number of switches in the ON state among the switches ₃₃ 1 ~ 33 _K, by adjusting the number of switches in the ON state among the switches ₃₄ 1 to 34C _K, The charge / discharge current Icp supplied from the charge pump 30 to the loop filter 40 can be adjusted.

  FIG. 6 is a diagram illustrating a configuration example of the loop filter 40. The loop filter 40 shown in this figure includes a resistor 41 and a capacitive element 42. The charge / discharge current output from the charge pump 30 is input to the first end of the resistor 41. A second end of the resistor 41 is connected to the capacitive element 42. In the loop filter 40 having such a configuration, the setting unit 70 sets the second end of the resistor 41 (the connection point between the resistor 41 and the capacitive element 42) to the initial value V1, and the detection unit 80 includes the resistor It is preferable to detect the voltage value at the second end of 41 as the control voltage value.

  If the resistance value of the resistor 41 is variable, the control unit 90 can adjust the characteristic of the loop filter 40 by adjusting the resistance value. If the capacitance value of the capacitive element 42 is variable, the control unit 90 can adjust the characteristic of the loop filter 40 by adjusting the capacitance value.

  As shown in FIG. 16, the setting unit 70 sets the second end of the resistor 41 to the initial value V1, and the detection unit 80 uses the voltage value at the first end of the resistor 41 as the control voltage value. It may be detected. As shown in FIG. 17, the setting unit 70 sets the first end of the resistor 41 to the initial value V1, and the detection unit 80 detects the voltage value of the second end of the resistor 41 as the control voltage value. May be. 18, the setting unit 70 sets the first end of the resistor 41 to the initial value V1, and the detection unit 80 uses the voltage value at the first end of the resistor 41 as the control voltage value. It may be detected.

  FIG. 7 is a diagram illustrating another configuration example of the loop filter 40. The loop filter 40 shown in this figure includes a capacitive element 43 and a switch 44 in addition to the resistor 41 and the capacitive element 42. The switch 44 is provided between the connection point between the resistor 41 and the capacitive element 42 and the capacitive element 43. When the switch 44 is in the on state, the capacitive element 42 and the capacitive element 43 are connected in parallel to each other. The capacitance value of the capacitive element 43 is larger than the capacitance value of the capacitive element 42.

  The open / close state of the switch 44 is set by a signal output from the control unit 90. When the switch 44 is in the off state, the capacitance value of the loop filter 40 is small, and when the switch 44 is in the on state, the capacitance value of the loop filter 40 is large. The controller 90 performs adjustment with the switch 44 turned off, and turns the switch 44 on after completion of the adjustment.

  The configuration of the loop filter 40 shown in FIG. 7 is useful in the following cases. That is, in order to reduce the influence of input jitter, it is preferable to lower the cut-off frequency of the loop filter. In this case, a capacitive element having a large capacitance value is used. If the capacitance value of the loop filter is large, the change rate of the control voltage value becomes slow, and the time Δt required for the control voltage value to change from the initial value V1 to V2 by ΔV becomes long. For example, ΔV is 0.5 V, the capacitance value is 220 pF, and the current Icp output from the charge pump is 20 μA. At this time, the time Δt is 5.5 μs. The circuit scale of the counter that performs counting over a long time of 5.5 μs is large. Although it is possible to perform time measurement with an analog circuit using a resistor and a capacitor, it is not practical because there are several tens of% of variations in the resistor and the capacitance value.

  In such a case, in order to shorten the time required for the adjustment, the adjustment time is shortened (for example, shortened to several tens of ns) by reducing the capacitance value by turning off the switch 44 when performing the adjustment. ). Then, the influence of input jitter can be reduced by increasing the capacitance value by turning on the switch 44 after the adjustment is completed.

  FIG. 8 is a diagram showing still another configuration of the loop filter 40. In the configuration shown in this figure, a first charge pump 30A and a second charge pump 30B are provided as charge pumps. The loop filter 40 includes a capacitive element 45, an amplifier 46 and a resistor 47.

  The capacitive element 45 is provided between the output terminal of the first charge pump 30A and the ground potential terminal. The amplifier 46 has two input ends and one output end, the voltage value of the capacitive element 45 is input to one input end, and the other input end is connected to the output end. The amplifier 46 has a voltage follower configuration. The amplifier 46 outputs a voltage value corresponding to the voltage value of the capacitive element 45 from the output terminal. The first end of the resistor 47 is connected to the output end of the amplifier 46, and the second end of the resistor 47 is connected to the output end of the second charge pump 30B. The potential at the second end of the resistor 47 is output to the voltage controlled oscillator 50 as a control voltage value.

  The first charge pump 30 </ b> A outputs a charge / discharge current that contributes to the integral term of the loop filter 40. The second charge pump 30B outputs a charge / discharge current that contributes to the proportional term of the loop filter 40. The controller 90 adjusts the charge / discharge current output from the first charge pump 30A.

  If the resistance value of the resistor 47 is variable, the control unit 90 can adjust the characteristic of the loop filter 40 by adjusting the resistance value. If the capacitance value of the capacitive element 45 is variable, the control unit 90 can adjust the characteristic of the loop filter 40 by adjusting the capacitance value.

  The controller 90 may adjust the characteristic Kvco of the voltage controlled oscillator 50. When voltage controlled oscillator 50 is of the LC-VCO type, that is, it includes a capacitive element having a capacitance value that changes according to the control voltage value, and outputs an oscillation signal having a frequency according to the capacitance value of this capacitive element In the case of the type to be used, the control unit 90 can adjust the characteristics of the voltage controlled oscillator 50 by changing the dependency of the capacitance value of the capacitive element on the control voltage value. The capacitive element may be a varactor or may have a configuration in which the drain and source of the MOS transistor are connected to each other. Adjustment of the capacitance value of the capacitive element is possible by providing a plurality of sets in parallel with one set of capacitive elements and switches connected in series, and adjusting the number of ON switches among the plurality of switches. is there.

  When the voltage controlled oscillator is of the Ring-VCO type, that is, it has a configuration in which a plurality of inverter circuits are connected in a ring shape, and outputs an oscillation signal having a frequency corresponding to the current supplied to these inverter circuits. In the case of the type, the control unit 90 can adjust the characteristics of the voltage controlled oscillator 50 by changing the dependency of the current supply amount to the inverter circuit on the control voltage value.

  In the present embodiment, the detection unit 80 detects the change rate of the control voltage value when the charge / discharge current output from the charge pump 30 is input to the loop filter 40, and based on the detection result, the charge pump 30 Since the controller 90 adjusts the output charge / discharge current, the characteristics of the loop filter 40, or the characteristics of the voltage controlled oscillator 50, a desired transfer function can be easily realized.

  That is, in the invention disclosed in Patent Document 1, since adjustment is performed based on the comparison result between the control voltage value and one reference voltage value, if the reference voltage value varies due to variations in characteristics of resistors or the like, the reference is made. The variation in voltage value affects the adjustment result, and it is not easy to make the actual transfer function of the PLL frequency synthesizer as designed. On the other hand, in this embodiment, even if the voltage values V1 and V2 vary due to variations in characteristics of resistors and the like, the variations do not affect the change rate (ΔV / Δt) of the control voltage value. A desired transfer function can be easily realized. In the present embodiment, since the amplifier 71 of the setting unit 70 and the amplifier 81 of the detection unit 80 can have the same characteristics, the influence of the offset of these amplifiers is also suppressed.

  In the invention disclosed in Patent Document 2, there arises a problem caused by adjusting the characteristics of the voltage controlled oscillator using a frequency divider. On the other hand, in the present embodiment, adjustment can be performed without using a frequency divider, so that a desired transfer function can be easily realized even in a configuration without a frequency divider.

  Next, the control by the control unit 90 in the PLL frequency synthesizer 1 of the present embodiment will be described in detail. Here, one mode of control by control unit 90 when adjusting charge / discharge current Icp of charge pump 30 in the configuration shown in FIGS. 1, 4, and 5 will be described. 9 to 15 are diagrams for explaining a state machine for explaining the control by the control unit 90.

  The control by the control unit 90 includes four state machines SCPCC, SCPCCNT, SCPCTL, and SCSG. The state machine SCPCC controls the entire adjustment operation, and controls the operations of the setting unit 70 and the detection unit 80, respectively. The state machine SCPCCNT controls the counting operation of the counter. The state machine SCPCTL controls the current output operation of the charge pump 30. The state machine SCSG determines the end of the adjustment operation.

  FIG. 9 is a diagram illustrating the state machine SCPCC. FIG. 10 is a table summarizing output settings in each state in the state machine SCPCC. The state machine SCPCC has four states WAIT, CAL, FIN, and TMP. If the variable FCNT is 0 in the WAIT state, it remains in the WAIT state, the VCFIXp signal becomes high level, the switch 72 of the setting unit 70 is turned on, and the control voltage value is set to the initial value V1.

  If the variable FCNT is 1 in the WAIT state, the state transitions from the WAIT state to the CAL state, the PFDENp signal becomes high level, the phase difference signal is output from the phase comparator 20, and the constant current output from the charge pump 30 Icp is supplied to the loop filter 40. If the variable CALAGAIN has a value of 1 in the CAL state, the CAL state transitions to the WAIT state. If the variable CALDNE is a value 1 in the CAL state, the state transitions from the CAL state to the FIN state. In the FIN state, both the VCFIXp signal and the PFDENp signal are at a low level, and normal operation is performed.

  FIG. 11 is a diagram illustrating the state machine SCPCCNT. FIG. 12 is a table summarizing output settings in each state in the state machine SCPCCNT. The state machine SCPCCNT controls the counting operation of the counter in the WAIT state or the CAL state. When the count value is not the predetermined number M, the FCNT variable has the value 0. When the count value reaches the predetermined number M, the FCNT variable becomes the value 1, and the state transitions. In addition, after the count value reaches the predetermined number M, the count value is initialized to zero.

  FIG. 13 is a diagram showing the slate machine SCPCTL. The slate machine SCPCTL controls the current Icp output operation of the charge pump 30 based on the value of the VCH signal output from the detection unit 80 in the CAL state. That is, if the VCH signal has a value of 0, it is determined that the change rate of the control voltage value is slow (that is, the current Icp is small), and the current Icp is increased. If the VCH signal is a value 1, it is determined that the change rate of the control voltage value is fast (that is, the current Icp is large), and the current Icp is decreased.

  FIG. 14 is a diagram illustrating the state machine SCSG. FIG. 15 is a table summarizing output settings in each state in the state machine SCSG. The state machine SCSG determines the end of the adjustment operation.

  If the VCH signal is 0 in the INIT state, the state transitions to the UP state, and the CALAGAIN signal goes high. If the VCH signal is 0 in the UP state, it remains in the UP state and the CALAGAIN signal goes high. If the VCH signal is 1 in the UP state, the state transits to the DNE state, and the CALDNE signal becomes high level.

  If the VCH signal is 1 in the INIT state, a transition is made to the DN state, and the CALAGAIN signal goes high. If the VCH signal is 1 in the DN state, it remains in the DN state and the CALAGAIN signal goes high. If the VCH signal is 0 in the DN state, the state transits to the DNE state, and the CALDNE signal goes high.

  That is, if the VCH signal remains at the value 0, or if the VCH signal remains at the value 1, it is determined that the adjustment is insufficient, the CALAGAIN variable becomes high level, and the CAL state changes to the WAIT state. Then, the adjustment operation is repeated (FIG. 9).

  On the other hand, when the VCH signal transitions from the value 0 to 1, or when the VCH signal transitions from the value 1 to 0, it is determined that the adjustment operation is completed, the state transitions to the DNE state, and the CALDNE signal becomes high level. Become. When the CALDNE signal goes high, the transition from the CAL state to the FIN state results in normal operation (FIG. 9).

  DESCRIPTION OF SYMBOLS 1 ... PLL frequency synthesizer, 10 ... Reference oscillator, 20 ... Phase comparison part, 30 ... Charge pump, 30A ... 1st charge pump, 30B ... 2nd charge pump, 40 ... Loop filter, 50 ... Voltage controlled oscillator, 60 ... minute Peripheral unit, 70 ... setting unit, 80 ... detection unit, 90 ... control unit.

Claims (11)

A voltage controlled oscillator that inputs a control voltage value and outputs an oscillation signal having a frequency according to the control voltage value;
An oscillation signal output from the voltage controlled oscillator or a signal obtained by dividing the oscillation signal is input as a feedback oscillation signal, and a reference oscillation signal is also input, and a phase difference between the feedback oscillation signal and the reference oscillation signal And a phase comparison unit that outputs a phase difference signal representing this phase difference,
A charge pump that inputs a phase difference signal output from the phase comparison unit and outputs a charge / discharge current corresponding to the phase difference represented by the phase difference signal;
Including a capacitive element that is charged and discharged by inputting a charge / discharge current output from the charge pump, and a loop filter that outputs the control voltage value that is increased or decreased according to the charge / discharge amount to the voltage controlled oscillator;
A detection unit for detecting a change rate of the control voltage value when a charge / discharge current output from the charge pump is input to the loop filter;
Based on a detection result by the detection unit, a control unit for adjusting a charge / discharge current output from the charge pump, a characteristic of the loop filter or a characteristic of the voltage controlled oscillator;
A PLL frequency synthesizer comprising: The detection unit detects a change speed of the control voltage value using the reference oscillation signal;
The PLL frequency synthesizer according to claim 1. A setting unit for setting the control voltage value to a predetermined value;
The detector detects a change rate of the control voltage value from the predetermined value;
The PLL frequency synthesizer according to claim 1 or 2. The setting unit includes an amplifier having a voltage follower configuration.
The PLL frequency synthesizer according to claim 3. The charge pump includes a plurality of current sources provided in parallel;
The control unit adjusts the charge / discharge current output from the charge pump by changing the number of current sources used among the plurality of current sources of the charge pump,
The PLL frequency synthesizer according to claim 1. The loop filter includes a resistor that inputs a charge / discharge current output from the charge pump to a first end, and a capacitive element connected to a second end of the resistor,
The detection unit monitors a potential of the first end or the second end of the resistor to detect a change speed of the control voltage value;
The PLL frequency synthesizer according to claim 1. The loop filter includes a resistor that inputs a charge / discharge current output from the charge pump to a first end, and a capacitive element connected to a second end of the resistor,
The setting unit sets a potential of the first end or the second end of the resistor to a predetermined value;
The detection unit monitors a potential of the first end or the second end of the resistor to detect a change speed of the control voltage value;
The PLL frequency synthesizer according to claim 3 or 4. The loop filter connects the first capacitive element, the second capacitive element having a capacitance value larger than the capacitance value of the first capacitive element, and the first capacitive element and the second capacitive element in parallel with each other. And a switch for
In a state where the second capacitive element is disconnected by the switch, the detection unit detects a change speed of the control voltage value, and the control unit performs adjustment,
After the adjustment by the control unit, the second capacitor element is connected in parallel to the first capacitor element by the switch.
The PLL frequency synthesizer according to claim 1. The charge pump comprises a first charge pump and a second charge pump,
The loop filter includes a capacitive element connected to the output terminal of the first charge pump, an amplifier that outputs a voltage value corresponding to the voltage value of the capacitive element, and a first terminal connected to the output terminal of the amplifier. And a resistor having a second end connected to the output end of the second charge pump, and outputting the control voltage value from the second end to the voltage controlled oscillator,
The controller adjusts a charge / discharge current output from the first charge pump;
The PLL frequency synthesizer according to claim 1. The voltage-controlled oscillator includes a capacitive element having a capacitance value that changes according to the control voltage value, and is an LC-VCO type that outputs an oscillation signal having a frequency according to the capacitance value of the capacitive element,
The control unit adjusts the characteristics of the voltage controlled oscillator by changing the dependency of the capacitance value of the capacitive element on the control voltage value;
The PLL frequency synthesizer according to claim 1. The voltage-controlled oscillator has a configuration in which a plurality of inverter circuits are connected in a ring shape, and is a Ring-VCO type that outputs an oscillation signal having a frequency corresponding to a current supplied to the inverter circuits.
The controller adjusts the characteristics of the voltage controlled oscillator by changing the dependency of the current supply amount to the inverter circuit on the control voltage value;
The PLL frequency synthesizer according to claim 1.

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