KR101390393B1 - Method and apparatus for calibrating current characteristic of charge pump and frequency synthesizer using the same - Google Patents

Abstract

A frequency generating apparatus including a charge pump and a loop filter, which is an open loop charge pump bias adjusting device for compensating a charge pump, according to embodiments of the present invention includes a pull-up bias voltage generating unit which generates a pull-up bias voltage and provides the pull-up bias voltage for a charge pump; an integrator which obtains an integral voltage by integrating the output voltage of a loop filter generated by the current of a pull-up charge pump flowing in the loop filter during a pull-up section where the charge pump generates the pull-up charge pump current by using the pull-up bias voltage; n number of comparators which output the result of a comparison between a sampled integral voltage and n number of reference voltages as a comparison signal of n bits when the pull-up section ends; a register of n bits which stores the comparison signal of n bits and outputs the comparison signal as a charge pump compensation signal of n bits; and a pull-down bias voltage generating unit which generates a pull-down bias voltage determined by the charge pump compensation signal and provides the pull-down bias voltage for the charge pump. [Reference numerals] (14) Frequency divider; (50) Charge pump bias adjusting unit; (AA) Bandwidth adjustment control unit; (BB) Test voltage generating unit; (CC) Automatic device compensating unit

Description

Charge pump bias adjusting device and frequency generating device using the same to adjust the current characteristics of the charge pump {METHOD AND APPARATUS FOR CALIBRATING CURRENT CHARACTERISTIC OF CHARGE PUMP AND FREQUENCY SYNTHESIZER USING THE SAME}

The present invention relates to a frequency generator, and more particularly, to a frequency generator of a voltage controlled oscillation method.

Most digital electronic circuits that use high frequency bands or have high speed digital signal transmission or data processing capabilities utilize high band or high precision frequency signals provided through high precision frequency generators. In particular, the importance of the frequency generating device as a factor that determines the performance of high-speed wireless communication, such as the recently spotlighted OFDM.

The frequency generator is itself a type of digital-analog integrated circuit and is manufactured through a semiconductor process such as, for example, a CMOS process, so it is inherently vulnerable to PVT conditions (process variables, operating voltage, temperature) like other semiconductor devices. Can be. Therefore, in the subsequent process, the value of the internal elements should be compensated to investigate the output state of the fabricated frequency generator and output the target frequency.

For example, in the LC oscillation or ring method, the size of the resonant element C can be compensated by permanently connecting or cutting the switches in the capacitance bank.

Furthermore, to reduce the effects of jitter or skew, the frequency generated by the frequency generator must have a constant bandwidth in accordance with the gain of the voltage controlled oscillator determined by the compensated device values.

However, in order to ship, all manufactured frequency generators must be fully investigated and the compensation value must be specified according to the manufacturing cost, and there is a problem that it is difficult to readjust internal device values after shipment.

Disclosure of Invention Problems to be solved by the present invention are to provide a charge pump bias adjustment method and apparatus capable of adjusting current characteristics of a charge pump for bandwidth adjustment in a later process, and a frequency generator using the same.

An open loop charge pump bias adjustment device for calibrating the charge pump for bandwidth adjustment in a frequency generation device including a charge pump and a loop filter, according to an aspect of the present invention,

A pull-up bias voltage generator configured to generate a pull-up bias voltage and provide it to the charge pump;

An integrator configured to integrate an output voltage of the loop filter generated by flowing the pull-up charge pump current through the loop filter during a pull-up period during which the charge pump generates a pull-up charge pump current by the pull-up bias voltage;

N comparators outputting a result of comparing the sampled integral voltage to n reference voltages as an n-bit comparison signal at the end of the pull-up period;

An n-bit register for storing the n-bit comparison signal and outputting it as an n-bit charge pump correction signal; And

A pull-down bias voltage generator configured to generate a pull-down bias voltage determined according to the charge pump correction signal and provide the pull-down bias voltage to the charge pump;

The charge pump generates the pull-up charge pump current according to the pull-up bias voltage during the pull-up period, and generates a pull-down charge pump current according to the pull-down bias voltage in a pull-down period complementary to the pull-up period to supply the loop filter. It can work.

According to one embodiment, the pull-down bias voltage generator,

Based on the charge pump correction signal, the variable current may be generated by activating at least some of the n unit current sources connected in parallel, and generating the pull-down bias voltage by current-voltage converting the generated variable current. .

According to one embodiment, the pull-down bias voltage generator,

The parallel n unit current sources are connected in parallel to one unit current source that always operates,

Each of the n unit current sources connected in parallel is activated or deactivated according to the charge pump correction signal to generate a variable current,

And generate the pull-down bias voltage by current-voltage converting the generated variable current.

According to an embodiment, the magnitude ratio of each of the n unit current sources connected in parallel may be a square number of two.

According to one embodiment, the pull-down bias voltage generator

Prior to the pull-up period, a pull-down bias voltage may be generated and provided to the charge pump to a magnitude before correction, and the pull-down charge pump current may flow through the loop filter to operate to lower the output voltage of the loop filter.

According to one embodiment, the open loop charge pump bias adjustment device,

While adjusting the charge pump the charge pump and loop filter may operate in disconnected state from the entire loop of the frequency generator.

Frequency generating apparatus according to another aspect of the present invention,

A phase frequency detector for receiving a reference frequency and a frequency dividing frequency respectively and generating an up signal or a down signal according to a result of comparison between a reference frequency and a frequency and a phase of the frequency division;

A charge pump configured to adjust the magnitude of the control voltage across the control voltage capacitor by supplying (pulling up) the charge voltage capacitor or providing a discharge path (pull down) according to the up signal or the down signal;

A loop filter including the capacitor for the control voltage and low frequency filtering the control voltage;

A ring type voltage controlled oscillator having a plurality of delay cells connected in a ring form to output an oscillation output according to the control voltage;

A frequency divider for outputting a frequency divided by the oscillation output at a predetermined frequency division ratio to the phase frequency detector,

With the charge pump disconnected from the phase frequency detector and the loop filter disconnected from the ring type voltage controlled oscillator, the charge pump is set to operate in a bias state prior to correction to the pullup charge pump current flowing from the charge pump. By increasing the output voltage of the loop filter by integrating the output voltage of the loop filter may include a bias voltage adjustment control unit for generating a pull-down bias voltage corresponding to the magnitude of the sampled integration voltage.

Selecting the magnitude of the bias current to flow through the delay cell, selecting the magnitude of the variable load capacitance to form at least a portion of the equivalent load capacitance present in the delay cell, and charging the equivalent load capacitance of the delay cell together with the bias current And further comprising an automatic element adjustment circuit operable to select a magnitude of the control voltage versus the additional drive current gain for generating an additional drive current that can be made according to the control voltage.

In accordance with another aspect of the present invention, a method for adjusting an open loop charge pump bias for calibrating the charge pump in a frequency generating device including a charge pump and a loop filter,

Disconnecting the charge pump and the loop filter in the entire loop of the frequency generator;

During the pull-up period, setting the charge pump to operate in a bias state before correction to increase the output voltage of the loop filter by a pull-up charge pump current flowing from the charge pump;

Integrating an output voltage of the loop filter during the pull-up period and sampling at the end of the pull-up period to obtain an integrated voltage;

Generating a pull-down bias voltage corresponding to the magnitude of the integrated voltage;

Reconnecting the charge pump and the loop filter to the entire loop of the frequency generator; And

Driving a pulldown charge pump current in the charge pump by the generated pulldown bias voltage.

According to one embodiment,

The method may further include setting the charge pump to operate in a pulldown period prior to the pullup period to lower the output voltage of the loop filter by a pulldown charge pump current before correction flowing from the charge pump.

According to one embodiment, the step of generating a pull-down bias voltage corresponding to the magnitude of the integral voltage,

Comparing the integrated voltage to n reference voltages to generate an n-bit thermometer code comparison signal;

Generating an n bit charge pump correction signal based on the n bit thermometer code comparison signal;

The method may include generating a pull-down bias voltage by current-voltage converting a variable current that varies according to the n-bit charge pump correction signal.

According to the charge pump bias adjustment method, apparatus and frequency generator of the present invention, the current characteristics of the charge pump for generating a control voltage for controlling the operating frequency of the ring-type voltage controlled oscillator are adjusted by adjusting the bias of the charge pump. Automatic adjustments can be made during the process so that bandwidth can be compensated.

According to the charge pump bias adjustment method, apparatus and frequency generator of the present invention, the adjustment operation through oscillation of the entire closed loop is not necessary to adjust the bandwidth, and the open loop of each of the charge pump or the voltage controlled oscillator is used. (open loop) adjustment is possible.

1 is a schematic block diagram of a frequency generating device according to an embodiment of the present invention.
2 is a more detailed block diagram of a voltage controlled oscillator used in a frequency generating device according to an embodiment of the present invention.
3 is a conceptual diagram illustrating a three-step procedure performed to find a target frequency in the frequency generating device according to an embodiment of the present invention.
FIG. 4 is a circuit diagram specifically illustrating one delay cell constituting a voltage controlled oscillator used in a frequency generating device according to an embodiment of the present invention.
FIG. 5 is a block diagram illustrating a manner in which voltage controlled oscillators used in a frequency generating device according to an embodiment of the present invention are implemented with four delay cells.
6 and 7 are timing diagrams illustrating the operation of the voltage controlled oscillator used in the frequency generating device according to an embodiment of the present invention and simulation results showing a process of finding a target frequency.
8 is a more detailed block diagram of a charge pump bias adjustment device, a charge pump, and a loop filter unit used in the frequency generator according to an embodiment of the present invention.
9 is a timing diagram illustrating the operation of the charge pump bias adjustment device used in the frequency generating device according to an embodiment of the present invention.
10 is a flow chart illustrating a procedure for adjusting the bias of the charge pump in the frequency generating device according to an embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a schematic block diagram of a frequency generating device according to an embodiment of the present invention.

Referring to FIG. 1, the frequency generator 10 is a phase-locked loop (PLL) type frequency synthesizer as an example, and includes a phase frequency detector (PFD) 11 and a charge pump. (12), loop filter (13), frequency divider (14), ring type voltage controlled oscillator (VCO) 20, automatic oscillator element compensator 30, test control voltage The generator 40 may include a charge pump bias adjuster 50 and a bandwidth correction controller 60.

Briefly describing the operation of the frequency generator 10, the reference frequency is first provided from a temperature compensated crystal oscillator TCXO which is insensitive to temperature or voltage and can output a precise reference frequency f _REF in a predetermined range. Accurate reference frequency f _REF can be obtained at several tens of MHz level.

The phase frequency detector 11 receives the reference frequency f _REF and the 1 / N frequency division frequency f _DIV output from the frequency divider 14, and outputs a comparison result of the frequency and phase of the reference frequency f _REF and the frequency division frequency f _DIV And outputs the up signal UP or the down signal DOWN to the charge pump 12.

If the frequency or phase of the frequency divider frequency f _DIV is smaller or slower than the frequency or phase of the reference frequency f _REF , the phase frequency detector 11 outputs the up signal UP. On the other hand, if the frequency or phase of the frequency dividing frequency f _DIV is larger or faster than the frequency or phase of the reference frequency f _REF , the phase frequency detector 11 outputs the down signal DOWN.

The charge pump 12 supplies (pulls up) a charge to a capacitor for a control voltage in the loop filter 13 according to an up signal UP or a down signal DOWN transmitted from the phase frequency detector 11. The charge voltage or the discharge path is provided (pulled down) to discharge to control the magnitude of the control voltage V _CTRL formed in the capacitor for the control voltage. Collectively referred to as the charge pump current I _CP through the pull-up charge pump current flowing from the charge pump 12 to the loop filter 13 at the time of charge or the pull-down charge pump current flowing from the loop filter 13 to the charge pump 12 at the time of discharge. do.

The loop filter 13 provides low frequency filtering (LPF) for a control voltage V _CTRL having ripple components due to switching of the charge pump 12 and supplies the filtered control voltage V _CTRL to a ring type voltage controlled oscillator 20).

The ring-type voltage-controlled oscillator 20 is one of voltage-controlled oscillators (VCOs), and is a circuit for obtaining stable oscillation signals by connecting delay cells, for example, implemented in a CMOS inverter, in a ring form. The bias current flowing through the CMOS inverter constituting the delay cell is controlled by the control voltage V _CTRL to adjust the driving capability of the CMOS inverter and further adjust the delay time of each delay cell and finally adjust the frequency of the oscillation output f _VCO have.

This ring-type voltage-controlled oscillator 20 can output the oscillation frequency f _VCO of the desired band through a certain settling time as the control voltage V _CTRL is applied. The oscillation output f _VCO is supplied to the circuit requiring this frequency and is also provided to the frequency divider 14.

The delay cell constituting the ring-type voltage-controlled oscillator 20 can adjust the delay rate according to how fast the equivalent load capacitance can be charged, and ultimately, this delay rate is controlled by the oscillation output of the ring-type voltage-controlled oscillator 20 f Determines the frequency of the _VCO .

The frequency divider 14 divides the frequency of the oscillation output f _VCO , which may range from several hundreds Mz to several GHz, by a predetermined frequency division ratio N to generate a divided frequency f _DIV and provides it to the phase frequency detector 11. The frequency division ratio N may be an integer or may have a fractional value if necessary.

As this operation is repeated, the frequency generator 10 can generate a stable oscillation output f _VCO , but it is necessary to presuppose that the elements contributing to oscillation, especially in a voltage controlled oscillator, have certain characteristics within the designed range. .

For example, the frequency generating device 10 such as a phase locked loop (PLL) may have a bandwidth different from that designed by, for example, influenced by a process, a supply voltage or a temperature when used in a transceiver for a wireless communication. If the bandwidth is different, the lock time of the phase-locked loop is changed, and a phenomenon that is not good for spurious or phase noise may occur. In order to solve this problem, it is necessary to adjust the characteristics of the elements of the frequency generating device to have a bandwidth as designed.

In particular, in a frequency generator such as the frequency generator 10 of FIG. 1, the bandwidth may be expressed as Equation 1 below. Therefore, it is possible to set the frequency generating device to have a desired bandwidth by measuring and appropriately adjusting factors influencing the bandwidth.

Where K _VCO is the gain of the voltage controlled oscillator (VCO), I _CP is the charge pump current, N is the division ratio, and R, C _Z and C _P are the device values in the loop filter, respectively.

According to Equation 1, the bandwidth _c may be adjusted to have a desired value by appropriately compensating elements in K _VCO , I _CP , division ratio N, and a loop filter. Among these factors, the division ratio, which is the ratio of the reference oscillation frequency and the output frequency, cannot be changed since the reference frequency provided from the temperature compensated crystal oscillator TCXO is fixed and the output frequency is ultimately fixed. Also, because the elements R and C in the loop filter must be relatively large to provide the correct control voltage V _CTRL , the configuration varying the values of these elements can have a significant effect on the layout as well as the overall area of the circuit. The inventors of the present application thus determine that it is most desirable to eventually adjust K _VCO and I _CP to the desired bandwidth.

As described above, in the related art, a procedure for compensating and adjusting the size or value of elements from the outside through total irradiation as a post-process when a frequency generator is shipped is required.

However, in the frequency generator 10 of the present invention, the automatic oscillator element compensator 30 automatically adjusts and sets the device characteristics related to the gain K _VCO in the ring type voltage controlled oscillator 20, and the charge pump bias adjuster By automatically adjusting and setting the charge pump current I _CP characteristics of the charge pump 12, it is possible to eliminate the need for a post-process of external testing and setting after manufacture, and furthermore, to reset the device characteristics at any time. can do.

During correction, the bandwidth correction controller 60 disconnects between the phase frequency detector 11 and the charge pump 12 in the entire loop and operates the charge pump bias adjuster 50, or the loop filter 13 and the voltage. The control oscillator 20 may be disconnected and the automatic oscillator element compensator 30 may be operated.

According to an exemplary embodiment, the bandwidth correction controller 60 may operate the automatic oscillator element compensator 30 and the charge pump bias adjuster 50 in order or in reverse order, or may operate simultaneously.

Specifically, the automatic oscillator element compensator 30 includes (1) the magnitude of the bias current flowing to basically charge the equivalent load capacitance of the delay cell regardless of the application of the control voltage V _CTRL , and (2) the delay. In addition to the magnitude of the cell's equivalent load capacitance and (3) the bias current, the ratio of generating additional drive current to charge the delay cell's equivalent load capacitance, according to the magnitude of the control voltage V _CTRL , that is, the control voltage versus additional drive current gain, respectively. By adjusting, the internal element characteristics can be set such that the ring type voltage controlled oscillator 20 finally has an oscillation frequency characteristic curve with respect to the desired control voltage, regardless of the variation of the manufacturing process.

In addition, the charge pump bias adjustment unit 50 determines the discharge rate by the pull-down current based on the charge rate by the pull-up current, thereby determining the difference between the charge and discharge driving capabilities of the charge pump 12 that causes noise and performance degradation. The current characteristic can be set to eliminate it.

Specifically, the charge pump bias adjustment unit 50 is a charge for the charge pump 12 to charge by supplying the charge to the capacitor for the control voltage in the loop filter 13 in the up / down signal or to provide a discharge path to discharge By adjusting the driving capability of the pump current I _CP , the speed of varying the magnitude of the control voltage V _CTRL across the control voltage capacitor can be adjusted as intended.

According to an embodiment, the automatic oscillator element compensator 30 and the charge pump bias adjuster 50 may be applied when power is applied to the frequency generator 10 or the operating voltage is changed, or according to a predetermined schedule or an external instruction. The characteristics of the elements constituting the delay cells in the ring type voltage controlled oscillator 20 or the characteristics of the elements constituting the current source of the charge pump 12 may be compensated or adjusted.

The operation of the ring type voltage controlled oscillator 20 and the automatic oscillator element compensator 30 and the operation of the charge pump bias adjuster 50 will be described in more detail below.

2 is a more detailed block diagram of a voltage controlled oscillator used in a frequency generating device according to an embodiment of the present invention.

2, ring type voltage controlled oscillator 20 includes a bias current source providing a plurality of selectable bias current magnitudes, a variable load capacitor providing a plurality of selectable variable load capacitances and a plurality of selectable control voltages. It is implemented with a plurality of delay cells having a variable current source providing drive current gains and an additional drive current that can charge the delay cell's equivalent load capacitance with the bias current.

In the adjustment of the voltage controlled oscillator 20, if the bandwidth adjustment control 60 first disconnects the connection between the loop filter 13 and the voltage controlled oscillator 20, the automatic oscillator element compensator 30 is connected to an open loop. The ring type voltage controlled oscillator 20 can be automatically compensated.

That is, the test control voltage generator 40 is not the control voltage V _CTRL which the automatic oscillator element compensator 30 adjusts through the closed loop feedback of the oscillation output f _VCO to compensate for the ring type voltage controlled oscillator 20. ) Means using a predetermined control voltage V _CTRL which is fixedly supplied.

The automatic oscillator element compensator 30 divides the oscillation output f _VCO of the compensation controller 31, the ring-type voltage controlled oscillator 20 as it is or appropriately divided, and counts the frequency counter 32, and the oscillation frequency for a predetermined time. The digital comparator 33 outputs an up / down signal according to the result of comparing the count value with the target frequency count value, and the ring type voltage according to the up signal or the down signal output from the digital comparator 33 as a first step. A bias adjuster 34 for selecting a bias current magnitude of the delay cell constituting the control oscillator 20, and a ring type voltage controlled oscillator 20 according to an up signal or a down signal output from the digital comparator 33 as a second step. The load adjuster 35 selects the variable load capacitance of the delay cell constituting the delay cell and the ringer according to the up signal or the down signal output from the digital comparator 33 as a third step. It may comprise a gain adjustment unit 36 to select a control voltage for driving additional current gain of the delay cell of the voltage controlled oscillator 20.

The automatic oscillator element compensator 30 first selects the magnitude of the bias current flowing in the delay cell in the first step.

To this end, the automatic oscillator element compensator 30 based on the comparison result of the oscillation frequency count and the target frequency count counted during the predetermined time frame with respect to the oscillation output f _VCO , the oscillation frequency count is added to the target frequency count during the next time frame. To be closer, a plurality of relatively sparse, selectable approximate frequencies, by performing at least one bias current adjustment step of selecting the bias current magnitude of the delay cells in the ring type voltage controlled oscillator 20 to be applied during the next time frame. One approximate frequency characteristic curve can be selected from the characteristic curves.

At this time, the start and end of the time frame are controlled by the compensation control unit 31.

Next, in the second step, the automatic oscillator element compensator 30 adjusts the size of the variable load capacitance. Here, the variable load capacitance is intentionally provided on the output terminal side so as to occupy a dominant portion of the equivalent load capacitance of the entire delay cell. Such a variable load capacitor may be implemented as a capacitor bank or the like.

To this end, the automatic oscillator element compensator 30 has the selected bias current and based on a comparison result of the oscillation frequency count and the target frequency count counted for the oscillation output f _VCO for a predetermined time frame, the oscillation frequency count is increased during the next time frame. One approximation selected in the bias adjustment step, by performing at least one load adjustment step of selecting a variable load capacitance magnitude of delay cells in the ring type voltage controlled oscillator 20 to be applied during the next time frame, to be closer to the target frequency count. Adjacent to the frequency characteristic curve, from among the plurality of selectable fine frequency characteristic curves with relatively narrow intervals, one fine frequency characteristic curve can be selected.

Finally, the automatic oscillator element compensator 30, in the third step, the ratio of the additional driving current to charge the equivalent load capacitance along with the bias current is generated according to the magnitude of the control voltage V _CTRL , that is, the control voltage versus the additional driving. By adjusting the current gain, you ultimately adjust the control voltage versus oscillation frequency gain K _VCO .

Specifically, in this specification, the control voltage vs. oscillation frequency gain K _VCO of the ring-type voltage-controlled oscillator 20 is defined as the amount of change in the oscillation output f _VCO relative to the magnitude of the change in the control voltage V _CTRL .

To this end, the automatic oscillator element compensator 30 has a selected bias current and variable load capacitance magnitude and based on a comparison result of the oscillation frequency count and the target frequency count counted for a predetermined time frame for the oscillation output f _VCO , the next time frame. By performing at least one gain adjustment step of selecting the control voltage versus the additional drive current gain of the delay cells in the ring type voltage controlled oscillator 20 to be applied during the next time frame so that the oscillation frequency count is closer to the target frequency count. A bias characteristic step and a load regulation step may select a frequency characteristic curve having one of a plurality of selectable control voltage versus oscillation frequency gain values with respect to the selected fine frequency characteristic curve.

Thus, the automatic oscillator element compensator 30 adjusts the device characteristics inside the ring type voltage controlled oscillator 20 such that the ring type voltage controlled oscillator 20 generates an oscillation output of a desired frequency with a desired control voltage versus oscillation frequency characteristic. It can be adjusted automatically.

However, according to the exemplary embodiment, the automatic oscillator element compensator 30 may sequentially perform the first, second, and third steps, but may simultaneously perform any two steps or all three steps.

For these operations, specifically, the compensation control section 31 operates in accordance with the reference clock CK_REF which is insensitive to temperature or voltage change. According to an embodiment, a separate reference clock generation circuit is configured in the automatic oscillator element compensator 30 to receive the reference clock CK_REF or to maintain the reference frequency f _REF applied to the phase frequency detector 11 described above. The used or divided may be provided as the reference clock CK_REF.

The compensation control unit 31 generates the count activation signal EN_CNT and the count reset signal RST_CNT for the frequency counter 32 based on the reference clock and controls the bias adjusting unit 34, the load adjusting unit 35, 36 perform step-by-step adjustment operations. The compensation control unit 31 may separately supply the operation clocks DEN_CLK of the bias adjustment unit 34, the load adjustment unit 35, and the gain adjustment unit 36.

The frequency counter 32 is a 15-bit digital counter, for example, which is initialized in accordance with the count reset signal RST_CNT and outputs a pulse of the oscillation output f _VCO of the voltage-controlled oscillator 20 during the time when the count activation signal EN_CNT is active Count. According to the embodiment, the frequency counter 32 may divide the oscillation output f _VCO of the voltage-controlled oscillator 20 by two or more division ratios, and then count the pulses.

The frequency counter 32 counts the pulse count value of the oscillation output f _VCO at the time when the count activation signal EN_CNT is inactivated, for example, in the form of a 15-bit oscillation frequency count value (VCO_CNT <14: 0> (33).

The period of the count reset signal RST_CNT of the compensation control unit 31, the activation time of the count activation signal EN_CNT, the count range of the frequency counter 32, and the like are the frequency of the oscillation output f _VCO of the voltage controlled oscillator 20, And may vary depending on the ratio of the frequency CK_REF. For example, if the frequency of the oscillation output f _VCO is 1.6 GHz and the reference frequency CK_REF is 300 kHz, the compensation control unit 31 generates the count reset signal RST_CNT and the count activation signal EN_CNT at 30 kHz, The comparator 32 may count the frequency of the oscillation output f _VCO divided by the frequency division ratio of 1/2 to 26,666 times every 1 / 30,000 seconds to output the 15-bit binary word 110100000101010B as the oscillation frequency count value VCO_CNT.

The digital comparator 33 compares the frequency count value VCO_CNT with the target frequency count value CH_FREQ and outputs the up signal UP or the down signal DOWN according to the comparison result. The target frequency count value CH_FREQ, which is equivalent to the number of counts of the target frequency for a specific time, may be, for example, a 15-bit digital word having a length equal to the frequency count value VCO_CNT. For example, , You can have a 15 bit binary word 110000110101000B counted 25,000 times for 1 / 30,000 seconds.

Specifically, if the oscillation frequency count value VCO_CNT is smaller than the target frequency count value CH_FREQ, the digital comparator 33 outputs the down signal DOWN. If the oscillation frequency count value VCO_CNT is smaller than the target frequency count value CH_FREQ, UP) can be output. The digital comparator 33 can appropriately output either the up signal UP or the down signal DOWN when the oscillation frequency count value VCO_CNT is equal to the target frequency count value CH_FREQ.

In the above example, the digital comparator 33 outputs the down signal DOWN because the oscillation frequency count value VCO_CNT is larger than the target frequency count value CH_FREQ.

According to the embodiment, the up / down signal outputted by the digital comparator 33 is a signal indicating that the comparison result of the oscillation frequency count value VCO_CNT and the target frequency count value CH_FREQ is merely one of the two states of "relatively large" , But may have information indicating one of four or more states, such as "much larger", "larger", "smaller", "much smaller" depending on the magnitude of the difference .

Meanwhile, referring to FIGS. 3 and 4 to look at the operation of the compensation controller 31 in more detail, FIG. 3 illustrates three operations performed by the frequency generator in order to find a target frequency. 4 is a conceptual diagram illustrating a procedure of steps, and FIG. 4 is a circuit diagram specifically illustrating one delay cell constituting a voltage controlled oscillator used in a frequency generating device according to an embodiment of the present invention.

In this case, the delay cell of FIG. 4 may be one of the differential delay cells connected in a quadrature manner so that one ring-type voltage-controlled oscillator can output four oscillation signals whose phases differ from each other by 90 degrees. The quadrature coupling scheme of the four delay cells connected in a differential manner is illustrated in Fig.

Referring again to FIGS. 2, 3 and 4, the bias adjusting unit 34 adjusts the bias current source 211 of the delay cell 21 of the ring-type voltage-controlled oscillator 20 as a first step For example, the bias adjustment signal FCON <7: 0> of the 8-bit word is adjusted in accordance with the up signal or the down signal of the digital comparator 33 to be supplied to the delay cell 21 of the ring voltage control oscillator 20 And output by the compensation control unit 31. [

For example, the bias current source 211 of the delay cell 21 of the ring-type voltage-controlled oscillator 20 may be implemented with a plurality of transistor current sources connected in parallel. The driving capability or size of the bias current source 211 is determined as a whole by electrically activating or deactivating a plurality of parallel connected transistors connected to the power source voltage according to the bit combination of the bias adjusting signal FCON. The bias current, that is, the driving ability of the delay cell 21 is changed according to the size of the bias current source 211, and thus the frequency of the oscillation output f _VCO of the ring-type voltage controlled oscillator 20 is greatly changed.

In this case, according to the embodiment, the bias adjustment signal FCON may be, for example, a thermometer code in which the bit number is important, or the binary value magnitude may be a binary code. If the bias adjustment signal FCON is a thermometer code, the bias current source 211 of each of the delay cells 21 of the ring-type voltage-controlled oscillator 20 outputs a bias current proportional to the number of bits "1 " 21). In this case, each of the parallel-connected transistors constituting the bias current source 211 may have the same size.

On the other hand, if the bias adjustment signal FCON is a binary code, the bias current source 211 of each of the delay cells 21 of the ring-type voltage-controlled oscillator 20 generates, for example, a bias current proportional to the binary value of the bias adjustment signal FCON Can be supplied to the delay cell (21). In this case, each of the parallel-connected transistors constituting the bias current source 211 may have a size proportional to a multiple of 2 corresponding to the binary digit number.

Since the magnitude of the bias currents varies discontinuously according to the combination of the bias adjustment signal FCON, the frequency characteristics exhibited by the bias currents are approximated as a few parallel straight lines spaced discontinuously and relatively widely as shown in the uppermost graph of FIG. . &Lt; / RTI &gt; 3, the horizontal axis represents the magnitude of the control voltage, and the vertical axis represents the frequency of the oscillation output.

The bias adjusting unit 34 adjusts the bias adjustment signal FCON until the frequency of the adjusted oscillation output f _VCO is determined to be closest to the target frequency until the specified number of iterations is reached, The bias adjustment signal FCON can be adjusted at least once until all the values of all the bits from the MSB to the LSB of the FCON are specified and when the adjustment is completed, the bias adjustment signal FCON value can be fixed.

An algorithm for finding an optimal bias adjustment signal FCON value can be implemented using a well-known algorithm such as a binary tree search algorithm.

Through the above-described operation, the ring-type voltage-controlled oscillator 20 generates an oscillation output f _{VCO (} k) along one approximate frequency characteristic curve selected in accordance with the bias adjustment signal FCON from among a plurality of relatively- . &Lt; / RTI &gt;

According to the embodiment, the load adjusting unit 35 and the gain adjusting unit 36 adjust the load adjusting signal CAPCON and gain (gain) until the bias adjusting signal FCON is fixed while the bias adjusting unit 34 performs the bias adjustment in the first step It is possible to continuously output the adjustment signal IC0N in a state in which it is set to have the default values.

The load adjusting unit 35 and the gain adjusting unit 36 may also perform the second step or the third step described below, respectively, while the bias adjusting unit 34 performs the bias adjustment of the first step, Each can be performed simultaneously.

Then, in order to carry out the second load adjustment step, the load adjustment unit 35 adjusts the size of the variable load capacitor 212 of the delay cell 21 by, for example, adjusting the 3-bit word load adjustment signal CAPCON < 2 : 0> to the delay cell 21 of the ring-type voltage-controlled oscillator 20 in accordance with the up signal or the down signal of the digital comparator 33. [

According to an embodiment, the load adjustment signal CAPCON may be a thermometer code or a binary code.

If the load adjustment signal CAPCON is a thermometer code, the variable load capacitor 212 of each of the delay cells 21 in the ring-type voltage-controlled oscillator 20 can have a load capacitance proportional to the number of bits "1" have. On the other hand, if the load adjustment signal CAPCON is a binary code, the variable load capacitor 212 of each of the delay cells 21 in the ring-type voltage-controlled oscillator 20 is, for example, a load capacitance proportional to the binary value of the load adjustment signal CAPCON Lt; / RTI &gt;

To this end, the variable load capacitors 212 in the delay cell 21 may be implemented with a series, parallel or series-parallel combination of capacitor banks electrically connected or disconnected respectively by the bit values of the load adjustment signal CAPCON.

Since the magnitude of the load capacitance varies discontinuously according to the combination of the load adjustment signal CAPCON, the control voltage-frequency characteristics that appear therefrom are different from each other in a few graphs Can be expressed as parallel straight lines.

The load adjustment unit 34 adjusts the load adjustment signal CAPCON until it is determined that the frequency of the oscillation output f _VCO adjusted in the range that can be adjusted by the load adjustment signal CAPCON is closest to the target frequency, The load adjustment signal CAPCON can be adjusted at least once until all the values of all the bits from the MSB to the LSB of the CAPCON are specified. When the adjustment is completed, the load adjustment signal CAPCON value is fixed and the second step is terminated.

An algorithm for finding an optimal load adjustment signal CAPCON value can be implemented using a well-known algorithm such as a binary tree search algorithm.

As a result, the oscillation output f _VCO is selected from among a plurality of selectable fine frequency characteristic curves adjacent to one approximate frequency characteristic curve selected in accordance with the bias adjustment signal FCON, Can be generated along a fine frequency characteristic curve.

Next, in the third step, in order to perform the gain adjustment step, the gain adjustment unit 36 controls the variable gain current source 213 of the delay cell 21 of the ring-type voltage-controlled oscillator 20, For example, a 3-bit word gain adjustment signal ICON < 2: 0 > that can adjust the ratio of generating a further drive current to charge the capacitance based on the control voltage V _CTRL , And may be controlled by the compensation control section 31 so as to adjust it according to the up signal or the down signal of the comparison section 33 and output it to the delay cell 21. [

In other words, the variable gain current source 213 changes the generation ratio of the additional drive current to be charged together with the bias current, i.e., the control voltage to the additional drive current gain, corresponding to the bit combination of the gain adjustment signal ICON , The desired slope control voltage vs. oscillation frequency gain characteristics can be selected.

As previously defined, the control voltage vs. frequency gain K _VCO is the frequency variation of the oscillation output f _VCO versus the variation of the control voltage V _CTRL .

For example, the variable gain current source 213 of the delay cell 21 of the ring-type voltage-controlled oscillator 20 includes voltage control current amplifying circuits 214 provided in parallel with each other and provided with the number of bits of the gain adjusting signal ICON, May include switches 218 that are turned on and off by the respective bits of the adjustment signal ICON to connect or disconnect between each of the current amplification circuits 214 and the output terminal (OUT or OUTB) of the delay cell 21 have.

Each of the voltage control current amplifying circuits 214 has a source degeneration capacitor 215 and a gate connected to the control voltage V _CTRL and a drain connected to the output terminal OUT, And a driving transistor 216 connected to ground (GND) through a source damping capacitor 215.

However, in the case of such a configuration, the control voltage if the size of the V _CTRL is lower than the threshold voltage (Vt) of NMOS drive transistor 216, NMOS driver transistor 216 does not linear operation control voltage to change the V _CTRL The additional drive current to be supplied by the variable gain current source 213 to the equivalent load capacitance of the delay cell 21 may not substantially fluctuate.

Accordingly, in another embodiment, by generating a shift control voltage V _{CTRL_S} that is a level-shifted control voltage V _CTRL by a threshold voltage Vt using, for example, a source follower structure, the control voltage V _CTRL the size of the, even if lower than the threshold voltage (Vt) of NMOS drive transistor 216, has a Vt as high shift control voltage V _{CTRL_S} than the control voltage V _CTRL drives the variable-gain current source 213, the control voltage V _CTRL The variable gain current source 213 can be configured so that the additional driving current supplied to the equivalent load capacitance of the delay cell 21 substantially varies depending on the variation.

In this embodiment, the voltage-controlled current amplifying circuit 214 includes a source decoupling capacitor 215, a gate receiving the control voltage V _CTRL , a drain connected to the output terminal OUT, and a source coupled to the source decoupling capacitor 215 And a drain connected to the output terminal OUT and a source connected to the ground GND through the source _decoupling capacitor 215. The first driving transistor 216 is connected to the ground GND via the source- And a second driving transistor 217 connected to the second driving transistor 217.

In these embodiments, the additional drive current generated in each variable gain current source 213 is selectively coupled to the equivalent load capacitance by the bits of the gain adjustment signal ICON. Thus, for example, even in the same sized control voltage V _CTRL , the slope K _VCO of the gain becomes larger when more additional driving current is connected to the equivalent load capacitance according to the gain adjustment signal ICON of the larger binary value, The smaller the slope K _VCO of the gain is, the less the additional drive current is connected to the equivalent load capacitance,

According to an embodiment, the gain adjustment signal ICON may be a thermometer code or a binary code. If the gain adjustment signal ICON is a thermometer code, the variable gain current source 213 may supply an additional drive current of a magnitude proportional to, for example, the number of bits "1 ". On the other hand, if the gain adjustment signal ICON is a binary code, then the variable gain current source 213 of each of the delay cells 21 in the voltage controlled oscillator 20 is set to an additional drive current, for example, proportional to the binary value of the gain adjustment signal ICON Can supply.

Further, since the magnitude of the additional driving current is discontinuously displayed according to the combination of the gain adjustment signal ICON, the frequency characteristics exhibited by the additional driving current can be expressed as several straight lines having different slopes as shown in the bottom graph of FIG. 3 . The higher the slope, the more sensitive the change in the control voltage V _CTRL .

The compensation control section 31 controls the gain adjustment signal ICON until it is determined that the adjusted control voltage vs. frequency gain characteristic is within a range that can be adjusted by the gain adjustment signal ICON, The gain adjustment signal ICON can be adjusted at least once until all the values of all bits from the MSB to the LSB of the ICON are specified. When the adjustment is completed, the gain adjustment signal ICON is fixed and the third step is terminated.

Thus, the ring-type voltage-controlled oscillator 20 in which the characteristics of the internal elements are determined by the fixed bias adjustment signal FCON, the load adjustment signal CAPCON, and the gain adjustment signal ICON at each step is obtained by following the characteristic curve closest to the desired frequency characteristic curve An oscillation output f _VCO can be generated.

According to the embodiment, the compensation control section 31 may control the bias adjustment section 34, the load adjustment section 35 and the gain adjustment section 36 to sequentially adjust the adjustment signals FCON, CAPCON and ICON , It may be controlled to adjust it simultaneously.

6 and 7 are timing diagrams illustrating the operation of the voltage controlled oscillator used in the frequency generating device according to an embodiment of the present invention and simulation results showing a process of finding a target frequency.

Referring to FIG. 6, the count activation signal EN_CNT and the count reset signal RST_CNT are not overlapped with each other at every time frame (T1 to T5) by the compensation controller 31 according to the input of the reference clock CK_REF .

Throughout each time frame T1 to T5, the divided pulse VCO_DIV which divides the frequency of the oscillation output f _VCO at 1 / K is counted and counted until the count enable signal EN_CNT is temporarily activated and deactivated. The comparison result of the oscillation frequency count value and the target frequency count value is derived. When the comparison between the oscillation frequency count value and the target frequency count value is completed, the count reset signal RST_CNT is activated and the oscillation frequency count value is initialized.

When the first time frame T1 starts for the first time, the bias adjustment signal FCON, the load adjustment signal CAPCON, and the gain adjustment signal ICON may all have default values.

When the bias adjustment signal FCON for the next time frame is generated and input to the ring-type voltage-controlled oscillator 21 in accordance with the comparison result between the oscillation frequency count value counted during the first time frame T1 and the target frequency count value, The oscillation output of the ring oscillator 21 is generated in the ring-type voltage-controlled oscillator 21, and the second time frame T2 starts.

Then, when a new bias adjustment signal FCON is generated and input to the ring-type voltage-controlled oscillator 21 according to the result of comparison between the newly counted oscillation frequency count value and the target frequency count value during the second time frame T2, An oscillation output of the ring-type voltage-controlled oscillator 21 will be generated.

During the second time frame T2, the load adjustment signal CAPCON and the gain adjustment signal ICON may have default values.

It may take several time frames until the bias adjustment signal FCON is settled. Depending on the embodiment, the bias adjustment signal FCON can be iteratively adjusted until a best approximate frequency characteristic is determined, until a predetermined number of iterations or until all the bits are adjusted in turn.

An algorithm for finding an optimal bias adjustment signal FCON value can be implemented using a well-known algorithm such as a binary tree search algorithm.

In the example of FIG. 6, if the bias adjustment signal FCON is settled in the third time frame T3, the value of the bias adjustment signal FCON can be fixed after the third time frame T3.

A new load adjustment signal CAPCON for the fourth time frame T4 is generated according to the comparison result of the oscillation frequency count value counted during the third time frame T3 and the target frequency count value to generate the ring type voltage control oscillator 21, The oscillation output of the changed frequency is generated in the ring-type voltage-controlled oscillator 21 during the fourth time frame T4.

Then, in accordance with the comparison result of the counted oscillation frequency count value and the target frequency count value during the fourth time frame T4, the load adjustment signal CAPCON is changed and settled, and the gain adjustment signal to be checked during the fifth time frame T5 ICON is changed and input to the ring-type voltage-controlled oscillator 21.

With the end of the fifth time frame T5, the fixed signal LOCK is activated so that the frequency adjustment step is finished and the internal element characteristic value for the frequency characteristic adjustment is determined according to the final value of each adjustment signal.

The frequency generator 10 can also finely tune the frequency of the desired oscillation output f _VCO through its own closed loop, so that internal device characteristic values need not be compensated with very high precision. Therefore, the operation of the automatic oscillator element compensator 30 may be sufficient to repeatedly adjust for a time frame of about 10 times.

Referring to FIG. 7, a simulation in which the automatic oscillator element compensator 30 adjusts internal device characteristic values of the ring type voltage controlled oscillator 20 is illustrated. The oscillating output, which exceeded 1.8 GHz in the first time frame, dropped to 1.45 GHz through 1.65 GHz following adjustment of the bias adjustment signal FCON, and then adjusted several times to 1.52 GHz, 1.42 GHz, 1.46 GHz, and 1.5 GHz. In other words, it is settled at the target frequency of 1.5 GHz.

Meanwhile, the bias adjustment signal FCON starts from 01111111B first, passes through values such as 00111111B, 00011111B, and finally is set as 00101100B.

The load adjustment signal CAPCON is then adjusted from 100B to 101B after the bias adjustment signal FCON is set and then settled.

On the other hand, the gain change of the oscillation output f _VCO according to the gain adjustment signal ICON is shown in accordance with the change in the magnitude of the control voltage V _CTRL . Since the gain change signal ICON is not visually represented on the time axis basis, Is omitted in Fig.

8 is a more detailed block diagram of a charge pump bias adjustment device, a charge pump, and a loop filter unit used in a frequency generator according to an embodiment of the present invention, and FIG. 9 is a frequency generator according to an embodiment of the present invention. It is a timing chart explaining the operation of the charge pump bias adjusting device used.

Referring to FIG. 8, the charge pump bias adjustment device 50 includes a charge pump adjustment control unit 51, an integrator 52, n comparators 53a, 53b, and 53c outputting various control signals and reference voltages. , 53n), an n-bit register 54, a pull-down bias voltage generator 55, and a pull-up bias voltage generator 56.

In detail, the charge pump adjustment controller 51 may generate the correction up / down signals UP _CAL , DN _CAL, and n reference voltages V _REF1 , V _REF2 ,..., And V _REFn .

The correction up / down signals UP _CAL and DN _CAL may be applied to the gate of the pull-up control transistor Q2 and the pull-down control transistor Q3 of the charge pump 12, respectively. The correction up / down signals UP _CAL , DN _CAL may be generated during the charge pump calibration procedure, first only the pulldown control transistor Q3 is activated during the pulldown period and then only the pullup control transistor Q2 during the pullup period.

In addition, the n reference voltages V _REF1 , V _REF2 , ..., V _REFn may be implemented by, for example, a resistor ladder, and the n comparators 53a, 53b, 53c ..., 53n Is provided for each.

The integrator 52 is a correction control voltage which is the output terminal voltage of the loop filter 13 after the loop filter 13 is disconnected from the ring type voltage controlled oscillator 20 by the bandwidth control signal BWC_EN of the bandwidth adjustment control unit 60. Receives and integrates V _{CTRL_CAL} to output the integral voltage V _INTG . In this case, the integrator 52 may be implemented, for example, with a large capacity capacitor.

The n comparators 53a, 53b, 53c ..., 53n compare the integral voltage V _INTG and one of the reference voltages V _REF1 , V _REF2 , ..., V _REFn , respectively.

The n bit register 54 stores the comparison signal CAL [n: 0], which is an n bit word composed of the comparison result of the n comparators 53a, 53b, 53c ..., 53n.

The point at which the n-bit register 54 stores the comparison signal CAL [n: 0] is the point at which the charge pump adjustment procedure is completed, and the n-bit register 54 stores the stored comparison signal CAL [n; 0] at a later frequency. It outputs to the pull-down bias voltage generation part 55 as charge pump correction signal CP_CAL [n: 0] throughout the operation | movement of the generator 10. FIG.

The pull-down bias voltage generator 55 may include a pull-down current voltage converter 552 that outputs the pull-down bias voltage V _{DN_CP} according to the magnitude of the variable current output from the n-bit variable current source 551.

The n-bit variable current source 551 of the pull-down bias voltage generator 55 has n unit current sources connected in parallel to one unit current source that is always in operation, and the charge pump correction signal CP_CAL [n generated when the charge pump correction is completed. According to: 0], the variable current can be generated by being activated or deactivated.

The magnitude ratio of each of the n unit current sources may be determined as a power of two. For example, the unit current source activated by the MSB of the charge pump correction signal CP_CAL [n: 0] may be 2 ⁿ times larger than the unit current source activated by the LSB.

At this time, while the correction of the charge pump 12 is in progress, the charge pump correction signal CP_CAL [n: 0] has a default value before the correction is completed. Only a unit current source transistor corresponding to a designated unit current source transistor, for example, an MSB, may be activated to provide a variable current to the pull-down current voltage converter 552.

The pull-down bias voltage generator 55 may apply the pull-down bias voltage V _{DN_CP} to the gate of the pull-down driving transistor Q4 of the charge pump 12.

If the pulldown control transistor Q3 of the charge pump 12 is activated during the pulldown period of the charge pump correction procedure, the pulldown drive transistor Q4 is _pulled by the pulldown charge pump current I _CP by the pulldown bias voltage V _{DN_CP} . Is discharged, and the correction control signal V _{CTRL_CAL} of the loop filter 13 falls.

On the other hand, the pull-up bias voltage generator 56 may include a pull-up current voltage converter 562 that outputs a pull-up bias voltage V _{UP_CP} corresponding to the magnitude of the fixed current output from one fixed current source 561.

The pull-up bias voltage generator 56 may apply the pull-up bias voltage V _{UP_CP} to the gate of the pull-up driving transistor Q1 of the charge pump 12.

If the pull-up control transistor Q2 of the charge pump 12 is activated during the pull-down period following the charge pump correction procedure, the pull-up driving transistor Q1 is _looped by the pull-up charge pump current I _CP by the pull-up bias voltage V _{UP_CP} . The filter 13 is charged, and the correction control signal V _{CTRL_CAL} of the loop filter 13 rises.

Next, the specific operation of the charge pump bias adjustment device 50 will be described below with reference to FIGS. 8 and 9.

The charge pump calibration procedure consists of a pulldown section T _DN , a pullup section T _UP, and a bias voltage determination section T _BIAS .

During the charge pump calibration procedure, the charge pump bias adjustment device 50 adjusts the current characteristics of the charge pump 12 with an open loop.

In other words, the charge pump 12 receives the correction up / down signals UP _CAL and DN _CAL provided by the charge pump bias adjusting device 50 instead of receiving the up / down signals from the phase frequency detector 11. And the loop filter 13 is also disconnected from the voltage controlled oscillator 20 and instead of outputting the control voltage V _CTRL to the voltage controlled oscillator 20, the correction control voltage V _{CTRL_CAL} is _supplied to the charge pump bias adjusting device 50. )

To this end, the bandwidth adjustment control 60 initiates the adjustment of the charge pump 12, and by activation of the bandwidth control signal BWC_EN, first the connection between the phase frequency detector 11 and the charge pump 12 and the loop filter ( 13) and the ring type voltage controlled oscillator 20 is disconnected.

The output terminal of the loop filter 13 is charged to the size of the control voltage V _CTRL supplied by the test control voltage generation unit 40 immediately before the charge pump correction procedure, and is controlled by the ring type voltage by the bandwidth control signal BWC_EN. It is connected to the integrator 52 instead of the oscillator 20.

Immediately after the bandwidth control signal BWC_EN is activated, during the pull-down period T _DN , the correction up / down signals UP _CAL and DN _CAL are output to have a logic value HIGH, respectively. The pull-up control transistor Q2 is deactivated and the pull-down control transistor Q3 is Is activated.

In this state, the charge pump bias adjustment device 50 discharges the loop filter 13 by _pulling down the pull-down driving transistor Q4 of the charge pump 12 with the pull-down bias voltage V _{DN_CP} in the state before being corrected.

The correction control voltage V _{CTRL_CAL} of the loop filter 13 is applied to the integrator 52. Since the correction control voltage V _{CTRL_CAL} gradually decreases _due to discharge, the integral voltage V _INTG output from the integrator 52 is also lowered and the pull-down period T _DN Falls to the lowest level before the end.

During the following pull-up period T _UP, the correction up / down signals UP _CAL and DN _CAL are output to have a logic value LOW, respectively. The pull-up control transistor Q2 is activated and the pull-down control transistor Q3 is deactivated.

In this state, the charge pump bias adjustment device 50 charges the loop filter 13 by _pulling up the pull-up driving transistor Q1 of the charge pump 12 by the pull-up bias voltage V _{UP_CP} .

The correction control voltage V _{CTRL_CAL} of the loop filter 13 is continuously applied to the integrator 52, and since the correction control voltage V _{CTRL_CAL} gradually increases _due to charging, the integral voltage V _INTG output from the integrator 52 gradually increases and the pull-up interval T _It rises to the highest level at the end of the _UP .

At this time, during the pull- _up period T _UP , the rising slope of the correction control voltage V _{CTRL_CAL} of the loop filter 13 or the rising slope of the integration voltage V _INTG output from the integrator 52 is applied to the gate and the pull-up bias voltage V _{UP_CP} is applied to the gate. It is determined by the pull-up charge pump current I _CP flowing in the drive transistor Q1.

On the other hand, the magnitude of the charge pump current I _CP at the time of pull-down is preferably determined corresponding to the magnitude of the charge pump current I _CP at the time of pull-up.

If the pull-down bias voltage V _{DN_CP} is determined based on the final magnitude of the integral voltage V _INTG output from the integrator 52, the pull-down charge pump current generated by the pull-down driving transistor Q4 based on the application of the pull-down bias voltage V _{DN_CP} . It can be said that I _CP is eventually determined corresponding to the magnitude of the charge pump current I _CP at the time of pull-up.

To this end a pull-up interval T _UP ends integral voltage V _INTG the point of time when the sampled, relatively short bias voltage determined period following the pull-up period T _UP during T _BIAS, the integral voltage V _INTG a plurality of comparators (53a, 53b, 53c ..., 53n) are compared to the reference voltages V _REF1 , V _REF2 , ..., V _REFn , _respectively , as a comparison signal CAL [n: 0] in the form of an n-bit thermometer code. The comparison signal CAL [n: 0] is stored in the n bit register 54.

The n bit register 54 then outputs the stored comparison signal CAL [n: 0] to the pull-down bias voltage generator 55 as the charge pump correction signal CP_CAL [n: 0].

The pull-down bias voltage generator 55 generates a pull-down bias voltage V _{DN_CP} that is determined based on the charge pump correction signal CP_CAL [n: 0], and _{uses the} generated V _{DN_CP} to pull-down driving transistor Q4 of the charge pump 12. Is applied to the gate.

Specifically, the pull-down bias voltage generator 55 generates a variable current by activating at least some of the n unit current sources connected in parallel based on the charge pump correction signal CP_CAL [n: 0], and converts the generated variable current into a current. Pull down bias voltage V _{DN_CP} can be generated by voltage conversion.

In this way, the charge pump current I _CP at the time of the charge pump current I _CP and the pull-down at the time of pull-up may be balanced.

Now that the correction of the charge pump current I _CP of the charge pump 12 is completed, the bandwidth correction controller 60 reconnects the entire loop of the frequency generator 10 with the deactivation of the bandwidth control signal BWC_EN. At this time, the pull-down bias voltage generator 55 and the pull-up bias voltage generator 56 are connected to the charge pump 12 regardless of the deactivation of the bandwidth control signal BWC_EN. In particular, the pull-down bias voltage generator 55 is corrected. Note that the pull-down bias voltage V _{DN_CP} is continuously applied.

10 is a flow chart illustrating a procedure for adjusting the bias of the charge pump in the frequency generating device according to an embodiment of the present invention.

Referring to FIG. 9 and FIG. 10 together, as the charge pump correction procedure is started, first, in step S101, the charge pump 12 and the loop filter 13 are disconnected in the entire loop of the frequency generator 10. .

In step S102, during the pull-down period, the correction control voltage V _{CTRL_CAL} which is the output voltage of the loop filter 13 by the pull-down charge pump current I _CP flowing from the charge pump 12 by setting the charge pump 12 to operate in a pull-down operation. To lower.

According to the embodiment, if the correction control voltage V _{CTRL_CAL which} is the output voltage of the loop filter 13 has already been sufficiently discharged at the start of the charge pump correction procedure, the charge pump 12 is _pulled down in step S102 to loop. The procedure for discharging the filter 13 can be omitted.

When the correction control voltage V _{CTRL_CAL, which} is the output voltage of the loop filter 13 during the charge pump correction procedure, is sufficiently lowered, the charge pump 12 is now set to pull up operation.

To this end, in step S103, during the pull-up period, the output of the loop filter 13 is set by the pull-up charge pump current I _CP flowing from the charge pump 12 by setting the charge pump 12 to operate in the bias state before correction. The correction control voltage V _{CTRL_CAL} which is a voltage is raised.

In step S104, the correction control voltage V _{CTRL_CAL} , which is the output voltage of the loop filter 13, is integrated during the pull-up period, and is sampled at the end of the pull-up period to obtain the integral voltage V _INTG .

In step S105, during the pull-down bias voltage determination period T _BIAS , a pull-down bias voltage V _{DN_CP} is generated corresponding to the magnitude of the integrated voltage V _INTG .

Specifically, the integral voltage V _INTG is compared to n reference voltages to generate n bits of thermometer code comparison signal CAL [n: 0], and n based on n bits of thermometer code comparison signal CAL [n: 0]. Generate a bit charge pump correction signal CP_CAL [n: 0].

Subsequently, a pull-down bias voltage V _{DN_CP} is generated by current-voltage conversion of a variable current that varies according to the n-bit charge pump correction signal CP_CAL [n: 0].

In step S106, the charge pump 12 and the loop filter 13 are reconnected to the entire loop of the frequency generator 10.

In step S107, the pull-down charge pump current I _CP of the charge pump 12 is driven by the generated pull-down bias voltage V _{DN_CP} .

As a result, the charge pump bias adjustment unit 50 may adjust the pull-down bias voltage such that the charge pump 12 applies the charge pump current I _CP to the loop filter 13 with the desired current characteristics.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Modification is possible. Accordingly, the spirit of the present invention should be understood only in accordance with the following claims, and all of the equivalent or equivalent variations will fall within the scope of the present invention.

10 Frequency Generator 11 Phase Frequency Detector (PFD)
12 Charge pump (CP) 13 Loop filter (LF)
14 Frequency Dividers 20 Ring Type Voltage Controlled Oscillator (VCO)
21 delay cell 211 bias current source
212 variable load capacitor 213 variable gain current source
30 Automatic Oscillator Element Compensation Unit 31 Compensation Control Unit
32 Frequency counter 33 Digital comparator
34 bias adjuster 35 load adjuster
36 Gain adjuster 40 Test voltage generator
50 Charge Pump Bias Adjuster 51 Charge Pump Adjuster
52 Integrator 53 Comparator
54 n-bit register
55 Pull-down Bias Voltage Generator 56 Pull-up Bias Voltage Generator
60 Bandwidth Compensation Control

Claims (11)

An open loop charge pump bias adjustment device for calibrating the charge pump for bandwidth adjustment in a frequency generating device including a charge pump and a loop filter,
A pull-up bias voltage generator configured to generate a pull-up bias voltage and provide it to the charge pump;
An integrator configured to integrate an output voltage of the loop filter generated by flowing the pull-up charge pump current through the loop filter during a pull-up period during which the charge pump generates a pull-up charge pump current by the pull-up bias voltage;
N comparators outputting a result of comparing the sampled integral voltage to n reference voltages as an n-bit comparison signal at the end of the pull-up period;
An n bit register for storing the n bit comparison signal and outputting the n bit comparison signal as an n bit charge pump correction signal; And
A pull-down bias voltage generator configured to generate a pull-down bias voltage determined according to the charge pump correction signal and provide the pull-down bias voltage to the charge pump;
The charge pump generates the pull-up charge pump current according to the pull-up bias voltage during the pull-up period, and generates a pull-down charge pump current according to the pull-down bias voltage in a pull-down period complementary to the pull-up period to supply the loop filter. An open loop charge pump bias adjustment device, characterized in that the operation. The method of claim 1, wherein the pull-down bias voltage generator,
And based on the charge pump correction signal, generate a variable current by activating at least some of the n unit current sources connected in parallel, and generating the pull-down bias voltage by current-voltage converting the generated variable current. Open loop charge pump bias adjustment device. The method of claim 2, wherein the pull-down bias voltage generator,
The parallel n unit current sources are connected in parallel to one unit current source that always operates,
Each of the n unit current sources connected in parallel is activated or deactivated according to the charge pump correction signal to generate a variable current,
And generate the pull-down bias voltage by current-voltage converting the generated variable current. The open loop charge pump bias adjustment apparatus of claim 2, wherein a ratio of the magnitudes of the n unit current sources connected in parallel is a power of two. The method of claim 1, wherein the pull-down bias voltage generator
A pull-down bias voltage is generated and provided to the charge pump prior to the pull-up period, and the pull-down charge pump current flows through the loop filter to operate so that the output voltage of the loop filter drops. Loop charge pump bias adjustment device. The method of claim 1, wherein the open loop charge pump bias adjustment device,
And wherein the charge pump and loop filter operate while disconnected from the entire loop of the frequency generating device while adjusting the charge pump. A phase frequency detector for receiving a reference frequency and a frequency dividing frequency respectively and generating an up signal or a down signal according to a result of comparison between a reference frequency and a frequency and a phase of the frequency division;
A charge pump configured to adjust the magnitude of the control voltage across the control voltage capacitor by supplying (pulling up) the charge voltage capacitor or providing a discharge path (pull down) according to the up signal or the down signal;
A loop filter including the capacitor for the control voltage and low frequency filtering the control voltage;
A ring type voltage controlled oscillator having a plurality of delay cells connected in a ring form to output an oscillation output according to the control voltage;
A frequency divider for outputting a frequency divided by the oscillation output at a predetermined frequency division ratio to the phase frequency detector,
With the charge pump disconnected from the phase frequency detector and the loop filter disconnected from the ring type voltage controlled oscillator, the charge pump is set to operate in a bias state prior to correction to the pullup charge pump current flowing from the charge pump. And a bias voltage adjustment control unit configured to increase the output voltage of the loop filter and to integrate the output voltage of the loop filter and generate a pull-down bias voltage corresponding to the magnitude of the sampled integrated voltage. The method of claim 7,
Selecting the magnitude of the bias current to flow in the delay cell, selecting the magnitude of the variable load capacitance to form at least a portion of the equivalent load capacitance appearing in the delay cell, and charging the equivalent load capacitance of the delay cell together with the bias current. And an automatic element adjusting circuit operable to select a magnitude of a control voltage versus an additional drive current gain for generating a possible additional drive current according to the control voltage. An open loop charge pump bias adjustment method for calibrating the charge pump in a frequency generating device including a charge pump and a loop filter,
Disconnecting the charge pump and the loop filter in the entire loop of the frequency generator;
During the pull-up period, setting the charge pump to operate in a bias state before correction to increase the output voltage of the loop filter by a pull-up charge pump current flowing from the charge pump;
Integrating an output voltage of the loop filter during the pull-up period and sampling at the end of the pull-up period to obtain an integrated voltage;
Generating a pull-down bias voltage corresponding to the magnitude of the integrated voltage;
Reconnecting the charge pump and the loop filter to the entire loop of the frequency generator; And
Driving a pulldown charge pump current in the charge pump by the generated pulldown bias voltage. The method of claim 9,
And setting the charge pump to operate in a pull-down period preceding the pull-up period to lower the output voltage of the loop filter by a pull-down charge pump current before correction flowing from the charge pump. Loop charge pump bias adjustment method. The method of claim 9, wherein generating a pull-down bias voltage corresponding to the magnitude of the integrated voltage comprises:
Comparing the integrated voltage to n reference voltages to generate an n-bit thermometer code comparison signal;
Generating an n bit charge pump correction signal based on the n bit thermometer code comparison signal;
And a pull-down bias voltage by current-to-voltage converting a variable current which is variable according to the n-bit charge pump correction signal.

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