KR20080014440A - Circuits and method for locking fast in phase lock frequency synthesizer - Google Patents

Abstract

A method and a circuit for synthesizing phase lock frequencies are provided to accelerate a phase-locking process by increasing a current gain of a charge pump circuit at an initial operation state. A phase-frequency detector(110) compares phases of a reference signal and a feedback signal with each other and generates up/down pulse signals. A charge pump circuit(120) generates a current signal which is varied in response to the up/down pulse signal. When a lock state is detected, the charge pump circuit recovers the bias current value to a normal value. The charge pump circuit generates a variable current signal in response to the up/down pulse, after the bias current is recovered to the normal value. A loop filter(130) integrates the current signal from the charge pump circuit and generates a control voltage signal. A VCO(Voltage Controlled Oscillator)(140) changes a frequency of the output signal in response to the control voltage signal from the loop filter. A divider(150) divides the output signal to generate a feedback signal and provides the feedback signal to the phase-frequency detector.

Description

Circuits and Method for Locking Fast in Phase Lock Frequency Synthesizer

1 is a block diagram of a typical PLL using a program counter.

2 shows a block diagram of a PLL using a prescaler operating at high speed.

3 is a block diagram of a fast locking phase synchronization circuit (FL-PLL: Fast Locking PLL) according to the present invention.

Figure 4 shows a preferred embodiment of a fast locking phase synchronization circuit (FL-PLL: Fast Locking PLL) according to the present invention.

5 is a timing diagram for explaining the locking time of the phase synchronization circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked frequency synthesis circuit and method, and more particularly, to a phase locked frequency synthesis circuit and method capable of quickly bringing a locking time in order to extend its application to high speed signal processing.

In general, satellite fixed frequency synthesis circuits are widely used to generate output frequencies that are phase-locked to the reference frequency by inputting the reference frequency. A key component of the satellite fixed frequency synthesis circuit is a phase locked loop circuit (PLL). The PLL is used to generate an internal clock signal synchronized with a reference clock signal supplied from an external source in a digital system or a local oscillation signal whose frequency and phase are synchronized with a signal received at a high frequency in a wireless communication system. PLLs are produced on individual semiconductor chips or on chip with other systems. Individual PLL chips are made to cover a wide frequency band for use at various frequencies. Recently, the demand for wideband PLLs is increasing due to the multibandization trend of communication systems such as portable terminals.

The implementation of such a wideband PLL has a problem in that an on-chip PLL having a faster lock time cannot be implemented because of design limitations when using multiple frequency bands in a wide band.

The object of the present invention is to set a large charge pump current gain that satisfies the design characteristics of the PLL before locking, and to restore the charge pump current gain to the normal design value after the PLL is locked to solve this problem. The present invention provides a phase-locked frequency synthesis circuit and method that can lock faster to enable faster locking time of an entire PLL.

Another object of the present invention is to provide a phase locked frequency synthesizing circuit capable of varying the current gain of the charge pump circuit in response to the locking detection.

In order to achieve the above object, the circuit of the present invention includes a phase frequency detector, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a divider. The phase frequency detector generates an up / down pulse signal by comparing the phase of the reference signal and the feedback signal. The charge pump circuit initially generates a variable current signal in response to an up / down pulse signal in a state where the bias current value is set larger than the normal value, and when the lock state is detected, changes the bias current value to a normal value and changes it to a normal value. Afterwards, a variable current signal is generated in response to the up / down pulse signal. The loop filter generates a control voltage signal by integrating the current signal provided from the charge pump circuit. The voltage controlled oscillator changes the frequency of the output signal in response to the control voltage signal provided from the loop filter. The divider divides the output signal to generate a feedback signal.

In the present invention, the charge pump circuit includes a pull-up circuit for switching an up bias current that is variable in response to an up bias control signal to an output node in response to an up signal of the phase frequency detector, and a down bias that is variable in response to a down bias control signal. A pull-down circuit for switching current to an output node in response to a down signal of the phase frequency detector, a lock detector for inputting a reference signal and a feedback signal to detect a lock state and generating a lock detection signal; Up and down bias control signals are generated such that the bias current has a larger value than normal, and when the lock state is detected in response to the lock detection signal, the up and down bias control signals are set so that the up and down bias currents have a normal value. It includes a bias control unit for generating a.

Here, the bias control unit generates a reference current generation unit for generating a reference current, and initially generates a bias current having a larger value in proportion to the reference current, and stops the generation of the bias current when a lock state is detected in response to the lock detection signal. And a current program unit for outputting the sum of the reference current and the bias current as up and down bias control signals provided to the pull-up circuit and the pull-down circuit, respectively. The current program unit may include a logic circuit outputting an n bit code value in response to the lock detection signal, a switch array including a plurality of switch elements switched in response to the n bit code value, and a current mirror coupled to the reference current generator. A plurality of current sources for generating a plurality of bias currents through the array.

The method of the present invention generates an up / down signal by comparing a phase of a reference signal and a feedback signal, and initially generates a current signal that is variable in response to an up / down pulse signal with a bias current value set larger than a normal value. When the locked state is detected, the bias current value is changed to a normal value, changed to a normal value, and a current signal that is variable in response to the up / down pulse signal is generated. Then, a control voltage signal is generated by integrating the current signal provided from the charge pump circuit, and the frequency of the output signal is changed in response to the control voltage signal provided from the loop filter. The output signal is divided to generate a feedback signal.

In the present invention, a phase locked loop (PLL) may be expressed as a phase locked loop or a phase locked loop by the same concept.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is described in sufficient detail to enable those skilled in the art to practice the invention.

Before describing the embodiments to help understand the present invention, a general PLL used in a frequency synthesizer will be described.

1 is a block diagram of a typical PLL using a program counter in a frequency synthesizer.

Referring to FIG. 1, the PLL 10 includes a phase comparator 12, a low pass filter 14, a voltage controlled oscillator 16, and a divider 18. The phase comparator 12 compares the reference frequency fr of the external clock signal ECLK with the comparison frequency fp of the comparison clock signal PCLK to generate an output signal according to the phase difference. The phase comparator 12 includes a phase frequency detector PFD and a charge pump circuit CP. The charge pump circuit CP generates, as an output signal, a current signal that varies according to the phase difference detected by the phase frequency detector PFD. The low pass filter 14 generates a voltage signal that maintains an average level by filtering the output signal of the phase comparator 10, that is, the ripple of the current signal. The voltage controlled oscillator 16 generates an internal clock signal ICLK whose frequency is varied in accordance with the voltage signal provided from the low pass filter 14. The divider 18 inputs an internal clock signal and divides it at a programmed constant 1 / N division ratio to generate a comparison clock signal PCLK.

That is, the frequency fvco of the internal clock signal ICLK is divided by 1 / N by the divider 18, negatively feedbacked by the comparison frequency fp, and input to the phase comparator 12 as the comparison clock signal PCLK. At this time, the output frequency fvco of the voltage controlled oscillator 16 is defined by the following equation (1).

[Equation 1]

Since fp = fr, Equation 1 may be expressed as Equation 2 below.

[Equation 2]

It can be seen from Equation 2 that the output frequency fvco can be changed by changing the value of N in steps of the reference frequency fr.

Therefore, when the output frequency fvco is used for a local oscillator or the like of various communication devices, various frequencies can be generated using the reference frequency provided from one crystal oscillator. The frequency generated in this way has the same stability as the crystal oscillator. Here, when the output frequency fvco becomes high, it is difficult to divide directly into the divider 18.

2 shows a block diagram of a PLL using a prescaler operating at high speed.

Therefore, a phase control loop circuit using a prescaler operating at high speed as shown in FIG. 2 is used.

2 is a block diagram illustrating a general PLL using a prescaler.

Referring to FIG. 2, the PLL 20 inputs an internal clock signal ICLK in comparison with the above-described PLL 10 to divide 1 / M and provide a divided signal to the divider 18. ) Is different.

The output frequency fvco of the voltage controlled oscillator 16 is first divided by 1 / M in the prescaler 19, and then again divided by 1 / N by the divider 18, negative feedback by the comparison frequency fp, and the phase comparator 12 Is entered.

Here, the comparison frequency fp is defined as in Equation 3.

[Equation 3]

Therefore, the output frequency fvco is arranged as shown in equation (4). Where fp = fr.

[Equation 4]

When the frequency division ratio N of the frequency divider 18 is changed in Equation 4, the output frequency fvco changes in steps of M x fr. Therefore, the channel separation, which is the frequency interval of the channel, is M x fr, and the reference frequency fr in the synthesizer is the frequency division ratio 1 / M of the channel separation.

As described above, the PLL according to the related art has a problem in that an on-chip PLL having a faster lock time cannot be implemented because of design limitations when using multiple frequency bands in a wide band.

3 is a block diagram of a fast locking phase synchronization circuit (FL-PLL: fast locking PLL) of a frequency synthesizer according to the present invention, and FIG. 4 is a fast locking phase synchronization circuit (FL-PLL: fast locking PLL) according to the present invention. One preferred embodiment of the is shown.

Referring to FIG. 3, the FL-PLL 100 of the present invention includes a phase frequency detector 110, a charge pump circuit 120, a loop filter 130, a voltage controlled oscillator 140, and a divider 150. do.

The phase frequency detector 110 inputs an external clock signal ECLK and a comparison clock signal PCLK to output an up signal and a down signal according to the phase difference between the two signals. The charge pump circuit 120 inputs an up signal and a down signal of the phase frequency detector 110 to output a corresponding current signal. The loop filter 130 removes (integrates) the ripple of the current signal provided from the charge pump circuit 120 and outputs a voltage signal having an average level of the current signal. The voltage controlled oscillator 140 inputs a voltage signal and outputs an output clock signal or an internal clock signal ICLK. The divider 150 inputs an internal clock signal ICLK and divides it at a programmed division ratio to generate a frequency-divided feedback signal and provides the feedback signal to the phase detector 110 as a comparison clock signal PCLK.

Referring to FIG. 4, the charge pump circuit 120 of the present invention includes a pull-up circuit 122, a pull-down circuit 124, a lock detector 126, and a bias controller 128.

The pull-up circuit 122 includes PMOS transistors PM9 and PM10 connected in series between the power supply terminal VCC and the output node ON. The up signal VUP provided to the phase frequency detector 110 is applied to the gate of the PM9, and the up bias signal BUP of the bias control unit 128 is applied to the gate of the PM10.

The pull-down circuit 124 includes NMOS transistors NM2 and NM3 connected in series between the ground terminal VSS and the output node ON. The down signal VDW provided to the phase frequency detector 110 is applied to the gate of NM3, and the down bias signal BDW is applied to the gate of NM2.

The lock detector 126 inputs the external clock signal ECLK and the comparison clock signal PCLK to generate the lock detection signal LKD. The Lal detector 126 is configured by applying a generally known lock detection circuit. Therefore, detailed description is omitted. The lock detection signal LKD is composed of a pulse signal that maintains a low state before the lock state and a high state after the lock state. That is, the timing at which the state of the lock detection signal LKD transitions from the low state to the high state is determined as the lock detection time.

The bias control unit 128 includes a reference signal generator 128a, a current program unit 128b, and an output unit 128c.

The reference signal generator 128a includes a current source CS1 and PMOS transistors PM1 and PM2. The PMOS transistors PM1 and PM2 are coupled to a current mirror to mirror the reference current set by the current source CS1 to the node N1.

The current program unit 128b includes a logic circuit LC, switch arrays SW1 to SW5, and PMOS transistors PM3 to PM7. The logic circuit LC inputs the lock detection signal LKD to generate the code value 11111 in order to supply the maximum current to the node N1 in the low state of the lock detection signal. (00000) occurs. For example, the logic circuit uses five D flip-flops to set all output signals of the D flip-flop to a high state, that is, a "1" state when the lock detection signal is in a low state. This can be accomplished by resetting all of the flop's output signals to a low state, i.

In addition, the logic circuit LC is configured as a 5-bit down counter to start down counting in the initial low state of the lock detection signal to generate a code value whose output value is gradually decreased from " 11111 " to " 00000 " The transition to the state may be implemented to maintain the output of the down counter in the "00000" state.

The switch arrays SW1 to SW5 correspond to each bit of the code value provided from the logic circuit LC and are turned on in the "1" state of each bit and turned off in the "0" state.

The PMOS transistors PM3 to PM7 are coupled to a current mirror of PM1 of the reference signal generator 128a and have a x1, x2, x4, x8, and x16 ratio of the current driving capability (W / L: channel width / channel length) of the PM1. Implemented in proportions. Therefore, each PM3 to PM7 operates as a current source for providing the node N1 with a current corresponding to the designed current driving capability. Therefore, if the reference current is I, the maximum current value that can be provided by the node N1 in the current program is set to 31 times the reference current. These currents may be transmitted to the node N1 through the turn-on state of the switches SW1 to SW5. Therefore, depending on the turn-on / turn-off combination of these switches, the bias current can be programmed between 1 and 32 times the reference current.

The output unit 128c includes NMOS transistors NM1 and NM2 and PMOS transistor PM8. NM1 and NM2 are coupled to a current mirror to cause a current equal to the current flowing in node N1 to flow to node N2. In addition, since NM1 is coupled to the current mirror of NM3 of the pull-down circuit 124, NM3 is biased in such a manner that a bias current having the same current as that flowing through the node N1 can be driven to the output node ON. Since the PM8 is coupled to the current mirror of the PM10 of the pull-up circuit 122, the PM10 is biased in such a state that the bias current having the same current as that flowing through the node N2 can be driven to the output node ON.

Therefore, initially, the frequency of the feedback signal follows the frequency of the reference signal with the maximum current so that the lock state can be quickly achieved. When the controller enters the locked state, the steady state, that is, the continuous lock state is maintained at the reference current level.

5 is a timing diagram for explaining the locking time of the phase synchronization circuit according to the present invention.

Referring to FIG. 5, the A waveform is a case where the current gain of the charge pump circuit is 0.4 mA, and the B waveform is a case where the current gain is set to 4 mA, and after the lock, the current gain of the charge pump circuit is set to 0.4 mA. Indicates. The C waveform is a waveform representing the lock detection state. It can be seen that the locking time is about 50% faster than that of the B waveform in comparison with the A waveform.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the fast locking phase synchronization circuit according to the present invention initially increases the current gain of the charge pump circuit to be larger than the normal value, thereby speeding up the locking operation, and restoring the current gain of the charge pump circuit to the normal value after locking. Improve the performance of the PLL.

Incorporating the present invention, it is possible to implement the excellent performance of the PLL even faster lock time when the entire PLL circuit consists of a single chip. The present invention can effectively design a PLL when designing a PLL that covers a wider frequency.

Claims (5)

A phase frequency detector for generating an up / down pulse signal by comparing a phase of a reference signal and a feedback signal; Initially, a variable current signal is generated in response to the up / down pulse signal in a state where the bias current value is set larger than the normal value, and when the locked state is detected, the bias current value is changed to a normal value and then changed to the normal value. A charge pump circuit for generating a current signal varying in response to an up / down pulse signal; A loop filter for generating a control voltage signal by integrating the current signal provided from the charge pump circuit; A voltage controlled oscillator for changing a frequency of an output signal in response to a control voltage signal provided from the loop filter; And And a divider which divides the output signal to generate a feedback signal and provides the generated feedback signal to the phase frequency detector. The method of claim 1, wherein the charge pump circuit A pull-up circuit for switching an up bias current that is varied in response to an up bias control signal to an output node in response to an up signal of the phase frequency detector; A pull-down circuit for switching a down bias current that is varied in response to a down bias control signal to an output node in response to a down signal of the phase frequency detector; A lock detector configured to input the reference signal and a feedback signal to detect a lock state and generate a lock detection signal; And Initially, the up and down bias control signals are generated such that the up and down bias currents have a value greater than the normal value, and when the lock state is detected in response to the lock detection signal, the up and down bias currents are set to normal values. And a bias control unit for generating the up and down bias control signals to have a phase fixed frequency synthesizing circuit. The method of claim 2, wherein the bias control unit A reference current generator for generating a reference current; A current program unit generating a bias current having a larger value in proportion to the reference current and stopping the generation of the bias current when a lock state is detected in response to the lock detection signal; And an output unit for outputting the sum of the reference current and the bias current as an up and down bias control signal provided to the pull-up circuit and the pull-down circuit, respectively. The method of claim 3, wherein the current program unit A logic circuit for outputting an n bit code value in response to the lock detection signal; A switch array including a plurality of switch elements switched in response to the n-bit code value; And And a plurality of current sources coupled to the reference current generating unit by a current mirror and generating a plurality of bias currents through the switch array. Generating an up / down signal by comparing a phase of a reference signal and a feedback signal; Initially, a variable current signal is generated in response to the up / down pulse signal in a state where the bias current value is set larger than the normal value, and when the locked state is detected, the bias current value is changed to a normal value and then changed to the normal value. Generating a variable current signal in response to an up / down pulse signal; Generating a control voltage signal by integrating the current signal provided from the charge pump circuit; Changing a frequency of an output signal in response to a control voltage signal provided from the loop filter; And And dividing the output signal to generate the feedback signal.

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