JP4471849B2 - PLL frequency synthesizer circuit and frequency tuning method thereof - Google Patents

Description

  The present invention relates to a PLL frequency synthesizer circuit and a frequency tuning method thereof.

  New functions are added to small mobile wireless devices typified by mobile phones every time the model is changed, and certain restrictions are imposed on the external dimensions, weight, and price of the device. For this reason, parts to be used are always required to be smaller, lighter and cheaper.

  A circuit called a PLL frequency synthesizer is usually used in a radio unit of a mobile radio device for generating a reference signal for transmission and reception.

  The PLL frequency synthesizer circuit is a negative feedback feedback loop circuit in which the oscillation frequency is automatically adjusted, and the oscillation frequency of the PLL frequency synthesizer is used as a reference signal.

  Conventionally, a PLL frequency synthesizer has a voltage-controlled oscillator (VCO: Voltage Controlled Oscillator) in which a circuit is modularized by discrete components because a high C / N (C / N: Carrier to Noise ratio) is required. It has been very common to configure a low-pass filter circuit (LPF circuit: Low Pass Filter) using discrete components and an IC in which other circuits are integrated.

  In recent years, in order to reduce the mounting area of the PLL frequency synthesizer on the board of the radio unit, attempts have been made to incorporate a voltage-controlled oscillation circuit and a low-pass filter circuit into a semiconductor integrated circuit, which have been difficult to incorporate into an IC with conventional technology. It is in a very active situation.

  Hereinafter, a conventional PLL frequency synthesizer circuit will be described in more detail.

<Basic configuration and operation of PLL frequency synthesizer>
FIG. 13 is a block diagram showing a configuration of a general PLL frequency synthesizer circuit.

  The PLL frequency synthesizer circuit shown in FIG. 13 is generally widely used as a reference frequency generation circuit of a wireless communication circuit, and includes a phase comparison circuit 901, a low-pass filter (LPF) circuit 902, a voltage controlled oscillation circuit 903, and The oscillation output 908 is configured by a feedback loop including a frequency dividing circuit 904, and the oscillation output 908 is used as a reference frequency for the transmitter circuit and the receiver circuit of the wireless communication circuit.

  The phase comparison circuit 901 detects the phase difference between the reference signal 905 input to the PLL frequency synthesizer and the output 909 of the frequency dividing circuit 904, and outputs a current or voltage 906 proportional to the phase difference.

  The low-pass filter circuit 902 gives a signal 907 obtained by removing a high frequency component from the output of the phase comparison circuit 901 to the voltage controlled oscillation circuit 903.

  The frequency dividing circuit 904 feeds back a signal 909 obtained by dividing the frequency of the output 908 of the voltage controlled oscillation circuit 903 to 1 / N (N frequency division) to the phase comparison circuit 901.

  With this configuration, in the negative feedback loop of the frequency synthesizer circuit, the phase of the signal 909 is adjusted so that the output 906 of the phase comparison circuit 901 becomes zero, and the frequency of the oscillation output 908 is the reference signal 905 in a steady state. The frequency is N times.

<Description of Configuration and Operation of CMOS VCO (Voltage Controlled Oscillation Circuit)>
In recent years, in order to reduce the mounting area of the PLL frequency synthesizer circuit on the device substrate, attempts have been actively made to incorporate a voltage controlled oscillation circuit and a low-pass filter circuit that have been difficult to incorporate into an IC into a semiconductor integrated circuit. It is as described above.

  14 to 16 are circuit diagrams showing a voltage-controlled oscillation circuit using CMOS transistors described in Non-Patent Document 1. FIG.

  FIG. 14 shows the basic circuit.

  The basic circuit shown in FIG. 14 includes first and second inductors 1001 and 1002, first and second variable capacitance elements 1003 and 1004, and first to third NMOS transistors 1005, 1006 and 1007. It is prepared for.

  In the circuit shown in FIG. 14, NMOS transistors 1005 and 1006 are used as active elements for obtaining a negative resistance, and a MOS capacitor using a gate-back gate composed of NMOS transistors 1003 and 1004 is used as a variable capacitance element. It has been. The capacitance values of the NMOS transistors 1003 and 1004 are equal to each other, and the inductor values of the inductors 1001 and 1002 are equal to each other.

  In the oscillation circuit of FIG. 14, if the capacitance of 1003 or 1004 is set to Cv and the inductor value of 1001 or 1002 is set to L1, the parallel frequency of Cv and L becomes the oscillation frequency fvco1 and is obtained by Equation 1.

fvco1 = 1 / (2 · π · (L1 · Cv) ^1/2 ) (1)
FIG. 15 includes capacitance switching circuits (Tuning Capacitor circuits) 1011 and 1012 having variable capacitance elements corresponding to the NMOS transistors 1003 and 1004 in the basic circuit of FIG. 14 in order to widen the oscillation frequency range.

  In FIG. 15, the capacitance switching circuits 1011 and 1012 each have the configuration shown in FIG. 16, and the variable capacitance element 1021 corresponds to the NMOS transistor 1003 or 1004 in FIG. The capacitance switching circuits 1011 and 1012 are configured to include a variable capacitance element 1021, capacitances 1022, 1023, and 1024 weighted with respective capacitance values C, 2C, and 4C, and NMOS transistors 1025, 1026, and 1027, respectively. Yes. The parallel capacitance Cvp synthesized by the variable capacitance element 1021 and the capacitances 1022, 1023, and 1024 is widened by controlling whether the capacitances 1022, 1023, and 1024 are grounded to GND by turning on / off the NMOS transistors 1025, 1026, and 1027. Variable in range. Further, by changing the control potential Vc applied to the back gate of the variable capacitance element 1021, the parallel capacitance Cvp synthesized by the variable capacitance element 1021, the capacitances 1022, 1023, and 1024 can be finely adjusted. Further, if the relationship between the capacitance change range ΔCvp of the variable capacitance element 1021 due to Vc and the capacitance value C of the capacitor 1022 is set to satisfy C <ΔCvp, the resonance frequency of the inductor 1013 and the capacitance switching circuit 1011, the inductor The resonance frequency of 1014 and the capacity switching circuit 1012 can be continuously varied, and the oscillation frequency fvco2 can also be continuously varied. Therefore, fvco2 can be varied in a wider frequency range than the circuit of FIG. 14. If the inductor values of the inductors 1013 and 1014 are L2, fvco2 can be obtained by Expression (2).

fvco2 = 1 / (2 · π · (L2 · Cvp) ^1/2 ) (2)
Further, Patent Document 1 shows an example in which the capacitance switching circuit of FIG. 17 is configured using only variable capacitance elements as a mechanism for changing the oscillation frequency of the CMOS VCO over a wide range.

  That is, as shown in FIG. 17, the circuit of FIG. 1 of Patent Document 1 includes a plurality of variable capacitance elements 1111, 1112, 1113, 1114, and frequency control corresponding to each variable capacitance element 1111 to 1114 on a one-to-one basis. Terminals 1121, 1122, 1123, and 1124, a resonance circuit 1101, a negative resistance circuit 1102, and a transmission output terminal 1103, and variable bias elements corresponding to bias potentials applied to the frequency control terminals 1121 to 1124, respectively. 15 is an example of a circuit that can realize a function equivalent to the capacitance switching circuit in the circuit of FIG. 15 by switching between a potential at which the capacitance change of 1111 to 1114 is saturated and minimized.

  Note that, as shown in FIGS. 14 to 17, PLL frequency synthesizer circuits using a VCO whose frequency can be varied widely by switching the capacitance of the capacitive resonance circuit include Patent Document 2, Patent Document 3, Patent Document 3, There are many known examples such as Patent Document 4.

  FIG. 18 is a circuit diagram showing a PLL frequency synthesizer circuit of Patent Document 4.

  As shown in FIG. 18, the PLL frequency synthesizer circuit of Patent Document 4 includes a VCO block 1210, a VCO selector 1220, an R frequency divider 1231 constituting a PLL unit, a phase frequency comparator (PD) 1232, and a charge pump. (CP) 1233, a low-pass filter (LPF) 1234, an N frequency divider 1235, three change-over switches 1241, 1242, 1243 used for frequency selection operation, and a bias voltage source 1244.

  The PLL frequency synthesizer circuit in FIG. 18 uses an external reference signal (frequency: fref) as an input signal, and obtains an output signal (frequency: fvco) obtained by multiplying the input signal.

  The VCO block 1210 includes m voltage controlled oscillators VCO0 (oscillation frequency: f0), VCO1 (oscillation frequency: f1), VCO2 (oscillation frequency: f2),... -It has VCOm-1 (oscillation frequency: fm-1). These m voltage controlled oscillators VCO0 to VCOm-1 are provided with m VCO selection signals VCOsel <0>, VCOsel <1>, VCOsel <2>,..., VCOsel output from the VCO selector 1220. Any one is selected and used according to <m>. However, there is a relationship of f0 <f1 <f2 <... <Fm−1 among the m oscillation frequencies.

  The PLL frequency synthesizer circuit of FIG. 18 is an example that embodies a mechanism that can select a VCO that can oscillate at a frequency to be locked in advance among m VCOs before the PLL frequency lock operation. In this example, selection of VCO is specified by the control signals VCOSEL <0> to VCOSEL <m−1>, and the relationship between the control voltage Vcont of each VCO and the oscillation frequency fvco is continuous as shown in FIG. Thus, the oscillation frequency ranges are set to overlap between adjacent VCOs so that the oscillation frequency can be varied over a wide range. The mechanism for switching the VCO can be said to be a means for realizing essentially the same function as the method of switching the range of the oscillation frequency of the VCO by switching the capacitance of the resonance circuit shown in FIGS.

The PLL frequency synthesizer of FIG. 18 oscillates each VCO after charging a fixed potential to the LPF circuit by a bias voltage source 1244 before an operation for locking the frequency to a desired frequency (hereinafter referred to as a lock operation). The frequency is counted by the counter 1221, the oscillation frequency range of each VCO is stored in advance from the counted value, and a mechanism for selecting the optimum VCO according to the frequency to be locked is realized.
JP 2001-352218 A (FIG. 1) Japanese Patent Laid-Open No. 07-303041 JP-A-10-200406 JP 2004-260387 A ISSCC (International Solid-State Circuits Conference) 2001, Session 23 AnalogTechniques 4, “A Filtering Technology to Lower Oscillator Phase Noise”, UCLA Abidi, etc.

  However, in a PLL frequency synthesizer circuit using a VCO whose frequency can be varied widely by switching the capacitance of the capacitive resonance circuit as shown in FIGS. 14 to 17, the VCO oscillation frequency is set before the frequency lock operation of the PLL loop. It is necessary to provide a mechanism for searching for the set value of the switching capacity in advance so that the frequency to be locked exists within the range.

  When searching for the set value of the switching capacitor in advance, it is necessary to fix the control voltage of the voltage controlled oscillator to a certain value. However, the circuit of FIG. 14 to FIG. 16 and the VCO circuit of Patent Document 1 (FIG. 17) uses the N-Well capacitor, which is a kind of MOS capacitor, as the variable capacitor for adjusting the oscillation frequency of the VCO, and therefore the following problems arise.

  The CV characteristics of the N-well capacity are shown in FIG. 7, and the N-well capacity is determined when searching for the set value of the switching capacity so that the voltage controlled oscillator linearly changes the frequency with respect to the control voltage. It is preferably biased to the center of the linear region 403 in FIG.

  However, in the case of a normal CMOS process, the range (change region) 402 in which the capacitance value changes in proportion to Vtune is as narrow as about 1 V, and the linear region 403 in which the capacitance changes linearly in proportion to Vtune is 0. In many cases, only about 5V can be obtained. Further, the CV characteristic of the N-well capacitance is affected by device variations during semiconductor manufacturing (hereinafter simply referred to as manufacturing variations) and temperature during operation, and the Vtune range in which a linear region of CV characteristics can be obtained. Moves to the left and right, and the slope of the characteristics in the linear region also changes.

  Further, as shown in FIG. 14, since the bias voltage across the N-Well capacitor can be the difference between the control voltage Vc and the power supply voltage, in this case, the Vc applied when searching for the set value of the switching capacitor. The value needs to follow changes in the power supply voltage.

  Therefore, when searching for the set value of the switching capacitor, even when conditions such as manufacturing variation, temperature, and power supply voltage change, the N-Well capacitor is always biased to the center of the linear region 403 of its CV characteristic. It becomes difficult to keep.

  In Patent Document 1, the method for correcting the characteristic change of the N-well capacity has specific descriptions in paragraphs 23 and 24, FIGS. 3, 4, 5, and the like.

  That is, in paragraph 23 of Patent Document 1, “For example, a predetermined voltage is applied from the frequency control terminal 8 at the time of factory shipment inspection,..., Frequency deviation due to manufacturing variation can be corrected”. Although there is an explanation, in the method of giving a constant voltage to the control terminal, there may be a case where the constant voltage becomes a potential at which the capacity change characteristic of the N-well capacitance is saturated due to element variation, and this method is suitable for mass production. It's hard to say.

  Paragraph 24 of Patent Document 1 describes a method of monitoring the frequency by a counter or the like and feeding back the result to the control voltage output by the frequency correction signal generation circuit. When the characteristic change is large, it is easily estimated that the error (deviation) of the oscillation frequency exceeds the correction range only by adjusting the potential applied to the single N-Well capacitor.

  The present invention has been made to solve the above-described problems, and a PLL frequency synthesizer circuit capable of bringing the oscillation frequency of a voltage-controlled oscillation circuit closer to a desired lock frequency more reliably than before, and its frequency An object is to provide a tuning method.

  In order to solve the above problems, a PLL frequency synthesizer circuit of the present invention uses a resonance frequency of an LC resonance circuit including a capacitor, an inductor, and a variable capacitance element in a PLL frequency synthesizer circuit integrated on a semiconductor integrated circuit. A negative feedback feedback loop that includes a voltage controlled oscillation circuit that oscillates and oscillates, and loops an oscillation signal output from the voltage controlled oscillation circuit to adjust a frequency of the signal to a desired lock frequency. A tuning means for tuning the oscillation frequency to be close to the lock frequency by adjusting a capacitance value of the capacitor of the voltage controlled oscillation circuit before the frequency pulling operation; The variable capacitance element of the voltage controlled oscillator circuit during tuning operation It is characterized by comprising a reference potential applying means capable of applying a reference potential, to the.

  The configuration of the PLL frequency synthesizer circuit of the present invention is such that the capacitance characteristic of the variable capacitance element is more linear than the absolute value of the voltage that can be applied from the first terminal to the second terminal of the variable capacitance element as the variable capacitance element. This is preferable in the case of using an element having a characteristic in which the voltage range that changes with time is narrow.

  The configuration of the PLL frequency synthesizer circuit of the present invention is preferable when a MOS capacitor is used as the variable capacitor. That is, in this case, one of the first and second terminals of the variable capacitance element is constituted by a semiconductor (N-type semiconductor (N-Well) or P-type semiconductor (P-Well)).

  In the PLL frequency synthesizer circuit of the present invention, when the frequency change amount of the oscillation frequency switching step by adjusting the capacitance value is fvco_step and the variable range of the oscillation frequency by voltage control is Δfvco, the value of fvco_step is fvco_step. It is preferably set so as to satisfy ≦ Δfvco / 4.

  In the PLL frequency synthesizer circuit of the present invention, the reference potential applying means selectively selects one of two kinds of potentials with respect to the variable capacitance element of the voltage controlled oscillation circuit during the tuning operation. It is preferably configured to be able to be applied.

  In the PLL frequency synthesizer circuit of the present invention, the two kinds of potentials are preferably fixed potentials.

  In the PLL frequency synthesizer circuit of the present invention, each of the two types of potentials is preferably set to a value that saturates the CV characteristic of the variable capacitance element.

  In the PLL frequency synthesizer circuit according to the present invention, each of the two kinds of potentials is caused by at least one of the following: a variation in manufacturing of the variable capacitance element, a variation in power supply voltage, and a variation in ambient temperature. Even if the CV characteristic of the variable capacitance element fluctuates, it is preferable to set the value so that the CV characteristic is saturated.

  In the PLL frequency synthesizer circuit of the present invention, it is preferable that one of the two kinds of potentials is a power supply potential and the other is a ground potential (GND potential).

  In the PLL frequency synthesizer circuit according to the present invention, the voltage-controlled oscillation circuit includes a plurality of capacitors, and the tuning unit adjusts the capacitance value by selecting an arbitrary combination of the plurality of capacitors. It is preferable that it is comprised.

  In the PLL frequency synthesizer circuit of the present invention, the tuning means applies one of the two kinds of potentials to the variable capacitance element of the voltage controlled oscillation circuit before the frequency pulling operation. A first tuning operation for searching for a first set value of the capacitance value of the capacitor such that the oscillation frequency is closest to the lock frequency by adjusting a capacitance value of the capacitor of the voltage controlled oscillation circuit; By adjusting the capacitance value of the capacitor of the voltage controlled oscillation circuit while applying the other potential of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit, the oscillation frequency is A second tuning operation for searching for a second set value of the capacitance value that is closest to a lock frequency; and the capacitance value is set to the first and second settings. It is preferable that the third and tuning operation for setting the third set value in the vicinity of the middle, and is configured to be capable of executing a series of tuning operation consisting of.

  In this case, the voltage-controlled oscillation circuit is configured to include a plurality of capacitors, and in the first tuning operation, the tuning unit determines the capacitance value by selecting an arbitrary combination of the plurality of capacitors. While searching for the first set value by adjusting, in the second tuning operation, by adjusting the capacitance value by selecting any combination of the plurality of capacitances, It is preferable to search for a set value of 2.

  In the PLL frequency synthesizer circuit of the present invention, the PLL frequency synthesizer circuit includes a holding unit that holds a value of the potential applied to the variable capacitance element in the locked state adjusted to the lock frequency by the frequency pulling operation, and the tuning unit includes the tuning unit, It is preferable that the tuning operation can be performed while the potential of the value held by the holding unit is supplied to the variable capacitance element.

  In this case, an A / D converter that converts the potential applied to the variable capacitance element into a digital value, an analog potential corresponding to the digital value held by the holding unit is generated, and the generated analog potential is A D / A converter capable of supplying the variable capacitance element, and the holding unit holds the digital value output from the A / D converter, thereby applying the digital value to the variable capacitance element in the locked state. The tuning means generates an analog potential corresponding to the digital value held by the holding unit to the D / A converter, and the generated analog potential is stored in the variable capacitor. It is preferable that the potential of the value held by the holding unit is supplied to the variable capacitance element by being supplied to the element.

  In the PLL frequency synthesizer circuit of the present invention, the voltage-controlled oscillation circuit is configured to include a plurality of capacitors, and the tuning unit supplies the potential of the value held by the holding unit to the variable capacitance element. In the tuning operation to be performed, by adjusting the capacitance value by selecting an arbitrary combination of the plurality of capacitors, a fourth set value of the capacitance value is set such that the oscillation frequency is closest to the lock frequency. It is preferably configured to search.

  In the PLL frequency synthesizer circuit of the present invention, the tuning means performs the first, second and second tuning operations in the tuning operation performed before the first frequency pull-in operation after powering on the PLL frequency synthesizer circuit. The holding unit holds the value of the potential applied to the variable capacitance element in the locked state adjusted to the lock frequency by the frequency pull-in operation performed after the third tuning operation. Then, the tuning means supplies the variable capacitance element with the potential of the value held by the holding unit for the tuning operation performed before the frequency pulling operation for the second and subsequent times after the power supply to the PLL frequency synthesizer circuit is turned on. However, it is preferable to be configured so that it can be performed.

  In the PLL frequency synthesizer circuit of the present invention, the holding unit performs an operation of newly holding the value of the potential applied to the variable capacitance element in the locked state adjusted to the lock frequency by the frequency pulling operation. Therefore, it is preferable to be configured to shift from the normal state to the resting state.

  In this case, the tuning means performs a tuning operation to be performed before the frequency pulling operation when the PLL frequency synthesizer circuit returns from the sleep state to the normal state, and sets the potential of the value held by the holding unit to the variable capacitance element. It is preferable that it can be performed while being supplied to

  In the PLL frequency synthesizer circuit of the present invention, an operating environment change detecting means for detecting a change in operating environment of the PLL frequency synthesizer circuit is provided, and the holding unit detects a change in the operating environment by the operating environment change detecting means. In such a case, it is preferable that the holding value update operation for newly holding the value of the voltage applied to the variable capacitance element in the locked state is performed.

  In this case, when a change in the operating environment is detected by the operating environment change detecting unit, the tuning unit performs the first, second, and third tuning operations, and the holding unit includes: It is preferable that the hold value update operation is performed in a lock state in which the lock is adjusted to the lock frequency by a frequency pull-in operation in a state where the capacitance value is set to the third set value.

  Alternatively, in the PLL frequency synthesizer circuit of the present invention, the PLL frequency synthesizer circuit includes a timing unit that counts an elapsed time since the holding unit last performed the holding operation of the voltage value applied to the variable capacitance element, and the holding unit includes: It is also preferable that when the predetermined time is counted by the time measuring means, a holding value update operation for newly holding the value of the voltage applied to the variable capacitance element in the locked state is performed. .

  In this case, when the predetermined time is measured by the time measuring means, the tuning means performs the first, second and third tuning operations, and the holding unit has the capacitance value of the first time. Preferably, the holding value update operation is performed in the locked state adjusted to the lock frequency by the frequency pull-in operation in the state set to the set value of 3.

  A frequency tuning method for a PLL frequency synthesizer circuit according to the present invention includes a voltage controlled oscillation circuit that oscillates using a resonance frequency of an LC resonant circuit including a capacitor, an inductor, and a variable capacitance element, and the voltage controlled oscillation In a method of tuning the oscillation frequency of a PLL frequency synthesizer circuit including a negative feedback feedback loop circuit capable of performing a frequency pull-in operation for looping an oscillation signal output from a circuit and adjusting the frequency of the signal to a desired lock frequency, By adjusting the capacitance value of the capacitor of the voltage controlled oscillation circuit while applying one of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit before the frequency pulling operation. , The first capacitance value such that the oscillation frequency is closest to the lock frequency. A first tuning step for searching for a set value, and a capacitance value of the capacitor of the voltage controlled oscillation circuit while applying the other potential of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit By adjusting a second tuning step for searching for a second set value of the capacitance value such that the oscillation frequency is closest to the lock frequency, and the capacitance value used for generation of the resonance frequency. And a third tuning step for setting a third set value in the vicinity of the middle between the first and second set values.

  In the PLL synthesizer circuit frequency tuning method of the present invention, the second tuning step starts with the first set value obtained in the first tuning step as an initial value of the capacitance value. This is preferable because the search time required in the second tuning step can be shortened.

  The frequency tuning method for a PLL frequency synthesizer circuit according to the present invention includes a holding step of holding a value of a potential applied to the variable capacitance element in a locked state adjusted to the lock frequency by the frequency pulling operation, and the holding Before the frequency pull-in operation after the process, the tuning operation is performed while supplying the potential of the value held in the holding process to the variable capacitance element instead of the first, second, and third tuning processes. It is preferable to execute a fourth tuning step for performing the above.

  According to the present invention, a PLL frequency synthesizer circuit integrated on a semiconductor integrated circuit includes a voltage-controlled oscillation circuit that oscillates using a resonance frequency of an LC resonance circuit including a capacitor, an inductor, and a variable capacitance element. A negative feedback feedback loop circuit configured to loop the oscillation signal output from the voltage controlled oscillation circuit and adjust the frequency of the signal to a desired lock frequency, and before the frequency pulling operation Tuning means for tuning the oscillation frequency to be close to the lock frequency by adjusting a capacitance value of the capacitor of the voltage controlled oscillation circuit; and the voltage controlled oscillation circuit during tuning operation by the tuning means And a reference potential applying means for applying a reference potential to the variable capacitance element. Since, the tuning operation than conventional reliably the oscillation frequency can be made closer to the desired lock frequency.

  Embodiments according to the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram showing a PLL frequency synthesizer circuit according to the first embodiment of the present invention, and also shows a circuit diagram as a basis of a second embodiment to be described later.

  As shown in FIG. 1, a PLL frequency synthesizer circuit according to this embodiment includes a phase frequency comparison circuit 601, a low-pass filter circuit (hereinafter also abbreviated as LPF circuit) 603, a voltage controlled oscillation circuit (hereinafter abbreviated as VCO). 604), a variable frequency dividing circuit 605, a frequency dividing number control circuit 606, a VCO automatic tuning circuit (tuning means) 607 and a reference voltage generating circuit (reference potential applying means) 608. It is integrated on an integrated circuit (not shown).

  Among these, the phase frequency comparison circuit 601 outputs a current or voltage proportional to the phase difference or frequency difference between the reference frequency signal REF and the output signal SIG of the variable frequency dividing circuit 605.

  The reference voltage generation circuit 608 includes a reference voltage source 630 and switches 632 and 633 that operate in the opposite state to each other. The reference voltage generation circuit 608 is a region in which the capacitance-voltage characteristics of variable capacitance elements 616 and 617 (described later) of the VCO 604 change linearly. It has a function capable of supplying a certain point of potential Vref to the LPF circuit 603 and the VCO 604.

  Among these, the reference voltage source 630 has one end grounded and the other end connected to the switch 632.

  Under the control of the VCO automatic tuning circuit 607, the switch 632 is converted into a state in which the reference voltage source 630 and the LPF circuit 603 (and the VCO 604 ahead) are connected to each other and a state in which they are disconnected from each other.

  In addition, the switch 633 converts the output of the phase frequency comparison circuit 601 and the LPF circuit 603 (and the VCO 604 ahead) from each other into a state where they are disconnected from each other and a state where they are disconnected from each other under the control of the VCO automatic tuning circuit 607. Is done.

  Here, in a steady state (a state in which the PLL frequency synthesizer circuit is locked to a desired frequency), the switch 633 is in a closed state (a state in which the phase frequency comparison circuit 601 and the LPF circuit 603 are connected to each other). 632 is in an open state (a state where the reference voltage source 630 and the LPF circuit 603 are separated from each other). Therefore, in a steady state, the output of the phase frequency comparison circuit 601 passes through the reference voltage generation circuit 608 and is supplied to the LPF circuit 603 as it is.

  The LPF circuit 603 includes capacitors 6341 and 6342 and a resistor 635. Among these, one end of the capacitor 6341 is grounded, the other end is connected to one end of the reference voltage generation circuit 608 and the resistor 635, the other end of the resistor 635 is connected to one end of the capacitor 6342, and the other end of the capacitor 6342 is grounded. Yes. Further, the one end of the resistor 635 is also connected to the terminal 610 of the VCO 604.

  The LPF circuit 603 configured in this manner removes an AC component from the output signal of the phase frequency comparison circuit 601 and gives a voltage signal Vcont (control voltage) for controlling the oscillation frequency to the terminal 610 of the VCO 604.

  The VCO 604 is an LC type oscillation circuit that uses an inverter circuit composed of a combination of a PMOS transistor and an NMOS transistor in a negative resistance circuit.

  Of these, a combination of the PMOS transistor 611 and the NMOS transistor 612 and a combination of the PMOS transistor 613 and the NMOS transistor 614 correspond to the inverter circuit.

  The LC resonance circuit for varying the oscillation frequency includes an inductor 615, variable capacitance elements 616 and 617, capacitance arrays 618, 619, 620, 621, 622, and 623 weighted capacitance values and switches 624 and 625. , 626, 627, 628, and 629, n (for example, 6) capacitor arrays.

  Among these, the frequency is finely adjusted by the variable capacitance elements 616 and 617, and the frequency can be varied in a wide range by the capacitance array. Here, as the variable capacitance elements 616 and 617, if a normal CMOS process is used, an NMOS capacitance (N-Well capacitance) or a PMOS capacitance (P-Well capacitance) is used. That is, FIG. 1 shows an example in which the NMOS capacitors shown in FIG. 6 (structure) and FIG. 7 (characteristics) are used as the variable capacitance elements 616 and 617.

The NMOS capacitor (N-Well capacitor) shown in FIG. 6 has a first terminal X formed of a conductor such as metal or polysilicon and a second terminal formed of a semiconductor (N-Well which is an N-type semiconductor). A structure in which an insulator such as SiO ₂ is sandwiched between the terminal Y and the terminal X and the terminal Y functions as a capacitor.

  The CV characteristic of the NMOS capacitor (N-Well capacitor) shown in FIG. 6 is as shown in FIG. 7, and changes depending on the voltage Vtune applied between the terminal X and the terminal Y. As Vtune, Voltage application up to the absolute value of the difference from the power supply voltage VDD is possible (FIG. 7, applied voltage range 401). In the case of a normal CMOS process, a range (change region) 402 in which the capacitance value changes in proportion to Vtune is as narrow as about 1 V, and a linear region 403 in which the capacitance changes linearly in proportion to Vtune is further provided. In many cases, it becomes narrow and only about 0.5V can be obtained. That is, the variable capacitance elements 616 and 617 included in the VCO 604 in the present embodiment are elements in which the linear region 403 is narrower than the applied voltage range 401.

  Here, the connection relationship of each component in the VCO 604 will be described.

  The variable capacitance element 616 and the variable capacitance element 617 are connected to each other on the semiconductor side (second terminal Y), and the connection point is connected to the terminal 610.

  Also, the conductor electrode side terminal (first terminal X) of the variable capacitance element 616 is connected to one end of the inductor 615, and the conductor electrode side terminal of the variable capacitance element 617 is connected to the other end of the inductor 615. Yes. Here, a connection point between the conductor side terminal of the variable capacitance element 616 and the inductor 615 is a point P1, and a connection point between the conductor side terminal of the variable capacitance element 617 and the inductor 615 is a point P2.

  The source terminal of the PMOS transistor 611 is connected to the power supply potential (VDD), the drain terminal is connected to the drain terminal of the NMOS transistor 612, the gate terminal is connected to the gate terminal of the NMOS transistor 612, and the source terminal of the NMOS transistor 612 is the current terminal. Connected to the source.

  Similarly, the source terminal of the PMOS transistor 613 is connected to the power supply potential (VDD), the drain terminal is connected to the drain terminal of the NMOS transistor 614, the gate terminal is connected to the gate terminal of the NMOS transistor 614, and the source terminal of the NMOS transistor 614 is Connected to a current source.

  The gate terminals of the PMOS transistor 611 and the NMOS transistor 612 are connected to a connection point between the drain terminal of the PMOS transistor 613 and the drain terminal of the NMOS transistor 614. Similarly, the gate terminals of the PMOS transistor 613 and the NMOS transistor 614 are The drain terminal of the PMOS transistor 611 and the drain terminal of the NMOS transistor 612 are connected to the connection point.

  Further, the connection point between the drain terminal of the PMOS transistor 611 and the drain terminal of the NMOS transistor 612 is connected to the point P1, and similarly, the connection point between the drain terminal of the PMOS transistor 613 and the drain terminal of the NMOS transistor 614 is at the point P2. It is connected.

  The capacitor 618 has one end connected to the point P 1 and the other end connected to the switch 624. Similarly, the capacitor 619 has one end connected to the point P1 and the other end connected to the switch 625, and the capacitor 620 has one end connected to the point P1 and the other end connected to the switch 626.

  The capacitor 621 has one end connected to the point P2 and the other end connected to the switch 627. Similarly, the capacitor 622 has one end connected to the point P2 and the other end connected to the switch 628, and the capacitor 623 has one end connected to the point P2 and the other end connected to the switch 629.

  Further, each of the switches 624 to 626 and 627 to 629 performs an opening / closing operation under the control of the VCO automatic tuning circuit 607, and adopts a state where the capacitors 618 to 620 and 621 to 623 are grounded in an arbitrary combination and a state where the capacitors are not grounded.

  The variable frequency dividing circuit 605 serves to feed back the signal SIG obtained by dividing the output signal fvco of the VCO 604 by N to the phase frequency comparison circuit 601. The frequency dividing number N of the variable frequency dividing circuit is given from the frequency dividing number control circuit 606 based on data inputted from the outside.

  Here, FIG. 2 is a diagram showing the relationship between the control potential (control voltage) Vcont (horizontal axis) of the VCO 604 and the oscillation frequency fvco (vertical axis) of the VCO 604 in FIG. 1 (a diagram showing an fvco-Vcont characteristic curve). is there.

  As shown in FIG. 2, the fvco-Vcont characteristic curve is obtained when the switches 624 to 626 and 627 to 629 are controlled to open and close by the nbit capacity switching signal VCOSET 636 (FIG. 1) for switching the capacity 618 to 620 and 621 to 623. As a result, the characteristics of the oscillation frequency of the VCO 604 are discretely moved up and down in inverse proportion to the total capacity of the capacitors 618 to 620 and the capacitors 621 to 623 grounded to the GND. That is, by selecting a combination of the switches 624 to 626 and 627 to 629 to be closed, the capacitance value used for generating the resonance frequency with the inductor 615 is adjusted.

  If the value of VCOSET is a certain value and the fvco-Vcont characteristic indicated by the curve 701 is obtained, the sum of the capacitance increases when the value of the signal VCOSET 636 is increased by 1, and the oscillation frequency characteristic is changed from the characteristic indicated by the curve 701 to the curve 702. The characteristics are reduced.

  Further, when the value of the signal VCOSET 636 is decreased by 1, the total capacitance is reduced, and the oscillation frequency characteristic is increased from the characteristic indicated by the curve 701 to the characteristic indicated by the curve 703.

  The operation of the VCO automatic tuning circuit 607 will be described below with reference to FIGS.

  The VCO automatic tuning circuit 607 starts the tuning operation using the Enable signal generated when the frequency setting data is updated as a trigger signal, and allows the VCO 604 to oscillate at the desired frequency fvco_lock to be locked. Open / close control of switches 624 to 626 and 627 to 629 for switching between 620 and 621 to 623 is performed.

  When the Enable signal is input, the VCO automatic tuning circuit 607 first performs control to invert the states of the two switches of the reference voltage generation circuit 608, that is, control to open the switch 633 while closing the switch 632.

  Then, the capacitors 6341 and 6342 of the LPF circuit 603 are charged with the potential Vref, and the potential Vref is supplied to the frequency control terminal 610 of the VCO 604. Therefore, the VCO 604 oscillates at a frequency corresponding to the potential Vref.

  In addition, when the Enable signal is input, the VCO automatic tuning circuit 607 performs control to switch the frequency dividing number of the variable frequency dividing circuit 605 from N to S, and the output signal SIG (fvco / f) of the variable frequency dividing circuit 604. S) is counted by the reference gate time generated from the reference frequency REF, and it is determined whether the output signal fvco of the VCO 604 is higher or lower than the frequency fvco_lock to be locked, and the capacity switching signal of the VCO 604 is used by using this determination result. The operation of adjusting the value of VCOSET 636 is repeated.

  At this time, if the frequency division number S is set to a value smaller than N, the number of SIG signals that can be counted during the reference gate time period increases, and the oscillation frequency of the VCO 604 can be determined with higher accuracy. If the determination accuracy is the same, the reference gate time can be shortened and the time required for automatic frequency tuning can be shortened.

  By repeating the adjustment of the signal VCOSET 636 as described above, the point 704 (FIG. 2) where the output signal fvco is closest to fvco_lock is finally searched, and the value of the signal VCOSET 636 at this time becomes “D”.

  Thereafter, the states of the switches 632 and 633 of the reference voltage generation circuit 608 are inverted to be in a steady state (the switch 633 is closed and the switch 632 is returned to the open state), while the frequency dividing number of the variable frequency dividing circuit 605 is set. Return from S division to N division.

  As a result, the PLL frequency synthesizer circuit performs an operation of locking to a frequency N times the reference frequency (frequency pull-in operation) in order to return to a normal operation state, and after a certain time, the frequency converges (locks) to a point 705 shown in FIG. )

  According to the first embodiment as described above, the reference voltage generation circuit 608 that applies the reference potential to the variable capacitance elements 616 and 617 of the VCO 604 during the tuning operation by the VCO automatic tuning circuit 607 is provided. Thus, the oscillation frequency can be brought closer to the desired lock frequency more reliably than in the prior art.

  Further, the VCO automatic tuning circuit 607 can be configured to be suitable for integration on a semiconductor.

[Second Embodiment]
Next, before describing the PLL frequency synthesizer circuit (FIG. 4) according to the second embodiment as an improved version of the PLL frequency synthesizer circuit according to the first embodiment, first, the first embodiment will be described. Explain the problem.

  The CV characteristic of the NMOS capacitor (N-Well capacitor) shown in FIG. 6 is as shown in FIG. 7, and changes depending on the voltage Vtune applied between the terminal X and the terminal Y. As Vtune, Voltage application up to the absolute value of the difference from the power supply voltage VDD is possible (FIG. 7, applied voltage range 401). In the case of a normal CMOS process, the range (change region) 402 in which the capacitance value changes in proportion to Vtune is as narrow as about 1 V, and the linear region 403 in which the capacitance changes linearly in proportion to Vtune is In many cases, it is narrower and only about 0.5V is obtained. That is, the variable capacitance elements 616 and 617 are elements in which the linear region 403 is narrower than the applied voltage range 401.

  In addition, the CV characteristic of the NMOS capacitor shown in FIG. 7 is affected by element variations during semiconductor manufacturing (hereinafter simply referred to as manufacturing variations) and temperature during operation, and a linear region of CV characteristics is obtained. The range of the Vtune to be moved moves to the left and right, and the slope of the characteristic in the linear region also changes. In the VCO 604 of FIG. 1 that uses this NMOS capacitor for frequency control, one of the voltages across the NMOS capacitor Vtune1 is determined by the potential difference between the potential of the frequency control terminal 610 and the point P1 (FIG. 1), and the other The voltage Vtune2 is determined by the potential difference between the potential of the control terminal 610 and the point P2 (FIG. 1).

  Here, the bias potential of P1 varies depending on the balance of threshold values (hereinafter referred to as Vt) of the PMOS transistor 611 and the NMOS transistor 612, the power supply voltage VDD, and the temperature Tj. Similarly, the bias potential of P2 is the same as that of the PMOS transistor 613. It varies depending on the balance of Vt of the NMOS transistor 614, the power supply potential VDD, and the temperature Tj.

  Therefore, in the Vcont-fvco characteristic shown in FIG. 2, the frequency adjustable range 706 is narrow, and further, the frequency adjustable range 706 varies in manufacturing, moves to the left and right depending on the power supply potential VDD and the temperature Tj, and the frequency can be adjusted. Even the slope of the range 706 changes. For this reason, even if there are manufacturing variations and fluctuations in conditions such as the power supply potential VDD and temperature Tj, the reference voltage Vref applied when automatically tuning the frequency of the VCO 604 in FIG. It is very difficult to realize a circuit that always exists.

  The above problems will be explained in more detail below.

  FIG. 3 shows fvco-Vcont characteristics in the case where the frequency adjustable range 801 of the VCO 604 moves to the left due to the influence of manufacturing variations, temperature Tj, and power supply potential VDD fluctuation in the PLL frequency synthesizer circuit shown in FIG. FIG.

  In FIG. 3, since the frequency adjustable range 801 has moved to the left, the voltage Vref applied to the control terminal 610 by the reference voltage generation circuit 608 during VCO automatic frequency tuning is outside the range of the frequency adjustable range 801. .

  In this case, the point 802 is searched by automatic frequency tuning, “E” is set to the value of the capacity switching signal VCOSET 636 of the VCO 604, and then the PLL frequency synthesizer circuit shifts to the lock operation.

  However, in this state, no matter what potential is applied to Vcont, the VCO oscillation frequency fvco can only change on the characteristic curve where the point 802 exists, so that the PLL frequency synthesizer circuit can converge the frequency to the target frequency fvco_lock. Can not.

  In order to ensure that the frequency locked by the PLL frequency synthesizer can be reliably searched by automatic frequency tuning, the value of the voltage Vref should have a characteristic that changes following the change of the frequency adjustable range 801. However, the characteristics of the variable capacitance elements (NMOS capacitors) 616 and 617 change due to manufacturing variations and the temperature Tj, and the biases of P1 and P2 of the CMOS VCO 604 change due to manufacturing variations, the power supply voltage VDD, and the temperature Tj. It is very difficult to realize a circuit in which the voltage Vref is interlocked with the above.

  Therefore, when all the circuits of the PLL frequency synthesizer shown in FIG. 1 are integrated on a semiconductor integrated circuit, the frequency variation of the VCO 604 is suppressed by suppressing variations in characteristics of CMOS transistors and variable capacitance elements in the semiconductor manufacturing stage. It is necessary to perform control such that the voltage Vref exists within the variable range of the variable region 801, or to perform trimming for adjusting the element value in the inspection process after manufacturing, resulting in a decrease in manufacturing yield. Alternatively, there arises a problem that more time is required for the inspection process after the manufacture.

  Next, a second embodiment in which the problems of the first embodiment are improved will be described.

  A PLL frequency synthesizer circuit according to the second embodiment shown in FIG. 4 includes a phase frequency comparison circuit 101, an LPF circuit 103, a VCO 104, a variable frequency dividing circuit 105, a frequency dividing number control circuit 106, a VCO automatic tuning circuit 107, and a reference voltage. It is composed of a negative feedback feedback loop composed of the generation circuit 108 and is integrated on a semiconductor integrated circuit (not shown).

  Among them, the circuits other than the VCO automatic tuning circuit 107, the reference voltage generation circuit 108, and the VCO 104 are configured in the same manner as in the PLL frequency synthesizer circuit (FIG. 1) according to the first embodiment. The detailed explanation is omitted.

  That is, the phase frequency comparison circuit 101 is the same as the phase frequency comparison circuit 601 in FIG. 1, the variable frequency dividing circuit 105 is the same as the variable frequency dividing circuit 605 in FIG. 1, and the frequency dividing number control circuit 106 is the same as that in FIG. This is the same as the frequency division number control circuit 606.

  The LPF circuit 103 includes capacitors 1351 and 1352 and a resistor 1353. These capacitors 1351 and 1352 and the resistor 1353 are the same as the capacitors 6341 and 6342 and the resistor 635 in the LPF circuit 603, respectively.

  Next, the VCO automatic tuning circuit 107, the reference voltage generation circuit 108, and the VCO 104 will be described in detail.

  First, as shown in FIG. 4, the reference voltage generation circuit 108 includes switches 130, 133, and 134 and two voltage sources (reference voltage sources) of a low potential Vref_L 131 and a high potential Vref_H 132 having different potentials. Configured.

  Of these switches, the switch 130 converts the output of the phase frequency comparison circuit 101 and the LPF circuit 103 (and the VCO 104 ahead of them) into a mutually connected state and a disconnected state under the control of the VCO automatic tuning circuit 107. Is done.

  Further, the switch 133 is converted into a state in which the low potential Vref_L 131 and the LPF circuit 103 (and the VCO 104 ahead) are connected to each other and a state in which they are disconnected from each other under the control of the VCO automatic tuning circuit 607. The switch 134 is converted into a state in which the high potential Vref_H 132 and the LPF circuit 103 (and the VCO 104 ahead) are connected to each other and a state in which they are disconnected from each other.

  In a normal state, the switch 130 is closed and the switch 133 and the switch 134 are open, the output voltage or output current of the phase frequency comparison circuit 101 is supplied to the LPF circuit 103, and the phase 110 is connected to the terminal 110 of the VCO 104. A potential from which an AC component has been removed by the LPF circuit 103 is supplied from the output of the frequency comparison circuit 101.

  The potential of the Vref_L 131 is sufficiently saturated when the Vref_L 131 is applied to the control terminal 110 of the VCO 104, and the values (capacitance values) of the variable capacitors 116 and 117 that are MOS capacitors are sufficiently saturated. Is set to a potential that maximizes.

  On the other hand, the potential of Vref_H132 is such that when Vref_H is applied to the control terminal 110 of the VCO 104, the values of the variable capacitors 116 and 117, which are MOS capacitors, are sufficiently saturated and their capacitance values are minimized. Is set.

  Here, each of the two kinds of potentials, that is, the potential of Vref_L131 and the potential of Vref_H132, is a value that saturates the CV characteristics even if the CV characteristics of the variable capacitors 116 and 117 vary due to manufacturing variations. More preferably, it is set.

  Next, the basic configuration of the VCO 104 is the same as that of the VCO 604 in the first embodiment.

  That is, as shown in FIG. 4, the VCO 104 includes variable capacitance elements 116 and 117, an inductor 115, PMOS transistors 111 and 113, NMOS transistors 112 and 114, capacitors 118, 119, 120, 121, 122, 123, a switch 124, 125, 126, 127, 128, and 129. These variable capacitance elements 116 and 117, inductor 115, PMOS transistors 111 and 113, NMOS transistors 112 and 114, capacitors 118 to 123, and switches 124 to 129 are variable in the VCO 604, respectively. The capacitor elements 616 and 617, the inductor 615, the PMOS transistors 611 and 613, the NMOS transistors 612 and 614, the capacitors 618 to 623, and the switches 624 to 629 are the same.

  Similarly to the VCO 604, the VCO 104 is an LC oscillation circuit that uses an inverter circuit that is a combination of a PMOS transistor and an NMOS transistor as a negative resistance circuit. The inverter circuit corresponds to the PMOS transistor 111 and the NMOS transistor. 112 is a combination of a PMOS transistor 113 and an NMOS transistor 114. In the VCO 104, the LC resonance circuit for varying the oscillation frequency includes n inductors 115, variable capacitance elements 116 and 117, capacitors 118 to 123 weighted capacitance values, and switches 124 to 129. (For example, six) capacity arrays.

  However, in the VCO 104 in this embodiment, the frequency change amount fvco_step of the switching step of the oscillation frequency is sufficiently smaller than the product of Δfvco and Vcont_w shown in FIG. 8 so that the automatic frequency tuning mechanism of the VCO oscillation frequency does not malfunction. In an ideal state, the weights of the capacitance values of the capacitors 118 to 120 and 121 to 123 must be adjusted so that (Δfvco × Vcont_w) / 4 ≧ fvco_step (details) Will be described later).

  Next, the VCO automatic frequency tuning operation of the PLL frequency synthesizer shown in FIG. 4 will be described with reference to the fvco-Vcont characteristic shown in FIG.

  The VCO automatic tuning circuit 107 starts the operation using the Enable signal generated when the frequency setting data is updated as a trigger signal, and performs automatic frequency tuning of the VCO twice (the first tuning operation and the first tuning operation). 2) with 2 tuning operations.

  First, in the first automatic frequency tuning (first tuning operation, first tuning step), when the Enable signal is input, the switch 130 of the reference voltage generation circuit 108 is opened while the switch 133 is closed, and the variable frequency division is performed. Control is performed to switch the frequency dividing number of the circuit 105 from normal N to S.

  Then, the LPF circuit 103 is charged with the low potential Vref_L131 by closing the switch 133, the low potential Vref_L131 is supplied to the frequency control terminal 110 of the VCO 104, and the VCO 104 oscillates at a frequency corresponding to the low potential Vref_L131. To do.

  In this state, the VCO automatic tuning circuit 107 counts the output signal SIG (fvco / S) of the variable frequency dividing circuit 105 with the reference gate time generated from the reference frequency REF, and the frequency fvco_lock (lock frequency) that fvco wants to lock. The operation of adjusting the value of the capacity switching signal VCOSET 136 of the VCO 104 is repeated using this determination result.

  Finally, a point 502 (FIG. 8: first set value) where fvco is closest to fvco_lock is searched, and the value “A” of VCOSET 136 at this time is stored in the VCO automatic tuning circuit 107, and the first automatic End frequency tuning.

  Next, in the second automatic frequency tuning (second tuning operation, second tuning step), the VCO automatic tuning circuit 107 performs control to close the switch 134 while opening the switch 133 of the reference voltage generation circuit 108. .

  In this case, the LPF circuit 103 is charged with the high potential Vref_H132, the high potential Vref_H132 is supplied to the frequency control terminal 110 of the VCO 104, and the VCO 104 oscillates at a frequency corresponding to the high potential Vref_H132.

  In this state, the VCO automatic tuning circuit 107 counts the output signal SIG (fvco / S) of the variable frequency dividing circuit 104 with the reference gate time generated from the reference frequency REF, and with respect to the frequency fvco_lock to lock fvco. It is determined whether it is high or low, and the operation of adjusting the value of the capacity switching signal VCOSET 136 of the VCO 104 is repeated using this determination result.

  Finally, a point 503 (figure 8: second set value) where fvco is closest to fvco_lock is searched, and the value “B” of VCOSET 136 at this time is stored in the VCO automatic tuning circuit 107, and the second automatic End frequency tuning.

  When starting the second tuning step, it is more preferable to start the search using the value “A” of the VCOSET obtained in the first tuning step as an initial value because the time of the second searching step can be shortened. .

  Thereafter, the VCO automatic tuning circuit 107 determines the value of the capacitance switching signal VCOSET 136 of the VCO 104 as an intermediate value “A” obtained by the first automatic frequency tuning and “B” obtained by the second automatic frequency tuning “ C ″ is fixed (third tuning operation, third tuning step), and the frequency dividing number of the variable frequency dividing circuit 105 is returned from S frequency division to N frequency division.

  Further, the VCO automatic tuning circuit 107 opens the switch 134 of the reference voltage generation circuit 208 and closes the switch 130 to return the PLL loop to a steady operation state.

  As a result, the PLL frequency synthesizer circuit performs an operation of locking to a frequency N times the reference frequency, and after a certain time, the frequency converges (locks) at a point 504 shown in FIG.

  Here, in order to ensure that the value C between the values A and B of the VCOSET 136 obtained by automatic frequency tuning always exists, it is necessary to satisfy the relationship of the following expression (3) in the ideal state. In the equation (3), the modulation sensitivity of the VCO 104 is Δfvco, the width of the Vcont region where fvco changes in proportion to Vcont is Vcont_w, and the frequency change amount when the value of VCOSET 136 is changed by 1 is fvco_step.

(Δfvco × Vcont_w) / 4 ≧ fvco_step (3)
Here, in the automatic frequency tuning, the output SIG of the variable frequency dividing circuit 105 is counted by the gate time created based on the reference signal to determine whether the VCO oscillation frequency is high or low. For this reason, the value of the searched VCOSET is expected to be miscounted by about ± 1 due to the timing relationship between the SIG signal and the gate time and disturbances during automatic frequency tuning. Conditions are required. However, in the actual design, a design with a further margin is required.

  In the above description, the example in which the first automatic frequency tuning is performed using the potential of the low potential Vref_L131 and the second automatic frequency tuning is performed using the potential of the high potential Vref_H132 has been described. The same effect can be obtained by performing automatic frequency tuning using the high potential Vref_H132 and performing the second automatic frequency tuning using the low potential Vref_L131.

  According to the second embodiment as described above, the following effects can be achieved.

  In the case of the PLL frequency synthesizer circuit according to the first embodiment shown in FIG. 1, in order for the PLL frequency synthesizer circuit to lock, the potential Vref applied to the control terminal 610 of the VCO 604 at the time of automatic frequency tuning is set to the frequency of the VCO 604. The VCO 604 cannot be tuned to a frequency at which the PLL frequency synthesizer circuit is to be locked unless it is always kept in a region that varies in proportion to the applied voltage.

  On the other hand, in the case of the second embodiment, the reference voltage Vref applied during automatic frequency tuning of the oscillation frequency of the VCO 204 is set to a low potential at which the CV characteristics of the variable capacitance elements (NMOS capacitors) 116 and 117 are sufficiently saturated. Automatic frequency tuning is performed under two conditions of Vref_L131 and high potential Vref_H132. Further, Vref_L131 and Vref_H132 are low potentials at which the CV characteristics are sufficiently saturated even if the fvco-Vcont characteristics shown in FIG. 8 fluctuate up and down and left and right due to semiconductor characteristic variations, temperature and power supply voltage fluctuations. Two conditions of Vref_L and high potential Vref_H are selected. Further, Δfvco, Vcont_w, and fvco_step are set to values that satisfy the relationship of Expression (3).

  Therefore, even if the characteristics of the semiconductor, characteristics of the MOS capacitor or the CMOS transistor vary due to variations in temperature, power supply voltage, etc., and the fvco-Vcont characteristics shown in FIG. The setting value “A” of the capacity switching mechanism searched by performing the automatic frequency tuning with the Vref_L 131 and the setting value VCOSET of the mechanism, and the setting value of the capacity switching mechanism obtained by performing the automatic frequency tuning with the Vref_H 132. If set to a value “C” intermediate to “B”, the VCO can always oscillate at a frequency at which the PLL frequency synthesizer is to be locked. This is apparent from the fvco-Vcont characteristic shown in FIG.

  Therefore, after setting the capacitance switching setting value VCOSET to a value “C” which is an intermediate value between “A” and “B”, the PLL frequency synthesizer circuit is shifted to the lock operation to ensure that the PLL frequency synthesizer circuit is Can be locked to frequency.

  In short, according to the second embodiment, even if the threshold value (Vt) of the CMOS transistor and the CV characteristic of the variable capacitance element are shifted due to manufacturing variations, temperature, power supply voltage, etc., and the power supply voltage changes, The oscillation frequency of the VCO 104 can be adjusted to a frequency at which the PLL frequency synthesizer circuit is desired to be locked.

  In addition, since it is not necessary to suppress the characteristic variation of the CMOS transistor excessively in the semiconductor manufacturing stage, a high yield can be expected even when all the circuits of the PLL frequency synthesizer are integrated by a general CMOS semiconductor process, and it is inexpensive. Mass production is possible.

[Third Embodiment]
Next, a PLL frequency synthesizer circuit according to a third embodiment will be described with reference to FIG.

  A PLL frequency synthesizer circuit according to the third embodiment shown in FIG. 5 includes a phase frequency comparison circuit 201, an LPF circuit 203, a VCO 204, a variable frequency dividing circuit 205, a frequency dividing number control circuit 206, a VCO automatic tuning circuit 207, and a reference voltage. It is composed of a negative feedback feedback loop composed of the generation circuit 208 and is integrated on a semiconductor integrated circuit (not shown).

  Among these, circuits other than the reference voltage generation circuit 208 are configured in the same manner as in the PLL frequency synthesizer circuit (FIG. 4) according to the second embodiment, and thus detailed description thereof is omitted.

  That is, the phase frequency comparison circuit 201 is the same as the phase frequency comparison circuit 101 in FIG. 4, the LPF circuit 203 is the same as the LPF circuit 103 in FIG. 4, the VCO 204 is the same as the VCO 104, and the variable frequency dividing circuit 205 is 4 is the same as the variable frequency dividing circuit 105 in FIG. 4, the frequency dividing number control circuit 206 is the same as the frequency dividing number control circuit 106 in FIG. 4, and the VCO automatic tuning circuit 207 is the same as the VCO automatic tuning circuit 107 in FIG. It is.

  The LPF circuit 203 includes capacitors 233 and 234 and a resistor 235. These capacitors 233 and 234 and the resistor 235 are similar to the capacitors 1351 and 1352 and the resistor 1353 in the LPF circuit 103, respectively.

  The VCO 204 includes variable capacitance elements 216 and 217, an inductor 215, PMOS transistors 211 and 213, NMOS transistors 212 and 214, capacitors 218, 219, 220, 221, 222, and 223, switches 224, 225, 226, 227, and 228. 229, the variable capacitance elements 216 and 217, the inductor 215, the PMOS transistors 211 and 213, the NMOS transistors 212 and 214, the capacitances 218 to 223, and the switches 224 to 229 are the variable capacitance element 116 in the VCO 104, respectively. 117, inductor 115, PMOS transistors 111 and 113, NMOS transistors 112 and 114, capacitors 118 to 123, and switches 124 to 129.

  That is, the VCO 204 is an LC oscillation circuit that uses an inverter circuit formed by a combination of a PMOS transistor and an NMOS transistor in a negative resistance circuit, and the inverter circuit corresponds to a combination of the PMOS transistor 211 and the NMOS transistor 212, This is a combination of a PMOS transistor 213 and an NMOS transistor 214. In the VCO 204, the LC resonance circuit for varying the oscillation frequency includes n inductors 215, variable capacitance elements 216 and 217, capacitors 218 to 223 whose capacitance values are weighted, and switches 224 to 229. (For example, six) capacity arrays.

  In the second embodiment (FIG. 4), the reference voltage generation circuit 108 is configured by using the low potential Vref_L131 and the high potential Vref_H132 as two reference voltage sources. However, the low potential Vref_L and Vref_H are variable capacitance elements. (In the case of FIG. 5, it is sufficient that the capacitance change characteristics of the variable capacitance elements 216, 217) be sufficiently saturated. For example, there is no problem even if Vref_L is set to the GND potential and Vref_H is set to the power supply voltage VDD.

  Therefore, in the present embodiment, as shown in FIG. 5, a reference voltage generation circuit 208 is provided instead of the reference voltage generation circuit 108 in the second embodiment.

  That is, the reference voltage generation circuit 208 includes a switch 230, a switch 231, and a switch 232. Of these, the switch 230 is controlled by the VCO automatic tuning circuit 207, and the phase frequency comparison circuit 201. And the LPF circuit 203 (and the VCO 204 ahead) are connected to each other and disconnected from each other. Further, the switch 231 is converted into a state in which the GND potential as the low potential Vref_L and the LPF circuit 203 (and the VCO 204 ahead) are connected to each other and a state in which the switch 232 is disconnected from each other. The VDD potential (power supply potential) as the potential Vref_H and the LPF circuit 203 (and the VCO 204 ahead) are connected to each other and separated from each other.

  In the case of this embodiment, the procedure of automatic frequency tuning is that the low potential Vref_L in the second embodiment is simply replaced with the GND potential, and the high potential Vref_H is replaced with the VDD potential. Since this is the same as the case of the embodiment, the description is omitted.

  According to the third embodiment as described above, the reference voltage generation circuit 208 can be realized with a simple configuration including only the switches 230, 231, and 232, and the design becomes easy.

  Further, since the reference voltage generation circuit 108 for generating the potential in an analog or digital manner is not necessary, the area occupied by the reference voltage generation circuit 208 on the semiconductor integrated circuit is reduced, and the manufacturing can be performed at a lower cost.

  Furthermore, since the potential supplied from the reference voltage generation circuit 208 only needs to be a binary value of the GND potential and the VDD potential, the power supply voltage (VDD) is a wide PLL frequency synthesizer circuit with a specification of 2.5V to 5V. Even so, the circuit of the present invention has the advantage that it can operate without any adjustment.

[Fourth Embodiment]
In the second and third embodiments described above, the automatic frequency tuning of the VCO is performed twice, so that even if there is a variation in semiconductor characteristics, or there is a fluctuation in characteristics of the NMOS capacitor or CMOS transistor due to temperature or power supply voltage, the PLL Although an example in which the frequency synthesizer can always lock to a desired frequency has been described, in this case, since it is necessary to perform automatic frequency tuning of the VCO twice, the lockup time combining the VCO tuning period and the PLL frequency pull-in period Will cause the disadvantage of becoming longer.

  For example, when considering use in a PLL frequency synthesizer used in the RF section of a TDMA (Time Division Multiple Access) mobile phone, search for the field strength between base stations in and around transmission and reception slots. In such a case, since a high-speed frequency switching operation may be required, the second and third embodiments may not be applicable because the lock-up time of the PLL becomes long.

  Therefore, in the fourth embodiment, a mechanism that can eliminate this drawback will be described.

  FIG. 9 is a circuit diagram showing a PLL frequency synthesizer circuit according to the fourth embodiment.

  As shown in FIG. 9, the PLL frequency synthesizer circuit according to the fourth embodiment has a configuration in which an A / D / D / A conversion block 1440 is added to the PLL frequency synthesizer circuit according to the second embodiment.

  Note that the PLL frequency synthesizer circuit according to the fourth embodiment is the same as that of the first embodiment except that the A / D / D / A conversion block 1440 is added and the operation of the VCO automatic tuning circuit 207 is slightly different. The configuration is the same as in the PLL frequency synthesizer circuit (FIG. 4) according to the second embodiment.

  That is, the reference voltage generation circuit 1409 is the same as the reference voltage generation circuit 108 in FIG. 4, the phase frequency comparison circuit 1401 is the same as the phase frequency comparison circuit 101 in FIG. 4, and the LPF circuit 1403 is the LPF circuit 103 in FIG. The VCO 1404 is the same as the VCO 104, the variable frequency dividing circuit 1405 is the same as the variable frequency dividing circuit 105 in FIG. 4, and the frequency dividing number control circuit 1406 is the same as the frequency dividing number control circuit 106 in FIG. It is.

  The reference voltage generation circuit 1409 includes switches 1430, 1433, and 1434, and two voltage sources (reference voltage sources) of low potential Vref_L1431 and high potential Vref_H1432 having different potentials, and these switches 1430, 1433, 1433, 1434, the low potential Vref_L1431, and the high potential Vref_H1432 are the same as the switches 130, 133, and 134, the low potential Vref_L131, and the high potential Vref_H132 of the reference voltage generation circuit 108, respectively.

  The LPF circuit 1403 includes capacitors 1435 and 1436 and a resistor 1437. These capacitors 1435 and 1436 and the resistor 1437 are similar to the capacitors 1351 and 1352 and the resistor 1353 in the LPF circuit 103, respectively.

  The VCO 1404 includes variable capacitance elements 1416 and 1417, an inductor 1415, PMOS transistors 1411 and 1413, NMOS transistors 1412 and 1414, capacitors 1418 and 1419, 1420, 1421, 1422, and 1423, switches 1424, 1425, 1426, 1427, and 1428. , 1429, the variable capacitance elements 1416 and 1417, the inductor 1415, the PMOS transistors 1411 and 1413, the NMOS transistors 1412 and 1414, the capacitances 1418 to 1423, and the switches 1424 to 1429 are the variable capacitance elements 116 in the VCO 104, respectively. 117, inductor 115, PMOS transistors 111 and 113, NMOS transistors 112 and 114, capacitors 118 to 123, switch 124-129 is the same as that.

  That is, the VCO 1404 is an LC oscillation circuit that uses an inverter circuit formed by a combination of a PMOS transistor and an NMOS transistor in a negative resistance circuit, and the inverter circuit corresponds to a combination of a PMOS transistor 1411 and an NMOS transistor 1412. This is a combination of a PMOS transistor 1413 and an NMOS transistor 1414. In the VCO 1404, the LC resonance circuit for varying the oscillation frequency includes n inductors 1415, variable capacitance elements 1416 and 1417, capacitances 1418 to 1423 weighted by capacitance values, and switches 1424 to 1429. (For example, six) capacity arrays.

  Next, the A / D / D / A conversion block 1440 will be described in detail.

  As shown in FIG. 9, the A / D / D / A conversion block 1440 includes an A / D conversion circuit 1441, a D / A conversion circuit 1442, and an A / D / D / A conversion control circuit 1443. It is configured.

  As a specific configuration of the A / D / D / A conversion block 1440, various types of A / D conversion circuits and D / A conversion circuits may be applied. In the present embodiment, a circuit is used as an example. A specific example is shown in FIG.

  That is, the A / D / D / A conversion block 1440 includes, for example, a power switch 1506 for starting / stopping the A / D / D / A conversion block 1440, a resistor group 1501, and a switch group as shown in FIG. 1502, a voltage follower 1504, a comparator 1503, an output switch 1505, and an A / D / D / A conversion control circuit 1443.

  Among these, the resistor group 1501 includes a plurality (q) of resistors 1511, 1512, 1513, 1514,..., 1515 connected in series with each other between the power supply potential VDD and the ground potential GND.

  The power switch 1506 is inserted between the resistor 1515 and the power supply potential VDD, for example.

  The switch group 1502 includes a plurality (q + 1) of switches 1516, 1517, 1518, 1519,..., 1520. One end of each of the switches 1516 to 1520 is between the ground potential GND and each resistance of the resistance group 1501. The power supply potential VDD and the power switch 1506 are connected to the connection point, respectively, and the other ends are connected in common.

  The other end side of the switches 1516 to 1520 connected in common is connected to the plus terminal of the comparator 1503 and the plus terminal of the voltage follower 1504.

  The negative terminal of the voltage follower 1504 is connected to the output terminal of the voltage follower 1504. The voltage follower 1504 outputs the potential input to the plus terminal from the output terminal.

  The minus terminal of the comparator 1503 is connected to the connection point between the output side of the LPF 1403 and the frequency control terminal 1410 of the VCO 1404.

  The A / D / D / A conversion control circuit 1443 controls the power switch 1506 and the output switch 1505 individually under the control of the VCO automatic tuning circuit 1407, and each switch group 1502 according to the comparison result of the comparator 1503. And a control to close any one of the switches 1516 to 1520 one by one.

  Under the control of the A / D / D / A conversion control circuit 1443, by closing any one of the switches 1516 to 1520 in the switch group 1502 while the power switch 1506 is closed, the comparator 1503 is positively connected. The terminal is supplied with any one of a plurality of types of potentials set stepwise within the range from the ground potential to the power supply potential.

  On the other hand, the same potential as that applied to the frequency control terminal 1410 of the VCO 1404, that is, the control potential of the VCO 1404 is supplied to the minus terminal of the comparator 1503.

  When the potential supplied to the plus terminal of the comparator 1503 is gradually increased by the A / D / D / A conversion control circuit 1443 performing opening / closing control of the switches 1516 to 1520 of the switch group 1502, the comparator 1503 is eventually added. The potential supplied to the plus terminal exceeds the potential supplied to the minus terminal.

  The comparator 1503 inverts the output from the Low level to the High level at the timing when the potential supplied to the plus terminal exceeds the potential supplied to the minus terminal in this manner, and the A / D / D / A conversion control circuit 1443 In contrast, a potential increase stop signal is output.

  The A / D / D / A conversion control circuit 1443 that has received the potential increase stop signal ends the open / close control of the switches 1516 to 1520.

  In this state, the open / closed state of each of the switches 1516 to 1520 is a state in which substantially the same potential as the control potential of the VCO 1404 can be supplied to the plus terminal of the voltage follower 1504.

  Therefore, when the A / D / D / A conversion control circuit 1443 performs control to close the output switch 1505 while maintaining the open / closed state of the switches 1516 to 1520, the potential substantially the same as the control potential of the VCO 1404 is set to A The signal can be supplied from the / D · D / A conversion block 1440 to the frequency control terminal 1410 of the VCO 1404.

  In such an A / D / D / A conversion block 1440, the D / A conversion circuit 1442 includes a resistor group 1501 and a switch group 1502, and the A / D conversion circuit 1441 includes a comparator 1503, a resistor group 1501, and a switch group 1502. Become.

  That is, in the A / D / D / A conversion block 1440, the D / A conversion operation generates the potential of the resistance divided by each resistance of the resistor group 1501 by performing the open / close control of each switch of the switch group 1502. The A / D conversion operation is performed by sequentially comparing the control potential of the VCO 1404 and the output of the D / A conversion circuit 1442 by the comparator 1503.

  Next, the operation of the PLL frequency synthesizer circuit of FIG. 9 will be described with reference to FIG.

  In the automatic frequency tuning of the VCO that is performed before the first frequency pull-in operation (operation that locks to the fvco_lock1) after the power is turned on for the PLL frequency synthesizer circuit, the control voltage Vcont of the VCO is set to Vref_L as in the second embodiment. Tuning operations are performed as two conditions of Vref_H (two tuning operations of a first tuning operation and a second tuning operation are performed).

  First, in automatic frequency tuning (first tuning operation) in which the VCO control voltage Vcont is set to Vref_L, the VCO automatic tuning circuit 1407 starts control using the Enable signal generated when the frequency setting data is updated as a trigger signal. To do.

  That is, the VCO automatic tuning circuit 1407 controls to open the switch 1430 of the reference voltage generation circuit 1409 while closing the switch 1433, and the A / D / D / A conversion control circuit 1443 of the A / D / D / A conversion circuit 1440. The power switch 1506 and the voltage follower output switch 1505 are opened to stop the A / D / D / A conversion circuit 1440, and the frequency division number of the variable frequency division control circuit 1406 is set to N And control for switching from S to S.

  Then, when the switch 1433 is closed, the LPF circuit 1403 is charged with the potential of Vref_L1431, the potential Vref_L1431 is supplied to the frequency control terminal 1410 of the VCO 1404, and the VCO 1404 oscillates at a frequency corresponding to Vref_L1431.

  In this state, the VCO automatic tuning circuit 1407 counts the output signal SIG (fvco / S) of the variable frequency dividing circuit 1405 with the reference gate time generated from the reference frequency REF, and the frequency fvco_lock1 (lock frequency) that fvco wants to lock. The operation of adjusting the value of the capacity switching signal VCOSET of the VCO 1404 is repeated using this determination result.

  Finally, a point 1602 (FIG. 11: first setting value) where fvco is closest to fvco_lock1 is searched, and the VCOSET value “F” at this time is stored in the VCO automatic tuning circuit 1407.

  Next, in automatic frequency tuning (second tuning operation) in which the VCO control voltage Vcont is set to Vref_H1432, the VCO automatic tuning circuit 1407 performs control to open the switch 1433 of the reference voltage generation circuit and close the switch 1434.

  In this case, the LPF circuit 1403 is charged with the potential of Vref_H1432, the potential Vref_H1432 is supplied to the frequency control terminal 1410 of the VCO 1404, and the VCO 1404 oscillates at a frequency corresponding to Vref_H1432.

  In this state, the VCO automatic tuning circuit 1407 counts the output signal SIG (fvco / S) of the variable frequency dividing circuit 1405 with the reference gate time generated from the reference frequency REF, and with respect to the frequency fvco_lock1 at which fvco is to be locked. It is determined whether it is high or low, and the operation of adjusting the value of the capacity switching signal VCOSET of the VCO 1404 is repeated using this determination result.

  Finally, a point 1603 (figure 11: second set value) where fvco is closest to fvco_lock1 is searched, and the VCOSET value “G” at this time is stored in the VCO automatic tuning circuit 1407 to perform automatic frequency tuning. finish.

  When starting the second tuning, it is more preferable to start the search by using the value “F” of VCOSET obtained in the first tuning as an initial value because the time of the second search process can be shortened. .

  Thereafter, the VCO automatic tuning circuit 1407 sets the value of the capacitance switching signal VCOSET of the VCO 1404 to “F” obtained by automatic frequency tuning when Vcont is the voltage of Vref_L1431, and the automatic frequency when Vcont is the voltage of Vref_H1432. The value is fixed at an intermediate value “H” of “G” obtained by tuning, and the frequency dividing number of the variable frequency dividing circuit 1405 is returned from the S frequency division to the N frequency division.

  Also, the VCO automatic tuning circuit 1407 opens the switch 1434 of the reference voltage generation circuit 1409, closes the switch 1430, and returns the PLL loop to the steady operation state.

  As a result, the PLL frequency synthesizer circuit performs an operation of locking to a frequency N times the reference frequency, and after a certain time, the frequency converges (locks) at a point 1604 shown in FIG.

  After the frequency is locked in the PLL frequency synthesizer circuit, the A / D / D / A conversion control circuit 1443 operates the A / D conversion circuit 1441 at an appropriate timing such that the circuit that supplies the oscillation output of the VCO 1404 is stopped. The A / D conversion circuit 1441 digitally detects the control voltage of the VCO 1404, and the A / D / D / A conversion control circuit 1443 holds this voltage as a digital value.

  In other words, under the control of the A / D / D / A conversion control circuit 1443, any one of the switches 1516 to 1520 in the switch group 1502 that is in the closed state is sequentially turned on while the power switch 1506 is closed. By switching, the potential supplied to the plus terminal of the comparator 1503 is gradually increased, and the switches 1516 to 1520 are opened and closed at a timing when the potential supplied to the plus terminal of the comparator 1503 exceeds the potential supplied to the minus terminal. The A / D / D / A conversion control circuit 1443 stores and holds a digital value of the opening / closing of the switches 1516 to 1520 at this time.

  That is, the value of the potential (substantially the same value) applied to the variable capacitance elements 1416 and 1417 in the steady state adjusted to the lock frequency by the first frequency pull-in operation after power-on to the PLL frequency synthesizer circuit is A It is held by a / D · D / A conversion control circuit (holding unit) 1443.

  In other words, the digital value output from the A / D conversion circuit 1441 in the locked state adjusted to the lock frequency by the first frequency pull-in operation after power-on to the PLL frequency synthesizer circuit is A / D · D / A It is held by a conversion control circuit (holding unit) 1443.

  After the power supply to the PLL frequency synthesizer circuit is turned on, automatic frequency tuning of the VCO 1404 is performed according to the following procedure before the second and subsequent frequency pulls in which the PLL frequency synthesizer is locked to fvco_lock2.

  First, the VCO automatic tuning circuit 1407 starts control using an Enable signal generated when the frequency setting data is updated as a trigger signal.

  In other words, the VCO automatic tuning circuit 1407 opens the switch 1430 of the reference voltage generation circuit 1409 and controls the switches 1433 and 1434 to be open, and the frequency dividing number of the variable frequency dividing circuit 1405 is changed from N in normal times to S. And switching control.

  In this state, the VCO automatic tuning circuit 1407 causes the A / D / D / A conversion control circuit 1443 of the A / D / D / A conversion circuit 1440 to close the power switch 1506, thereby A / D / D / A. By controlling the activation of the conversion circuit 1440 and opening / closing control of the switches 1515 to 1520 of the switch group 1502 based on the digital value held in the A / D / D / A conversion control circuit 1443, the digital Control for generating a voltage Vlock corresponding to the value, and control for supplying the voltage Vlock to the frequency control terminal 1410 of the VCO 1404 via the voltage follower 1504 by closing the output switch 1505 (as a control voltage of the VCO 1404). And do.

  If the value of the voltage Vlock is designed so that the resolution of fvco_step is high, the frequency of the VCO 1404 is in the vicinity of the center of the range Vcont_w1601 that can be adjusted by the VCO control voltage. The VCO automatic frequency of the second and third embodiments It will be obvious from the tuning explanation.

  In this state, the VCO automatic tuning circuit 1407 counts the output signal SIG (fvco / S) of the variable frequency dividing circuit 1405 with the reference gate time generated from the reference frequency REF, and with respect to the frequency fvco_lock2 that fvco wants to lock. It is determined whether it is high or low, and the operation of adjusting the value of the capacity switching signal VCOSET of the VCO 1404 is repeated using this determination result.

  Finally, a point 1605 where fvco is closest to fvco_lock2 is searched for, and the VCOSET value “I” at this time is stored in the VCO automatic tuning circuit 1407.

  Thereafter, the VCO automatic tuning circuit 1407 fixes the value of the capacitance switching signal VCOSET of the VCO 1404 to “I” and returns the frequency dividing number of the variable frequency dividing circuit from S frequency division to N frequency division. The VCO automatic tuning circuit 1407 closes the switch 1430 while controlling the A / D / D / A conversion control circuit 1443 to open the power switch 1506 and the output switch 1505 to return the PLL loop to the steady operation state. .

  Then, the PLL frequency synthesizer circuit performs an operation of locking to a frequency N times the reference frequency, and then the frequency converges (locks) at a point 1606 shown in FIG.

  In the present embodiment, the first VCO automatic frequency tuning (first tuning operation) that is performed before the first frequency pull-in after the power is turned on for the PLL frequency synthesizer circuit is performed at the potential of Vref_L1431. Although an example in which automatic frequency tuning (second tuning operation) is performed using Vref_H1432, the same effect can be obtained by performing the first time using Vref_H1432 and the second time using Vref_L1431.

  Further, when the PLL frequency synthesizer circuit of the present embodiment shifts to a sleep state (power save state), the digital value of the VCO control voltage detected by the A / D conversion circuit 1441 is converted into A / D / D / A conversion control. The circuit 1443 is held and enters a dormant state.

  Thereafter, when the PLL frequency synthesizer circuit returns to the normal operation from the hibernation state, the control voltage of the VCO 1404 is generated by the D / A conversion circuit 1442 using the held digital value, and the second and subsequent times The voltage Vlock digitally held in the A / D / D / A conversion control circuit 1443 is D / A converted by performing the same procedure as the automatic frequency tuning of the VCO before the frequency pull-in By converting the analog voltage into an analog voltage by the circuit 1442 and supplying it as the control voltage of the VCO 1404 to the frequency control terminal 1410 of the VCO 1404, the lock-up time can be shortened.

  In addition, the PLL frequency synthesizer circuit of this embodiment has a case where the operating environment (temperature, power supply voltage, etc.) changes after holding the VCO control voltage in the A / D conversion circuit 1441, or the A / D conversion circuit 1441 When the predetermined time has elapsed from the time when the VCO control voltage is held, the control voltage Vcont of the VCO 1404 is set as two conditions of Vref_L1431 and Vref_H1432, respectively, as in the first automatic frequency tuning of the VCO after power-on. The tuning operation is performed, and the value of the capacitance switching signal VCOSET of the VCO 1404 is fixed to an intermediate value “H” between “F” obtained by using Vcont as the voltage of Vref_L1431 and “G” obtained by using Vcont as Vref_H1432. Lock operation ( Wave number pull-in operation), the VCO control voltage at the time of locking is converted into a digital value by the A / D conversion circuit 1441, and this value is held by the A / D / D / A conversion control circuit 1443 To do.

  That is, the PLL frequency synthesizer circuit of this embodiment includes an operating environment change detecting means (for example, a temperature sensor, a voltage measuring circuit, etc .: not shown) that detects a change in the operating environment of the PLL frequency synthesizer circuit, and an A / D / D. The / A conversion control circuit 1443 includes time measuring means (timer: not shown) for measuring the elapsed time since the digital value corresponding to the VCO control voltage was last held.

  When a predetermined time is measured by the time measuring means or when a change in the operating environment is detected by the operating environment change detecting means, the VCO automatic tuning circuit 1407 performs the first, second and third operations. Tuning operation (the control voltage Vcont of the VCO 1404 is set to two conditions of Vref_L1431 and Vref_H1432, respectively, and further, the value of the capacitance switching signal VCOSET of the VCO 1404 is obtained as “F” obtained by using Vcont as the voltage of Vref_L1431, and Vcont The VCO control voltage when the PLL frequency synthesizer circuit shifts to the normal operation and locks to the A / D converter circuit is performed. 1441 Into a digital value, to implement an operation (holding value update operation) for holding the digital value at A / D · D / A converter control circuit 1443.

  As a result, even when some operating condition changes over time or when the operating environment changes as detected by the operating environment change detecting means, the oscillation frequency of the VCO 1404 is always set to the PLL frequency synthesizer circuit. You can adjust the frequency you want to lock.

  According to the fourth embodiment as described above, since the automatic frequency tuning of the VCO 1404 is required only once in the second and subsequent operations for locking the PLL frequency synthesizer circuit after the power is turned on, the automatic frequency tuning period of the VCO 1404 and the PLL The lock-up time obtained by adding up the frequency pull-in periods is shortened by a period corresponding to one automatic frequency tuning of the VCO, as compared with the second and third embodiments. For this reason, the fourth embodiment is suitable when a high-speed switching operation of the PLL frequency is required. Note that the first lock-up time after power-on requires the same period as in the second and third embodiments, but the disadvantage of the first lock-up time after power-on is long on the radio communication system. Can be avoided.

[Fifth Embodiment]
In the fifth embodiment, an example in which the third embodiment is applied to the fourth embodiment will be described.

  FIG. 12 is a circuit diagram showing a PLL frequency synthesizer circuit according to the fifth embodiment.

  A PLL frequency synthesizer circuit according to the fifth embodiment shown in FIG. 12 includes a phase frequency comparison circuit 1701, an LPF circuit 1703, a VCO 1704, a variable frequency dividing circuit 1705, a frequency dividing number control circuit 1706, a VCO automatic tuning circuit 1707, and a reference voltage. A negative feedback feedback loop including a generation circuit 1708 is formed and integrated on a semiconductor integrated circuit (not shown). In addition, the PLL frequency synthesizer circuit according to the fifth embodiment shown in FIG. 12 includes an A / D / D / A conversion block 1740, similar to the PLL frequency synthesizer circuit according to the fourth embodiment.

  Among these, circuits other than the reference voltage generation circuit 1708 are configured in the same manner as in the PLL frequency synthesizer circuit (FIG. 9) according to the fourth embodiment.

  That is, the phase frequency comparison circuit 1701 is the same as the phase frequency comparison circuit 1401 in FIG. 9, the LPF circuit 1703 is the same as the LPF circuit 1403 in FIG. 9, the VCO 1704 is the same as the VCO 1404, and the variable frequency dividing circuit 1705 is 9 is the same as the variable frequency dividing circuit 1405 in FIG. 9, the frequency dividing number control circuit 1706 is the same as the frequency dividing number control circuit 1406 in FIG. 9, and the VCO automatic tuning circuit 1707 is the same as the VCO automatic tuning circuit 1407 in FIG. It is.

  The LPF circuit 1703 includes capacitors 1735 and 1736 and a resistor 1737. These capacitors 1735 and 1736 and the resistor 1737 are similar to the capacitors 1435 and 1436 and the resistor 1437 in the LPF circuit 1403, respectively.

  The VCO 1704 includes variable capacitance elements 1716 and 1717, an inductor 1715, PMOS transistors 1711 and 1713, NMOS transistors 1712 and 1714, capacitors 1718, 1719, 1720, 1721, 1722, and 1723, switches 1724, 1725, 1726, 1727, and 1728. 1729, the variable capacitance elements 1716 and 1717, the inductor 1715, the PMOS transistors 1711 and 1713, the NMOS transistors 1712 and 1714, the capacitances 1718 to 1723, and the switches 1724 to 1729 are respectively the variable capacitance elements 1416 and 1416 in the VCO 1404. 1417, inductor 1415, PMOS transistors 1411 and 1413, NMOS transistors 1412 and 1414, capacitor 141 ～1423, is the same as that of the switch 1424 to 1429.

  That is, the VCO 1704 is an LC oscillation circuit that uses an inverter circuit formed by a combination of a PMOS transistor and an NMOS transistor in a negative resistance circuit. The inverter circuit corresponds to a combination of a PMOS transistor 1711 and an NMOS transistor 1712. This is a combination of a PMOS transistor 1713 and an NMOS transistor 1714. In the VCO 1704, the LC resonance circuit for varying the oscillation frequency includes n inductors 1715, variable capacitance elements 1716 and 1717, capacitances 1718 to 1723 weighted by capacitance values, and switches 1724 to 1729. (For example, six) capacity arrays.

  The A / D / D / A conversion block 1740 includes an A / D conversion circuit 1741, a D / A conversion circuit 1742, and an A / D / D / A conversion control circuit 1743. The circuit 1741, the D / A conversion circuit 1742, and the A / D / D / A conversion control circuit 1743 are the A / D conversion circuit 1441 and the D / A conversion circuit 1442 in the A / D / D / A conversion block 1440 of FIG. The same as the A / D · D / A conversion control circuit 1443.

  In the case of this embodiment, the reference voltage generation circuit 1708 has the same configuration as the reference voltage generation circuit 208 in the third embodiment shown in FIG.

  That is, the reference voltage generation circuit 1708 includes a switch 1730, a switch 1731, and a switch 1732, and the switch 1730 is a phase frequency comparison circuit 1701 under the control of the VCO automatic tuning circuit 1707. And the LPF circuit 1703 (and the VCO 1704 ahead) are connected to each other and disconnected from each other. Further, the switch 1731 is converted into a state in which the GND potential as the low potential Vref_L and the LPF circuit 1703 (and the VCO 1704 ahead) are connected to each other and a state in which the switch 1731 is disconnected from each other. The VDD potential (power supply potential) as the potential Vref_H and the LPF circuit 1703 (and the VCO 1704 ahead) are converted into a state where they are connected to each other and a state where they are disconnected from each other.

  In the case of this embodiment, the procedure of automatic frequency tuning is that the low potential Vref_L and the high potential Vref_H in the fourth embodiment are replaced with the GND potential and the VDD potential, respectively. Since this is the same as the case of the embodiment, the description is omitted.

  According to the fifth embodiment as described above, the reference voltage generation circuit 1708 can be realized with a simple configuration including only the switches 1730, 1731, and 1732. Therefore, the design is facilitated.

  In addition, since a reference voltage source circuit for generating an analog potential is not necessary, the area occupied by the reference voltage generation circuit 1708 on the semiconductor integrated circuit is reduced, which is advantageous in that it can be manufactured at low cost.

1 is a circuit diagram showing a PLL frequency synthesizer circuit according to a first embodiment of the present invention. It is a figure (ideal state) for demonstrating VCO automatic frequency tuning in the PLL frequency synthesizer circuit of FIG. FIG. 2 is a diagram for explaining VCO automatic frequency tuning in the PLL frequency synthesizer circuit of FIG. 1 (when affected by element variations, temperature, and power supply voltage). It is a circuit diagram which shows the PLL frequency synthesizer circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the PLL frequency synthesizer circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the variable capacitance element (MOS capacity | capacitance) of a voltage control oscillation circuit (VCO), (a) is the figure shown with the symbol among these, (b) is the figure which showed the structure typically. It is a figure which shows the voltage characteristic (CV characteristic) of MOS capacity | capacitance. FIG. 6 is a diagram for explaining VCO automatic frequency tuning in the PLL frequency synthesizer circuit of FIGS. 4 and 5. It is a circuit diagram which shows the PLL frequency synthesizer circuit which concerns on the 4th Embodiment of this invention. FIG. 10 is a circuit diagram illustrating an A / D converter and a D / A converter included in the PLL frequency synthesizer circuit of FIG. 9. FIG. 10 is a diagram for explaining VCO automatic frequency tuning in the PLL frequency synthesizer circuit of FIG. 9. It is a circuit diagram which shows the PLL frequency synthesizer circuit which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of a general PLL frequency synthesizer circuit. 2 is a circuit diagram showing a voltage controlled oscillation circuit (VCO) of Non-Patent Document 1. FIG. 2 is a circuit diagram showing a voltage controlled oscillation circuit (VCO) of Non-Patent Document 1. FIG. 2 is a circuit diagram showing a voltage controlled oscillation circuit (VCO) of Non-Patent Document 1. FIG. 6 is a circuit diagram showing a voltage controlled oscillation circuit (VCO) of Patent Document 1. FIG. 10 is a circuit diagram showing a PLL frequency synthesizer circuit of Patent Document 4. FIG. It is a figure which shows the relationship between the VCO control voltage and oscillation frequency of the PLL frequency synthesizer circuit of FIG.

Explanation of symbols

618, 619, 620, 621, 622, 623 Capacitance 615 Inductor 616, 617 Variable capacitance element 604 Voltage controlled oscillation circuit 607 VCO automatic tuning circuit (tuning means)
608 Reference voltage generation circuit (reference potential application means)
118, 119, 120, 121, 122, 123 Capacitance 115 Inductor 116, 117 Variable capacitance element 104 Voltage controlled oscillation circuit 107 VCO automatic tuning circuit (tuning means)
108 Reference voltage generation circuit (reference potential application means)
218, 219, 220, 221, 222, 223 Capacitance 215 Inductors 216, 217 Variable capacitance element 204 Voltage controlled oscillation circuit 207 VCO automatic tuning circuit (tuning means)
208 Reference voltage generation circuit (reference potential application means)
1418, 1419, 1420, 1421, 1422, 1423 Capacitance 1415 Inductor 1416, 1417 Variable capacitance element 1404 Voltage controlled oscillation circuit 1407 VCO automatic tuning circuit (tuning means)
1408 Reference voltage generating circuit (reference potential applying means)
1440 A / D / D / A Conversion Block 1441 A / D Conversion Circuit (A / D Converter)
1442 D / A converter circuit (D / A converter)
1443 A / D / D / A conversion control circuit (holding unit)
1718, 1719, 1720, 1721, 1722, 1723 Capacitance 1715 Inductors 1716, 1717 Variable capacitance element 1704 Voltage controlled oscillation circuit 1707 VCO automatic tuning circuit (tuning means)
1708 Reference voltage generating circuit (reference potential applying means)
1740 A / D / D / A conversion block 1741 A / D conversion circuit (A / D converter)
1742 D / A converter circuit (D / A converter)
1743 A / D / D / A conversion control circuit (holding unit)

Claims (23)

In a PLL frequency synthesizer circuit integrated on a semiconductor integrated circuit,
A voltage-controlled oscillation circuit that oscillates using the resonance frequency of the LC resonance circuit including a capacitor, an inductor, and a variable-capacitance element; loops an oscillation signal output from the voltage-controlled oscillation circuit; A negative feedback feedback loop circuit capable of frequency pull-in operation to adjust the frequency of
Tuning means for tuning the oscillation frequency to be close to the lock frequency by adjusting a capacitance value of the capacitor of the voltage controlled oscillation circuit before the frequency pulling operation;
A reference potential applying means capable of applying a reference potential to the variable capacitance element of the voltage controlled oscillation circuit during a tuning operation by the tuning means;
With
The reference potential applying means is configured to selectively apply any one of two kinds of potentials to the variable capacitance element of the voltage controlled oscillation circuit during the tuning operation.
The tuning means, before the frequency pulling operation,
By adjusting the capacitance value of the capacitor of the voltage controlled oscillation circuit while applying one of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit, the oscillation frequency is adjusted to the lock frequency. A first tuning operation for searching for a first set value of the capacitance value of the capacitor that is closest to the frequency;
By adjusting the capacitance value of the capacitance of the voltage controlled oscillation circuit while applying the other potential of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit, the oscillation frequency is adjusted to the lock. A second tuning operation for searching for a second set value of the capacitance value that is closest to the frequency;
A third tuning operation for setting the capacitance value to a third set value near the middle of the first and second set values;
A PLL frequency synthesizer circuit configured to be capable of executing a series of tuning operations.   The variable capacitance element has a characteristic that a voltage range in which the capacitance characteristic of the variable capacitance element linearly changes is narrower than an absolute value of a voltage applied from the first terminal to the second terminal of the variable capacitance element. The PLL frequency synthesizer circuit according to claim 1, wherein an element having the same is used.   3. The PLL frequency synthesizer circuit according to claim 2, wherein a MOS capacitor is used as the variable capacitance element.   The value of fvco_step is set to satisfy fvco_step ≦ Δfvco / 4, where fvco_step is the frequency change amount of the oscillation frequency switching step by adjusting the capacitance value and Δfvco is the variable range of the oscillation frequency by voltage control. The PLL frequency synthesizer circuit according to claim 1, wherein the PLL frequency synthesizer circuit is provided.   5. The PLL frequency synthesizer circuit according to claim 1, wherein each of the two types of potentials is a fixed potential. 6.   6. The PLL frequency synthesizer according to claim 1, wherein each of the two types of potentials is set to a value such that a CV characteristic of the variable capacitance element is saturated. circuit.   Each of the two types of potentials varies in the CV characteristics of the variable capacitance element due to at least one of the following: variation in manufacturing of the variable capacitance element, variation in power supply voltage, and variation in ambient temperature. The PLL frequency synthesizer circuit according to claim 6, wherein the PLL frequency synthesizer circuit is set to a value that saturates the CV characteristic.   8. The PLL frequency synthesizer circuit according to claim 1, wherein one of the two types of potentials is a power supply potential and the other is a ground potential. The capacitor of the voltage controlled oscillation circuit is configured to include a plurality of capacitors,
The PLL according to any one of claims 1 to 8, wherein the tuning unit is configured to adjust the capacitance value by selecting an arbitrary combination of the plurality of capacitances. Frequency synthesizer circuit. The capacitor of the voltage controlled oscillation circuit is configured to include a plurality of capacitors,
The tuning means includes
In the first tuning operation, while searching for the first set value by adjusting the capacitance value by selecting an arbitrary combination of the plurality of capacitances,
Wherein in the second tuning operation, by adjusting the capacitance value by selecting any combination of said plurality of capacitor, according to claim 1 to 8, characterized in that searching said second set value The PLL frequency synthesizer circuit according to any one of the above. A holding unit that holds a value of a potential applied to the variable capacitance element in a locked state adjusted to the lock frequency by the frequency pulling operation;
11. The tuning unit according to claim 1, wherein the tuning unit is configured to perform a tuning operation while supplying a potential of a value held by the holding unit to the variable capacitance element. A PLL frequency synthesizer circuit according to any one of the preceding claims. An A / D converter that converts a potential applied to the variable capacitance element into a digital value;
A D / A converter capable of generating an analog potential corresponding to the digital value held by the holding unit and supplying the generated analog potential to the variable capacitance element;
With
The holding unit holds the digital value output from the A / D converter, thereby holding the value of the potential applied to the variable capacitance element in the locked state,
The tuning unit causes the D / A converter to generate an analog potential corresponding to the digital value held by the holding unit, and to supply the generated analog potential to the variable capacitance element. The PLL frequency synthesizer circuit according to claim 11 , wherein a potential having a value held by a unit is supplied to the variable capacitance element. The voltage controlled oscillation circuit is configured to include a plurality of capacitors,
The tuning means adjusts the capacitance value by selecting an arbitrary combination of the plurality of capacitors in a tuning operation performed while supplying the potential of the value held by the holding unit to the variable capacitance element. 13. The PLL frequency synthesizer circuit according to claim 11, wherein the PLL frequency synthesizer circuit is configured to search for a fourth set value of the capacitance value such that the oscillation frequency is closest to the lock frequency. The tuning means includes
In the tuning operation performed before the first frequency pull-in operation after powering on the PLL frequency synthesizer circuit, the first, second and third tuning operations are performed,
The holding unit holds a value of a potential applied to the variable capacitance element in a locked state adjusted to the lock frequency by a frequency pulling operation performed after the third tuning operation;
The tuning means includes
It is possible to perform a tuning operation performed before the frequency pull-in operation for the second and subsequent times after turning on the power to the PLL frequency synthesizer circuit while supplying the potential of the value held by the holding unit to the variable capacitance element. The PLL frequency synthesizer circuit according to any one of claims 11 to 13, wherein the PLL frequency synthesizer circuit is configured as described above.   The PLL frequency synthesizer circuit normally causes the holding unit to perform an operation of newly holding the value of the potential applied to the variable capacitance element in the locked state adjusted to the lock frequency by the frequency pulling operation. The PLL frequency synthesizer circuit according to any one of claims 11 to 14, wherein the PLL frequency synthesizer circuit is configured to shift from a state to a dormant state.   The tuning unit supplies the variable capacitance element with a potential of a value held by the holding unit, and performs a tuning operation performed before the frequency pull-in operation when the PLL frequency synthesizer circuit returns from a sleep state to a normal state. The PLL frequency synthesizer circuit according to claim 15, wherein the PLL frequency synthesizer circuit is configured so as to be able to be performed. An operating environment change detecting means for detecting a change in operating environment of the PLL frequency synthesizer circuit;
The holding unit performs a holding value update operation for newly holding a value of a voltage applied to the variable capacitance element in the locked state when a change in the operating environment is detected by the operating environment change detecting unit. The PLL frequency synthesizer circuit according to claim 11, wherein the PLL frequency synthesizer circuit is configured to perform the PLL frequency synthesizer circuit. When a change in the operating environment is detected by the operating environment change detecting means,
The tuning means performs the first, second and third tuning operations,
The said holding | maintenance part performs the said holding value update operation in the locked state adjusted to the said lock frequency by the frequency drawing operation in the state in which the said capacitance value was set to the said 3rd setting value. Item 18. The PLL frequency synthesizer circuit according to Item 17. A timing means for measuring an elapsed time since the holding unit last performed the holding operation of the voltage value applied to the variable capacitance element;
The holding unit is configured to perform a holding value update operation for newly holding a value of a voltage applied to the variable capacitance element in the locked state when a predetermined time is counted by the timing unit. The PLL frequency synthesizer circuit according to claim 11, wherein the PLL frequency synthesizer circuit is provided. When a predetermined time is measured by the time measuring means,
The tuning means performs the first, second and third tuning operations,
The said holding | maintenance part performs the said holding value update operation in the locked state adjusted to the said lock frequency by the frequency drawing operation in the state in which the said capacitance value was set to the said 3rd setting value. Item 20. A PLL frequency synthesizer circuit according to Item 19. A voltage-controlled oscillation circuit that oscillates using the resonance frequency of the LC resonance circuit including a capacitor, an inductor, and a variable-capacitance element; loops an oscillation signal output from the voltage-controlled oscillation circuit; In a method for tuning the oscillation frequency of a PLL frequency synthesizer circuit including a negative feedback feedback loop circuit capable of performing a frequency pull-in operation to adjust the frequency of
Before the frequency pulling operation,
The oscillation frequency is adjusted to the lock frequency by adjusting the capacitance value of the capacitor of the voltage controlled oscillation circuit while applying one of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit. A first tuning step for searching for a first set value of the capacitance value that is closest to
By adjusting the capacitance value of the capacitance of the voltage controlled oscillation circuit while applying the other potential of the two types of potentials to the variable capacitance element of the voltage controlled oscillation circuit, the oscillation frequency is adjusted to the lock. A second tuning step for searching for a second set value of the capacitance value that is closest to the frequency;
A third tuning step for setting the capacitance value used for generation of the resonance frequency to a third set value in the vicinity of the middle between the first and second set values;
And a frequency tuning method for a PLL frequency synthesizer circuit.   The frequency tuning method for a PLL frequency synthesizer circuit according to claim 21, wherein the second tuning step starts with the first set value as an initial value of the capacitance value. A holding step of holding a value of a potential applied to the variable capacitance element in a locked state adjusted to the lock frequency by the frequency pulling operation;
Before the frequency pulling operation after the holding step, the potential of the value held in the holding step is supplied to the variable capacitance element instead of the first, second, and third tuning steps. The frequency tuning method for a PLL frequency synthesizer circuit according to claim 21 or 22, wherein a fourth tuning step for performing a tuning operation is executed.

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