JP6736339B2 - PLL frequency synthesizer - Google Patents

Description

The present invention relates to a PLL frequency synthesizer.

Generally, a PLL (Phase Locked Loop) frequency synthesizer includes a voltage controlled oscillator (VCO), a phase comparison unit, a charge pump, and a loop filter, and a loop is configured by these. The PLL frequency synthesizer can output an oscillation signal having a frequency that is a constant multiple of the frequency of the reference oscillation signal.

The PLL frequency synthesizer operates as follows. A control voltage value is input to the voltage controlled oscillator, and an oscillation signal having a frequency according to this control voltage value is output from the voltage controlled oscillator. An oscillation signal output from the voltage controlled oscillator or a signal obtained by dividing the oscillation signal is input to the phase comparison unit as a feedback oscillation signal. The reference oscillation signal is also input to the phase comparison unit. The phase comparator detects the phase difference between the feedback oscillation signal and the reference oscillation signal, and outputs the phase difference signal representing the detected phase difference.

A charge pump that receives the phase difference signal outputs a charging/discharging current according to the phase difference represented by the phase difference signal. This charge/discharge current is input to the loop filter. For example, the loop filter includes a resistor and a capacitance element that are connected in series with each other, and also includes another capacitance element that is provided in parallel with the resistor and the capacitance element. The control voltage value output from the loop filter is input to the voltage controlled oscillator. In this way, the PLL frequency synthesizer outputs an oscillation signal having a frequency that is a constant multiple of the frequency of the reference oscillation signal.

The transfer function of the PLL frequency synthesizer configured as described above has characteristics based on the resistance value of the resistor of the loop filter and the capacitance value of the capacitive element, and the characteristics of the voltage controlled oscillator (between the control voltage value and the frequency of the oscillation signal). Relationship), and the charge/discharge current of the charge pump. For example, when a resistor and a capacitance element are formed on a semiconductor substrate, the resistance value of the resistor may vary by about ±15%, and the capacitance value of the capacitance element may vary by about ±10%. If there is such variation in characteristics, the actual transfer function of the PLL frequency synthesizer may not have the cutoff frequency or peak gain as designed, and may not meet the required specifications.

Inventions intended to solve such problems are disclosed in Patent Documents 1 and 2. The invention disclosed in Patent Document 1 monitors a control voltage value input to a voltage controlled oscillator, compares the control voltage value with a reference voltage value, and based on the comparison result, an output current of a charge pump or Adjust the characteristics of the voltage controlled oscillator. The invention disclosed in Patent Document 2 adjusts the characteristics of the voltage-controlled oscillator by using a frequency divider that divides an oscillation signal output from the voltage-controlled oscillator to generate a feedback oscillation signal.

U.S. Pat. No. 7,772,930 U.S. Pat. No. 8,483,985

In the invention disclosed in Patent Document 1, the reference voltage value may vary due to variations in the characteristics of resistors and the like, and the variations in the reference voltage value affect the adjustment result. Therefore, the actual transfer function of the PLL frequency synthesizer is Is not easy to do as designed.

In the invention disclosed in Patent Document 2, since the characteristics of the voltage controlled oscillator are adjusted by using the frequency divider, the frequency of the oscillation signal changes due to the adjustment. It may be necessary to set a frequency division ratio that cannot be realized by the frequency divider. If the frequency of the output oscillation signal is to be the same as the frequency of the reference oscillation signal, the frequency of the oscillation signal fluctuates by inserting a frequency divider for adjustment.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a PLL frequency synthesizer that can easily realize a desired transfer function.

The PLL frequency synthesizer of the present invention includes (1) a voltage control oscillator that inputs a control voltage value and outputs an oscillation signal having a frequency corresponding to the control voltage value, and (2) an oscillation signal output from the voltage control oscillator. Alternatively, a signal obtained by dividing the oscillation signal is input as a feedback oscillation signal, and a reference oscillation signal is also input, and a phase difference between the feedback oscillation signal and the reference oscillation signal is detected and the phase difference is represented. A phase comparison unit that outputs a phase difference signal, and (3) a phase difference signal output from the phase comparison unit is input, and a charge pump that outputs a charge/discharge current according to the phase difference represented by this phase difference signal, (4) A loop filter that includes a capacitive element that is charged and discharged by inputting the charging/discharging current output from the charge pump, and that outputs a control voltage value that is increased or decreased according to this charging/discharging amount to the voltage controlled oscillator 5) a setting unit the control voltage value is set to a predetermined value, a detecting unit for detecting the speed of change of the control voltage value when charge and discharge current is input to the loop filter output from (6) charge pump, ( 7) Adjust the charge/discharge current output from the charge pump, the characteristics of the loop filter, or the characteristics of the voltage-controlled oscillator based on the detection result of the detector to determine the rate of change of the control voltage value detected by the detector. A control unit that sets a desired value and sets the integral term of the loop filter in the open loop characteristic to a desired value. The setting unit includes a first amplifier having a voltage follower configuration and a switch, and sets the control voltage value to the voltage value V1 output from the output end of the first amplifier via the switch. The detection unit includes a second amplifier that inputs the control voltage value and the voltage value V2, and the second amplifier detects the changing speed of the control voltage value based on the comparison between the control voltage value and the voltage value V2. The first amplifier and the second amplifier have the same offset characteristic.

In the present invention, it is preferable that the detection unit uses the reference oscillation signal to detect the changing speed of the control voltage value.

In the present invention, the charge pump includes a plurality of current sources provided in parallel, and the control unit changes the number of current sources to be used among the plurality of current sources of the charge pump to output the charge pump. It is preferable to adjust the charging/discharging current. The loop filter includes a resistor for inputting the charging/discharging current output from the charge pump to the first end, and a capacitive element connected to the second end of the resistor, and the detection unit includes the first resistor of the resistor. It is preferable to monitor the potential at the end or the second end to detect the rate of change of the control voltage value. Further, the loop filter includes a resistor for inputting the charging/discharging current output from the charge pump to the first end, and a capacitive element connected to the second end of the resistor, and the setting unit includes the resistor of the resistor. It is also preferable that the potential of the first end or the second end is set to a predetermined value, and the detection unit monitors the potential of the first end or the second end of the resistor to detect the changing speed of the control voltage value. is there.

In the present invention, the loop filter connects the first capacitance element, the second capacitance element having a capacitance value larger than the capacitance value of the first capacitance element, the first capacitance element and the second capacitance element in parallel to each other. And a switch for disconnecting the second capacitive element by the switch, the detection unit detects the changing speed of the control voltage value and the control unit performs the adjustment. It is preferable to connect the second capacitance element in parallel with the first capacitance element.

In the present invention, a first charge pump and a second charge pump are provided as charge pumps, and the loop filter sets a capacitance element connected to the output terminal of the first charge pump and a voltage value corresponding to the voltage value of the capacitance element. An amplifier for outputting and a resistor having a first end connected to the output end of the amplifier and a second end connected to the output end of the second charge pump are included, and the control voltage value is voltage-controlled from the second end. It is preferable that the control unit adjusts the charge/discharge current output to the oscillator and output from the first charge pump.

In the present invention, the voltage-controlled oscillator is of the LC-VCO type that includes a capacitance element having a capacitance value that changes according to the control voltage value and outputs an oscillation signal having a frequency according to the capacitance value of the capacitance element. Therefore, it is preferable that the control unit adjusts the characteristic of the voltage controlled oscillator by changing the dependency of the capacitance value of the capacitance element on the control voltage value.

In the present invention, the voltage-controlled oscillator is of a Ring-VCO type that has a configuration in which a plurality of inverter circuits are connected in a ring shape and outputs an oscillation signal of a frequency according to the current supplied to these inverter circuits. Therefore, it is preferable that the control unit adjusts the characteristic of the voltage controlled oscillator by changing the dependency of the current supply amount to the inverter circuit on the control voltage value.

The PLL frequency synthesizer of the present invention can easily realize a desired transfer function even if the parameters of the PLL (eg, resistance value, capacitance value, current of charge pump, etc.) do not reach a desired value due to manufacturing variations. it can.

FIG. 1 is a diagram showing a configuration of a PLL frequency synthesizer 1. FIG. 2 is a diagram showing a phase domain model of the PLL frequency synthesizer 1. FIG. 3 is a diagram illustrating an example of the adjustment operation by the control unit 90 of the PLL frequency synthesizer 1. FIG. 4 is a diagram showing a configuration example of the setting unit 70 and the detection unit 80. FIG. 5 is a diagram showing a configuration example of the charge pump 30. FIG. 6 is a diagram showing a configuration example of the loop filter 40. FIG. 7 is a diagram showing another configuration example of the loop filter 40. FIG. 8 is a diagram showing still another configuration of the loop filter 40. FIG. 9 is a diagram showing the state machine SCPCC. FIG. 10 is a table summarizing the output settings in each state in the state machine SCPCC. FIG. 11 is a diagram showing a state machine SCPCCNT. FIG. 12 is a table summarizing output settings in each state in the state machine SCPCCNT. Figure 13 is a diagram showing a scan te Tomashin SCPCTL. FIG. 14 is a diagram showing the state machine SCSG. FIG. 15 is a table summarizing output settings in each state in the state machine SCSG. FIG. 16 is a diagram showing a configuration example of the loop filter 40. FIG. 17 is a diagram showing a configuration example of the loop filter 40. FIG. 18 is a diagram showing a configuration example of the loop filter 40.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. The present invention is not limited to these exemplifications, but is defined by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

FIG. 1 is a diagram showing a configuration of a PLL frequency synthesizer 1. The PLL frequency synthesizer 1 includes a reference oscillator 10, a phase comparison unit 20, a charge pump 30, a loop filter 40, a voltage controlled oscillator 50, a frequency divider 60, a setting unit 70, a detection unit 80, and a control unit 90.

The reference oscillator 10 includes, for example, a crystal oscillator, and outputs a highly accurate stabilized reference oscillation signal having a constant frequency to the phase comparison unit 20. The phase comparison section 20 inputs this reference oscillation signal. The phase comparison unit 20 also receives the feedback oscillation signal output from the frequency divider 60. The phase comparison unit 20 detects a phase difference between the feedback oscillation signal and the reference oscillation signal, and outputs a phase difference signal representing this phase difference to the charge pump 30. The phase difference signal indicates which of the reference oscillation signal and the feedback oscillation signal has the advanced phase.

The charge pump 30 receives the phase difference signal output from the phase comparison unit 20 and outputs a charge/discharge current according to the phase difference represented by the phase difference signal to the loop filter 40. The charge/discharge current output from the charge pump 30 to the output to the loop filter 40 has different polarities depending on which of the reference oscillation signal and the feedback oscillation signal has the advanced phase. The loop filter 40 includes a capacitive element that is charged and discharged by inputting the charging/discharging current output from the charge pump 30, and outputs a control voltage value that is increased/decreased according to the charging/discharging amount to the voltage controlled oscillator 50. The loop filter 40 also includes a resistor in addition to the capacitive element.

The voltage controlled oscillator 50 inputs the control voltage value output from the loop filter 40 and outputs an oscillation signal having a frequency according to this control voltage value. The frequency divider 60 inputs the oscillation signal output from the voltage controlled oscillator 50, divides the oscillation signal by N to generate a feedback oscillation signal, and outputs the feedback oscillation signal to the phase comparison unit 20.

The phase comparison unit 20, charge pump 30, loop filter 40, voltage controlled oscillator 50, and frequency divider 60 form a loop. In this loop, the charge/discharge current is input from the charge pump 30 to the loop filter 40 so that the phase difference between the reference oscillation signal and the feedback oscillation signal input to the phase comparison unit 20 becomes small. When the operation of this loop is stable, the oscillation signal output from the voltage controlled oscillator 50 has a frequency N times the frequency of the reference oscillation signal. The frequency divider 60 may not be provided, and in this case, the oscillation signal output from the voltage controlled oscillator 50 has the same frequency as the frequency of the reference oscillation signal.

Details of the setting unit 70, the detection unit 80, and the control unit 90 will be described later.

FIG. 2 is a diagram showing a phase domain model of the PLL frequency synthesizer 1. The open loop characteristic H(s) of the PLL frequency synthesizer 1 is expressed by the following equation (1). Kvco represents the characteristic of the voltage controlled oscillator 50 (dependence of the frequency of the oscillation signal on the control voltage value). Kp is a proportional term of the loop filter 40 and is expressed by the following equation (2). Ki is an integral term of the loop filter 40 and is expressed by the following equation (3). R is the resistance value of the resistor of the loop filter 40. C is the capacitance value of the capacitive element of the loop filter 40.

Icpp is a current that contributes to the proportional term of the charging/discharging current Icp given from the charge pump 30 to the loop filter 40. Icpi is a current that contributes to the integral term in the charge/discharge current Icp given to the loop filter 40 from the charge pump 30. Normally, the relationship of the following expression (4) may be satisfied.

Generally, the current output from the charge pump 30 is generated based on the voltage value Vref supplied from a BGR (Band Gap Reference) block. The charging/discharging current Icp given from the charge pump 30 to the loop filter 40 is expressed by the following equation (5).

Using this equation (5), the above equation (2) becomes the following equation (6). As can be seen from the equation (6), the proportional term Kp of the loop filter 40 does not depend on either the resistance value R or the capacitance value C. Since the voltage value Vref supplied from the BGR block is excellent in stability, the proportional term Kp of the loop filter 40 is excellent in stability.

Further, using the above equation (5), the above equation (3) becomes the following equation (7). As can be seen from the equation (7), the integral term Ki of the loop filter 40 depends on both the resistance value R and the capacitance value C. Therefore, if the resistance value R or the capacitance value C varies, the integral term Ki of the loop filter 40 also varies.

When the open-loop characteristic H(s) of the PLL frequency synthesizer 1 fluctuates due to the variation in the resistance value R or the capacitance value C in this way, the actual transfer function of the PLL frequency synthesizer 1 becomes the cutoff frequency or peak as designed. It may not have a gain and may not meet the required specifications. In order to solve such a problem, the PLL frequency synthesizer 1 of this embodiment includes a setting unit 70, a detection unit 80, and a control unit 90 to facilitate the realization of a desired transfer function.

The detection unit 80 detects the changing speed of the control voltage value when a constant current output from the charge pump 30 is input to the loop filter 40. The detection unit 80 may measure the control voltage values V1 and V2 at arbitrary two times t1 and t2, respectively. The detection unit 80 may measure the time t2 at which the control voltage value changes to V2 by a predetermined ΔV after the setting unit 70 sets the control voltage value to the initial value V1 at the time t1. Further, the detection unit 80 may measure the control voltage value V2 at time t2 after a certain time Δt has elapsed from the time t1 when the setting unit 70 sets the control voltage value to the initial value V1. In any case, the change rate ΔV/Δt of the control voltage value is expressed by the following equation (8).

The control unit 90 controls the overall operation of the PLL frequency synthesizer 1. In particular, the control unit 90 uses the charge/discharge current Icp output from the charge pump 30, the characteristics of the loop filter 40 (in particular, the resistance value R of the resistor and the capacitance value C of the capacitive element, based on the detection result of the detection unit 80). Characteristics) or the characteristic Kvco of the voltage controlled oscillator 50 (dependence of the frequency of the oscillation signal on the control voltage value) is adjusted.

FIG. 3 is a diagram illustrating an example of the adjustment operation by the control unit 90 of the PLL frequency synthesizer 1. In this figure, the horizontal axis represents time and the vertical axis represents control voltage value. In addition, in this figure, each of the three straight lines A, B, and C indicates different control voltage value changing speeds. If the changing speed of the control voltage value indicated by the straight line A is preferable, on the other hand, the changing speed of the control voltage value indicated by the straight line B is slow, and the changing speed of the control voltage value indicated by the straight line C is fast. The control unit 90 performs adjustment so that the rate of change of the control voltage value indicated by the straight line A becomes a preferable value.

An example of the adjusting operation by the control unit 90 of the PLL frequency synthesizer 1 is as follows. In the first step, the control unit 90 causes the setting unit 70 to set the control voltage value to V1. In the subsequent second step, the control unit 90 causes the phase comparison unit 20 to output the phase difference signal for a certain period of time Δt to supply the constant current Icp output from the charge pump 30 to the loop filter 40. In the second step performed first, the amount of current is set to the minimum value that can be set.

In the subsequent third step, the control unit 90 acquires the control voltage value measured by the detection unit 80 after the end of the second step. Then, in the fourth step, when the control unit 90 determines that the control voltage value measured in the third step does not exceed the predetermined value V2, the control unit 90 increases the set value of the current Icp to start the first step and thereafter. repeat. When the control unit 90 determines that the control voltage value measured in the third step exceeds the predetermined value V2, the adjustment operation ends.

In this operation example, the initial value of the current Icp is set to the minimum value that can be set and the current Icp is gradually increased, but the present invention is not limited to this. The current Icp may be gradually decreased by setting the initial value of the current Icp to the maximum value that can be set. Further, if the initial value of the current Icp is set to an arbitrary value and the control voltage value measured in the third step is less than the predetermined value V2 at this initial value, the current Icp is gradually increased. Sometimes, if the control voltage value measured in the third step exceeds the predetermined value V2, the current Icp may be gradually decreased.

The time Δt at which the current is supplied from the charge pump 30 to the loop filter 40 can be monitored by using a counter that counts the pulses of the reference oscillation signal (or another signal whose frequency is stable) output from the reference oscillator 10. it can. That is, the time Δt can be obtained from the count value M by the counter and the frequency F of the reference oscillation signal by the following equation (9).

The current Icpi supplied from the charge pump 30 to the loop filter 40 is the time Δt for supplying the current from the charge pump 30 to the loop filter 40, the voltage difference ΔV between the initial value V1 of the control voltage value and the predetermined value V2 at the end of the adjustment. , And the capacitance value C of the capacitance element of the loop filter 40 are represented by the following (10). Using this equation (10), the above equation (3) becomes the following equation (11).

Since the voltage difference ΔV is generated by the BGR block, the variation is small. Since the time Δt is obtained by using the reference oscillation signal output from the reference oscillator 10, the variation is small. The equation (11) does not depend on either the resistance value R or the capacitance value C. By adjusting the current Icpi, the changing speed of the control voltage value can be set to a desired value, and the integral term Ki can be set to a desired value.

FIG. 4 is a diagram showing a configuration example of the setting unit 70 and the detection unit 80. The setting unit 70 includes an amplifier 71 and a switch 72. The amplifier 71 has two input ends and one output end, the voltage value V1 is input to one input end, and the other input end is connected to the output end. The amplifier 71 has a voltage follower configuration. The first end of the switch 72 is connected to the output end of the amplifier 71, and the second end of the switch 72 is connected to the location where the control voltage value should be set to V1. The opening/closing operation of the switch 72 is controlled by the VCFIXp signal output from the control unit 90.

The detection unit 80 includes an amplifier 81. The amplifier 81 has two input ends and one output end, the voltage value V2 is input to one input end, the control voltage value is input to the other input end, and the VCH signal is output from the output end to the control unit 90. Output to. The amplifier 81 sets the VCH signal to the low level when the control voltage value is V2 or less, and sets the VCH signal to the high level when the control voltage value exceeds V2.

The control unit 90 sets the control voltage value to the initial value V1 by turning on the switch 72 of the setting unit 70 for a certain period by the VCFIXp signal. The control unit 90 turns the switch 72 to the off state at time t1, and then detects the level of the VCH signal output from the amplifier 81 of the detection unit 80 at time t2. The control unit 90 can determine whether the changing speed of the control voltage value is larger or smaller than the target value based on the level of this VCH signal.

FIG. 5 is a diagram showing a configuration example of the charge pump 30. The charge pump 30 includes current sources 31 _{1 to} 31 _K , current sources 32 _{1 to} 32 _K , switches 33 _{1 to} 33 _K , switches 34 _{1 to} 34 _K , a switch 35, and a switch 36. K is an integer of 2 or more, and k is each integer of 1 or more and K or less.

The current source 31 _k and the switch 33 _k are connected in series with each other and are provided between the high-potential power supply potential and the switch 35. The current source 32 _k and the switch 34 _k are connected in series with each other and are provided between the low-potential ground potential and the switch 36. The connection point between the switch 35 and the switch 36 is connected to the loop filter 40.

The open/closed state of each of the switches 33 _{1 to} 33 _K and the switches 34 _{1 to} 34 _K is set by the CPSetting signal output from the control unit 90. The opening/closing operation of each of the switch 35 and the switch 36 is controlled by the phase difference signal (UP signal, DOWN signal) output from the phase comparison unit 20. The switch 35 and the switch 36 are not turned on at the same time.

When the switch 35 is on, the capacitive element of the loop filter 40 is charged. The amount of charge at that time depends on the number of switches in the ON state among the switches 33 _{1 to} 33 _K. Further, when the switch 36 is in the ON state, the capacitive element of the loop filter 40 is discharged. The amount of discharge at that time depends on the number of switches in the ON state among the switches 34 _{1 to} 34 _K.

The control unit 90 adjusts the number of switches in the ON state among the switches 33 _{1 to} 33 _K by the CPSetting signal and also adjusts the number of switches in the ON state among the switches 34 _{1 to} 34 _K. The charge/discharge current Icp applied from the charge pump 30 to the loop filter 40 can be adjusted.

FIG. 6 is a diagram showing a configuration example of the loop filter 40. The loop filter 40 shown in this figure includes a resistor 41 and a capacitive element 42. The charge/discharge current output from the charge pump 30 is input to the first end of the resistor 41. The second end of the resistor 41 is connected to the capacitive element 42. In the loop filter 40 having such a configuration, the setting unit 70 sets the second end of the resistor 41 (the connection point between the resistor 41 and the capacitive element 42) to the initial value V1, and the detection unit 80 sets the resistor to the resistor. It is preferable to detect the voltage value of the second end of 41 as the control voltage value.

If the resistance value of the resistor 41 is variable, the control unit 90 can adjust the characteristics of the loop filter 40 by adjusting the resistance value. If the capacitance value of the capacitive element 42 is variable, the control unit 90 can adjust the capacitance value to adjust the characteristic of the loop filter 40.

As shown in FIG. 16, the setting unit 70 sets the second end of the resistor 41 to the initial value V1, and the detection unit 80 sets the voltage value of the first end of the resistor 41 as the control voltage value. It may be detected. As shown in FIG. 17, the setting unit 70 sets the first end of the resistor 41 to the initial value V1, and the detection unit 80 detects the voltage value of the second end of the resistor 41 as the control voltage value. May be. Further, as shown in FIG. 18, the setting unit 70 sets the first end of the resistor 41 to the initial value V1, and the detection unit 80 sets the voltage value of the first end of the resistor 41 as the control voltage value. It may be detected.

FIG. 7 is a diagram showing another configuration example of the loop filter 40. The loop filter 40 shown in this figure includes a capacitor 41 and a switch 44 in addition to the resistor 41 and the capacitor 42. The switch 44 is provided between the connection point between the resistor 41 and the capacitance element 42 and the capacitance element 43. When the switch 44 is in the ON state, the capacitance element 42 and the capacitance element 43 are connected in parallel with each other. The capacitance value of the capacitance element 43 is larger than the capacitance value of the capacitance element 42.

The open/closed state of the switch 44 is set by a signal output from the control unit 90. When the switch 44 is off, the capacitance value of the loop filter 40 is small, and when the switch 44 is on, the capacitance value of the loop filter 40 is large. The control unit 90 makes the adjustment by turning off the switch 44, and turns on the switch 44 after the adjustment is completed.

The configuration of the loop filter 40 shown in FIG. 7 is useful in the following cases. That is, in order to reduce the effect of input jitter, it is preferable to lower the cutoff frequency of the loop filter, and in that case, a capacitive element having a large capacitance value is used. When the capacitance value of the loop filter is large, the change speed of the control voltage value becomes slow, and the time Δt required for the control voltage value to change from the initial value V1 to V2 by ΔV becomes long. For example, assume that ΔV is 0.5 V, the capacitance value is 220 pF, and the current Icp output from the charge pump is 20 μA. At this time, the time Δt becomes 5.5 μs. The circuit scale of a counter that counts for a long time of 5.5 μs is large. Although it is possible to measure the time with an analog circuit using a resistor and a capacitive element, it is not realistic because there are several tens% of variations in the resistor and the capacitance value.

In such a case, in order to reduce the time required for the adjustment, the adjustment time is shortened (for example, to several tens of nanoseconds) by turning off the switch 44 to reduce the capacitance value when performing the adjustment. ). After the adjustment is completed, the switch 44 is turned on to increase the capacitance value, so that the influence of the input jitter can be reduced.

FIG. 8 is a diagram showing still another configuration of the loop filter 40. In the configuration shown in this figure, a first charge pump 30A and a second charge pump 30B are provided as charge pumps. The loop filter 40 includes a capacitive element 45, an amplifier 46 and a resistor 47.

The capacitive element 45 is provided between the output end of the first charge pump 30A and the ground potential end. The amplifier 46 has two input ends and one output end, the voltage value of the capacitive element 45 is input to one input end, and the other input end is connected to the output end. The amplifier 46 has a voltage follower configuration. The amplifier 46 outputs a voltage value according to the voltage value of the capacitive element 45 from the output end. The first end of the resistor 47 is connected to the output end of the amplifier 46, and the second end of the resistor 47 is connected to the output end of the second charge pump 30B. The potential of the second end of the resistor 47 is output to the voltage controlled oscillator 50 as a control voltage value.

The first charge pump 30A outputs a charge/discharge current that contributes to the integral term of the loop filter 40. The second charge pump 30B outputs a charge/discharge current that contributes to the proportional term of the loop filter 40. The controller 90 adjusts the charging/discharging current output from the first charge pump 30A.

If the resistance value of the resistor 47 is variable, the control unit 90 can adjust the resistance value to adjust the characteristic of the loop filter 40. If the capacitance value of the capacitance element 45 is variable, the control unit 90 can adjust the capacitance value to adjust the characteristic of the loop filter 40.

The control unit 90 may adjust the characteristic Kvco of the voltage controlled oscillator 50. When the voltage controlled oscillator 50 is of the LC-VCO type, that is, it includes a capacitance element having a capacitance value that changes according to the control voltage value, and outputs an oscillation signal having a frequency according to the capacitance value of this capacitance element. In the case of the control type, the control unit 90 can adjust the characteristic of the voltage controlled oscillator 50 by changing the dependency of the capacitance value of the capacitive element on the control voltage value. This capacitive element may be a varactor, or may have a configuration in which the drain and source of a MOS transistor are connected to each other. The capacitance value of the capacitance element can be adjusted by providing a plurality of sets in parallel with one set of the capacitance element and the switch connected in series, and adjusting the number of switches in the ON state among the plurality of switches. is there.

When the voltage controlled oscillator is of the Ring-VCO type, that is, it has a configuration in which a plurality of inverter circuits are connected in a ring shape and outputs an oscillation signal of a frequency according to the current supplied to these inverter circuits. In the case of the type, the control unit 90 can adjust the characteristic of the voltage controlled oscillator 50 by changing the dependency of the current supply amount to the inverter circuit on the control voltage value.

In the present embodiment, the changing speed of the control voltage value when the charging/discharging current output from the charge pump 30 is input to the loop filter 40 is detected by the detection unit 80, and the charge pump 30 outputs the detection result based on the detection result. Since the control unit 90 adjusts the output charge/discharge current, the characteristics of the loop filter 40, or the characteristics of the voltage controlled oscillator 50, a desired transfer function can be easily realized.

That is, in the invention disclosed in Patent Document 1, since the adjustment is performed based on the comparison result of the control voltage value and one reference voltage value, if the reference voltage value varies due to the variation of the characteristics of the resistor or the like, the reference is performed. The variation in voltage value affects the adjustment result, and it is not easy to make the actual transfer function of the PLL frequency synthesizer as designed. On the other hand, in the present embodiment, even if the voltage values V1 and V2 vary due to the variation in the characteristics of the resistor or the like, the variation does not affect the changing speed (ΔV/Δt) of the control voltage value. A desired transfer function can be easily realized. In the present embodiment, since the amplifier 71 of the setting unit 70 and the amplifier 81 of the detection unit 80 can have the same characteristics, the influence of the offset of these amplifiers can be suppressed.

Further, in the invention disclosed in Patent Document 2, there is a problem caused by adjusting the characteristics of the voltage controlled oscillator using the frequency divider. On the other hand, in the present embodiment, since the adjustment can be performed without using the frequency divider, it is possible to easily realize a desired transfer function even if the frequency divider is not provided.

Next, the control by the control unit 90 in the PLL frequency synthesizer 1 of this embodiment will be described in detail. Here, one mode of control by the control unit 90 when adjusting the charge/discharge current Icp of the charge pump 30 in the configurations shown in FIGS. 1, 4 and 5 will be described. 9 to 15 are diagrams illustrating a state machine for explaining control by the control unit 90.

The control by the control unit 90 has four state machines SCPCC, SCPCCNT, SCPCTL and SCSG. The state machine SCPCC controls the entire adjustment operation, and controls the operations of the setting unit 70 and the detection unit 80. The state machine SCPCCNT controls the counting operation of the counter. The state machine SCPCTL controls the current output operation of the charge pump 30. The state machine SCSG determines the end of the adjustment operation.

FIG. 9 is a diagram showing the state machine SCPCC. FIG. 10 is a table summarizing the output settings in each state in the state machine SCPCC. The state machine SCPCC has four states WAIT, CAL, FIN and TMP. If the variable FCNT has a value 0 in the WAIT state, the variable CNT stays in the WAIT state, the VCFIXp signal becomes high level, the switch 72 of the setting unit 70 is turned on, and the control voltage value is set to the initial value V1.

When the variable FCNT has a value of 1 in the WAIT state, the WAIT state is transited to the CAL state, the PFDENp signal becomes high level, the phase difference signal is output from the phase comparator 20, and the constant current output from the charge pump 30. Icp is supplied to the loop filter 40. If the variable CALAGAIN has the value 1 in the CAL state, the CAL state transits to the WAIT state. If the variable CALDNE has the value 1 in the CAL state, the CAL state transits to the FIN state. In the FIN state, both the VCFIXp signal and the PFDENp signal are low level, and normal operation is performed.

FIG. 11 is a diagram showing a state machine SCPCCNT. FIG. 12 is a table summarizing output settings in each state in the state machine SCPCCNT. The state machine SCPCCNT controls the counting operation of the counter in the WAIT state or the CAL state. When the count value is not the predetermined number M, the FCNT variable has the value 0. When the count value reaches the predetermined number M, the FCNT variable becomes the value 1 and the state transits. Further, after the count value reaches the predetermined number M, the count value is initialized to 0.

Figure 13 is a diagram showing a scan te Tomashin SCPCTL. Scan Te Tomashin SCPCTL, in CAL state, based on the value of VCH signal output from the detecting unit 80 controls the current Icp output operation of the charge pump 30. That is, if the VCH signal has a value of 0, it is determined that the control voltage value changes at a slow rate (that is, the current Icp is small) and the current Icp is increased. If the VCH signal has the value 1, it is determined that the change speed of the control voltage value is fast (that is, the current Icp is large), and the current Icp is reduced.

FIG. 14 is a diagram showing the state machine SCSG. FIG. 15 is a table summarizing output settings in each state in the state machine SCSG. The state machine SCSG determines the end of the adjustment operation.

If the VCH signal has a value of 0 in the INIT state, the state transitions to the UP state and the CALAGAIN signal becomes high level. If the VCH signal has a value of 0 in the UP state, the CALAGAIN signal remains at the high level and remains in the UP state. If the VCH signal has a value of 1 in the UP state, the state transitions to the DNE state, and the CALDNE signal becomes high level.

If the VCH signal has a value of 1 in the INIT state, it transits to the DN state and the CALAGAIN signal becomes high level. If the VCH signal has a value of 1 in the DN state, it stays in the DN state and the CALAGAIN signal becomes high level. If the VCH signal has a value of 0 in the DN state, the state transitions to the DNE state, and the CALDNE signal becomes high level.

That is, if the VCH signal remains at the value 0 or the VCH signal remains at the value 1, it is determined that the adjustment is insufficient, the CALAGAIN variable becomes high level, and the CAL state changes to the WAIT state. After the transition, the adjustment operation is repeated (FIG. 9).

On the other hand, when the VCH signal transits from the value 0 to 1 or when the VCH signal transits from the value 1 to 0, it is determined that the adjustment operation is completed, the state transits to the DNE state, and the CALDNE signal becomes high level. Become. When the CALDNE signal becomes high level, the CAL state is transited to the FIN state and normal operation is performed (FIG. 9).

DESCRIPTION OF SYMBOLS 1... PLL frequency synthesizer, 10... Reference oscillator, 20... Phase comparison part, 30... Charge pump, 30A... 1st charge pump, 30B... 2nd charge pump, 40... Loop filter, 50... Voltage controlled oscillator, 60... Minute Circulator, 70... Setting unit, 80... Detection unit, 90... Control unit.

Claims (9)

A voltage-controlled oscillator that inputs a control voltage value and outputs an oscillation signal having a frequency according to the control voltage value,
An oscillation signal output from the voltage controlled oscillator or a signal obtained by dividing the oscillation signal is input as a feedback oscillation signal, and a reference oscillation signal is also input, and the phase difference between the feedback oscillation signal and the reference oscillation signal is input. And a phase comparison unit that outputs a phase difference signal representing this phase difference,
A charge pump that inputs the phase difference signal output from the phase comparison unit and outputs a charge/discharge current according to the phase difference represented by the phase difference signal,
A loop filter that includes a capacitive element that is charged and discharged by inputting a charge/discharge current output from the charge pump, and outputs the control voltage value that is increased or decreased according to the charge/discharge amount to the voltage controlled oscillator,
A setting unit for setting the control voltage value to a predetermined value,
A detection unit that detects the rate of change of the control voltage value when the charge/discharge current output from the charge pump is input to the loop filter,
The control voltage value detected by the detection unit by adjusting the charge/discharge current output from the charge pump, the characteristic of the loop filter or the characteristic of the voltage controlled oscillator based on the detection result of the detection unit. And a control unit that sets the change rate of to a desired value and sets the integral term of the loop filter in the open loop characteristic to a desired value,
Equipped with
The setting unit includes a first amplifier having a voltage follower configuration and a switch, and sets the control voltage value to a voltage value V1 output from the output end of the first amplifier via the switch,
The detection unit includes a second amplifier that inputs the control voltage value and the voltage value V2, and the changing speed of the control voltage value based on the comparison between the control voltage value and the voltage value V2 by the second amplifier. Detect
The first amplifier and the second amplifier have the same offset characteristics,
PLL frequency synthesizer. The detection unit detects the rate of change of the control voltage value using the reference oscillation signal,
The PLL frequency synthesizer according to claim 1. The charge pump includes a plurality of current sources arranged in parallel,
The control unit adjusts the charging/discharging current output from the charge pump by changing the number of current sources used among the plurality of current sources of the charge pump.
The PLL frequency synthesizer according to claim 1 or 2 . The loop filter includes a resistor for inputting a charging/discharging current output from the charge pump to a first end, and a capacitive element connected to a second end of the resistor,
The detection unit monitors a potential of the first end or the second end of the resistor to detect a changing speed of the control voltage value.
PLL frequency synthesizer according to any one of claims 1-3. The loop filter includes a resistor for inputting a charging/discharging current output from the charge pump to a first end, and a capacitive element connected to a second end of the resistor,
The setting unit sets the potential of the first end or the second end of the resistor to a predetermined value,
The detection unit monitors a potential of the first end or the second end of the resistor to detect a changing speed of the control voltage value.
The PLL frequency synthesizer according to any one of claims 1 to 4 . The loop filter connects the first capacitance element, the second capacitance element having a capacitance value larger than the capacitance value of the first capacitance element, the first capacitance element and the second capacitance element in parallel to each other. And a switch for
In a state where the second capacitive element is separated by the switch, the detection unit detects the changing speed of the control voltage value and the control unit performs adjustment,
After the adjustment by the control unit, the switch connects the second capacitive element in parallel to the first capacitive element,
PLL frequency synthesizer according to any one of claims 1-5. The charge pump includes a first charge pump and a second charge pump,
The loop filter includes a capacitive element connected to the output terminal of the first charge pump, an amplifier that outputs a voltage value according to the voltage value of the capacitive element, and a first terminal connected to the output terminal of the amplifier. And a resistor having a second end connected to the output end of the second charge pump, the control voltage value being output from the second end to the voltage controlled oscillator,
The control unit adjusts a charging/discharging current output from the first charge pump,
PLL frequency synthesizer according to any one of claims 1-6. The voltage-controlled oscillator includes a capacitance element having a capacitance value that changes according to the control voltage value, and is of an LC-VCO type that outputs an oscillation signal having a frequency according to the capacitance value of the capacitance element.
The control unit adjusts the characteristic of the voltage controlled oscillator by changing the dependency of the capacitance value of the capacitive element on the control voltage value,
PLL frequency synthesizer according to any one of claims 1-7. The voltage-controlled oscillator has a structure in which a plurality of inverter circuits are connected in a ring shape, and is of a Ring-VCO type that outputs an oscillation signal having a frequency according to a current supplied to these inverter circuits.
The control unit adjusts the characteristics of the voltage controlled oscillator by changing the dependency of the current supply amount to the inverter circuit on the control voltage value.
PLL frequency synthesizer according to any one of claims 1-7.

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