CN219514064U

CN219514064U - Ring oscillator and phase-locked loop

Info

Publication number: CN219514064U
Application number: CN202223489702.XU
Authority: CN
Inventors: 刘梁凝一
Original assignee: Fuman Microelectronics Group Co ltd
Current assignee: Fuman Microelectronics Group Co ltd
Priority date: 2022-12-22
Filing date: 2022-12-22
Publication date: 2023-08-11
Anticipated expiration: 2032-12-22

Abstract

The utility model provides a ring oscillator, which comprises an inverter delay module, an adjusting module, a switch module, a first capacitor and a second capacitor, wherein the inverter delay module is connected with the adjusting module; the control end of the adjusting module is connected with the first end of the first capacitor and an input voltage end, and the input voltage end is used for outputting an input voltage to adjust the on-resistance of the adjusting module; the first end of the adjusting module is connected with the power supply voltage end and the second end of the first capacitor, and the second end of the adjusting module is connected with the first end of the switch module; the control end of the switch module is connected with a reference voltage end, and the reference voltage end is used for inputting a reference voltage to drive the switch module; the second end of the switch module is connected with the first end of the inverter delay module so as to output an output current to the inverter delay module; the inverter delay module comprises a frequency output end for outputting an output frequency.

Description

Ring oscillator and phase-locked loop

Technical Field

The present utility model relates to the field of phase-locked loops, and in particular, to a ring oscillator and a phase-locked loop.

Background

A Phase Locked Loop (PLL) plays a role of generating a frequency source, and an output signal thereof can be used as a clock signal, for example, the PLL is applied to a digital processing circuit, and generally consists of an input reference clock, a phase frequency detector PFD, a charge pump CP, a filter LPF, a voltage controlled oscillator VCO, a frequency divider, and other modules, and in a locked state, the phase difference between the input reference clock and the clock divided by the VCO is 0 or a fixed value, so that the PLL can provide a stable and high-precision clock. The VCO is one of the key modules in the PLL circuit design, and its quality directly determines the overall operating quality of the entire PLL circuit, and when the VCO operating voltage is in excess of the VCO rated operating voltage for a long period of time, the VCO will be damaged, and even seriously affects the stability and accuracy of PLL operation.

In the prior art, the voltage-controlled oscillator only has the option of voltage adjustment, but for the voltage-controlled oscillator, the output frequency of the oscillator is changed through a voltage value, and the frequency modulation range is very small; in addition, the bandwidth of the phase-locked loop in the prior art can only be smaller than 10% of the reference frequency, so that the bandwidth of the phase-locked loop is limited and the power consumption of the phase-locked loop is improved.

Disclosure of Invention

The utility model provides a ring oscillator and a phase-locked loop, which are used for solving the problems of small frequency modulation range of a voltage-controlled oscillator, small bandwidth of the phase-locked loop and high power consumption.

According to a first aspect of the present utility model, there is provided a ring oscillator comprising an inverter delay module, a regulation module, a switch module, a first capacitor and a second capacitor;

the control end of the adjusting module is connected with the first end of the first capacitor and an input voltage end, and the input voltage end is used for outputting an input voltage to adjust the on-resistance of the adjusting module; the first end of the adjusting module is connected with the power supply voltage end and the second end of the first capacitor, and the second end of the adjusting module is connected with the first end of the switch module; the control end of the switch module is connected with a reference voltage end, and the reference voltage end is used for inputting a reference voltage to drive the switch module; the second end of the switch module is connected with the first end of the inverter delay module so as to output an output current to the inverter delay module; the second end of the inverter delay module is connected with the first end of the second capacitor, and the second end of the second capacitor is grounded; the inverter delay module comprises a frequency output end and a delay module, wherein the frequency output end is used for outputting an output frequency;

The switch module is used for: the first target impedance is obtained by performing first-stage adjustment on the target impedance of the adjusting module by being controlled by the reference voltage to be turned on or turned off;

the adjusting module is used for: the first target impedance is controlled by the input voltage, and is subjected to secondary regulation under the action of the input voltage so as to obtain a second target impedance;

the inverter delay module is used for: and adjusting the output frequency under the control of the second target impedance.

Optionally, the adjusting module includes a plurality of adjusting units, the switching module includes a plurality of switching units, the inverter delay module includes a plurality of inverter delay units, and the number of the reference voltage terminals is a plurality; the control ends of the regulating units are connected with the first end of the first capacitor and the input voltage end, the first end of each regulating unit is connected with the power voltage end and the second end of the first capacitor, and the second end of each regulating unit is connected with the first end of a corresponding switch unit respectively; the control end of each switch unit is respectively connected with a reference voltage end so as to be controlled by an independent reference voltage end; the plurality of inverter delay units are sequentially connected in series, the output end of the former inverter delay unit is connected with the input end of the latter inverter delay unit, and the output end of the last inverter delay unit is connected with the input end of the first inverter delay unit; the control ends of all inverter delay units are connected to the first end of the second capacitor, and the second ends of all switch units are connected to the first end of the second capacitor.

Optionally, the switch module includes a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a fifth switch unit; the adjusting module comprises a first adjusting unit, a second adjusting unit, a third adjusting unit, a fourth adjusting unit and a fifth adjusting unit; the inverter delay module comprises a first inverter delay unit, a second inverter delay unit, a third inverter delay unit, a fourth inverter delay unit and a fifth inverter delay unit;

the control ends of the first adjusting unit to the fifth adjusting unit are connected to the input voltage end and the first end of the first capacitor, the first ends of the first adjusting unit to the fifth adjusting unit are connected to the power voltage end and the second end of the first capacitor, the second ends of the first adjusting unit to the fifth adjusting unit are connected to the first ends of the first switching unit to the fifth switching unit, the control ends of the first switching unit to the fifth switching unit are connected to the first reference voltage end, the second reference voltage end, the third reference voltage end, the fourth reference voltage end and the fifth reference voltage end, the second ends of the first switching unit to the fifth switching unit are connected to the power ends of the first inverter delay unit to the fifth inverter delay unit and the second capacitor, the first inverter delay unit to the fifth inverter delay unit are in loop connection, and the output end of the fifth inverter is the frequency delay end.

Optionally, the inverter delay unit includes: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the voltage-controlled capacitor;

the control ends of the first MOS tube and the fifth MOS tube are connected to a voltage input end, the first end of the first MOS tube is connected with a power end, the second end of the first MOS tube is connected with the first end of the second MOS tube, the second end of the second MOS tube is connected with the first end of the third MOS tube, the second end of the third MOS tube is connected with the first end of the fourth MOS tube, the second end of the fourth MOS tube is connected with the first end of the fifth MOS tube, the second end of the fifth MOS tube is grounded, the second end of the second MOS tube is also connected with the first end of the fifth MOS tube, the second end of the fifth MOS tube is connected with the first end of the voltage-controlled capacitor, and the second end of the voltage-controlled capacitor is connected with the power end.

Optionally, the first to fifth MOS transistors include NMOS transistors or PMOS transistors.

According to a second aspect of the present utility model, there is provided a phase locked loop comprising the ring oscillator of the first aspect and optionally the phase frequency detector, a charge pump, a switching loop filter, a first frequency divider, a second frequency divider, a bias current generation module;

The output end of the charge pump is connected with the output end of the switch loop filter, the output end of the switch loop filter is connected with the input end of the first frequency divider and the input end of the second frequency divider, the output end of the first frequency divider is connected with the second input end of the bias current generation module, the output end of the bias current generation module is connected with the second input end of the charge pump, and the output end of the second frequency divider is connected with the second input end of the phase detector;

the phase frequency detector is used for: detecting a phase difference between a reference signal output by the reference signal end and a feedback signal output by the second frequency divider, and converting the phase difference into a voltage pulse width; to output a pulse signal to the charge pump;

the charge pump is used for: charging or discharging the switch loop filter according to the pulse signal so as to control the control voltage of the ring oscillator;

The switching loop filter is used for: filtering high-frequency noise generated in the phase frequency detector and outputting an output voltage to the ring oscillator;

the ring oscillator is used for: adjusting the output frequency according to the output voltage;

the first frequency divider and the second frequency divider are configured to: dividing the output frequency, and configuring the output frequency by adjusting the frequency dividing ratio;

the bias current generation module is used for: and generating a current signal according to the control reference signal and the output frequency and transmitting the current signal to the charge pump.

Optionally, the phase frequency detector is configured to:

when the phase difference is larger than a first threshold value, the phase frequency detector outputs a first pulse signal;

when the phase difference is smaller than a second threshold value, the phase frequency detector outputs a second pulse signal;

when the phase difference is between the first threshold value and the second threshold value, the phase frequency detector outputs no pulse signal.

Optionally, the charge pump includes: the current replication unit, the third capacitor, the fourth capacitor, the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the first T switch and the second T switch;

The input end of the current replication is connected with the output end of the bias current generation module, the output end of the current replication unit is connected with the third capacitor and the fourth capacitor, the first end of the third capacitor is connected with the first PMOS tube and the grid electrode of the second PMOS tube, the second end of the third capacitor is connected with the first end of the first T switch, the second end of the first T switch is connected with the source electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with the first end of the second T switch, and the second end of the second T switch is grounded;

the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are configured to:

when the input signal is the first pulse signal, the first PMOS tube and the second PMOS tube are conducted;

when the input signal is the second pulse signal, the first NMOS tube and the second NMOS tube are conducted;

the first T-switch and the second T-switch are configured to:

When the input signal is the first pulse signal, the third PMOS tube and the fourth PMOS tube in the first T switch are turned on, the fifth PMOS tube is turned off, the third NMOS tube and the fourth NMOS tube in the second switch are turned off, and the fifth NMOS tube is turned on;

when the input signal is the second pulse signal, the third PMOS tube and the fourth PMOS tube in the first T are turned off, the fifth PMOS tube is turned on, the third NMOS tube and the fourth NMOS tube in the second switch are turned on, and the fifth NMOS tube is turned off.

Optionally, the first T switch includes: the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube; the source electrode of the third PMOS tube is connected with the output voltage end, the drain electrode of the third PMOS tube is connected with the source electrodes of the fourth PMOS tube and the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the source electrode of the first PMOS tube, and the drain electrode of the fifth PMOS tube is grounded;

the input signals of the control ends of the third PMOS tube and the fourth PMOS tube are configured to be inverse signals of the first pulse; and the input signal of the control end of the fifth PMOS tube is configured as the first pulse signal.

Optionally, the second T switch includes: the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube; the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrodes of the fourth NMOS tube and the fifth NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the source electrode of the fifth NMOS tube is connected with the output voltage end;

The input signals of the control ends of the third NMOS tube and the fourth NMOS tube are configured to be the second pulse; the input signal of the control end of the fifth NMOS tube is configured as the inverse signal of the second pulse signal.

Optionally, the bias current generating module includes: a data selector and a bias current generator; the input end of the data selector is respectively connected with the first frequency divider and the reference signal end, the output end of the data selector is connected with the input end of the bias current generator, and the output end of the bias current generator is connected with the charge pump so as to output bias current.

Optionally, the bias current generator includes: the device comprises an adjustable resistor, a first resistor, an amplifier, a first filter, a second filter, a sixth MOS tube, a seventh MOS tube, a fifth capacitor, a sixth capacitor, a seventh capacitor, a switch unit and a trigger;

the output voltage ends are all connected to the first end of the first resistor, the first end of the first filter, the first end of the second filter, the first end of the sixth MOS tube, the first end of the seventh MOS tube, the second end of the first resistor is connected with the first end of the adjustable resistor and the inverting input end of the amplifier, the second end of the adjustable resistor is grounded, the non-inverting input end of the amplifier is connected with the first end of the switching unit, the output end of the amplifier is connected with the second end of the second filter, the third end of the second filter is connected with the control end of the seventh MOS tube, the second end of the seventh MOS tube is connected with the second end of the switching unit and the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the grid electrode of the seventh MOS tube is also connected with the second end of the first filter, the third end of the first filter is connected with the control end of the sixth tube, the third end of the fourth filter is connected with the switching unit, the third end of the seventh MOS tube is connected with the third end of the switching unit, the seventh end of the switching unit is grounded, the seventh end of the switching unit is connected with the eighth end of the switching unit is grounded, and the output end of the seventh MOS unit is connected with the eighth end of the switching unit.

Optionally, the switch unit comprises a first switch, a second switch, a third switch and a fourth switch,

the first end of the first switch is connected with the fifth capacitor and the first end of the fourth switch, the second end of the first switch is connected with the first end of the second switch and the sixth capacitor, the second end of the second switch is grounded, the second end of the fourth switch is connected with the first end of the third switch and the seventh capacitor, the second end of the third switch is grounded, the control end of the third switch is connected with the control end of the first switch and the first end of the data selector, and the control end of the second switch is connected with the control end of the fourth switch and the second end of the data selector.

Optionally, the sixth MOS transistor and the seventh MOS transistor each include an NMOS transistor or a PMOS transistor.

According to the ring oscillator provided by the utility model, the first-stage adjustment of the output resistor and the second-stage adjustment of the voltage-controlled capacitor are performed through the switch module and the adjusting module, so that the adjusting range of the output frequency is enlarged.

According to the phase-locked loop, the adjusting range of the output frequency of the phase-locked loop is enlarged through the ring oscillator, and the performance of phase noise of the phase-locked loop is improved.

In the preferred embodiment, the utility model adopts the bias current generating module and the charge pump, and adds the T switch in the charge pump, and the subthreshold leakage is reduced by the on or off of the T switch, so that the power consumption of the phase-locked loop is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the utility model, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.

Fig. 1 is a schematic diagram of a prior art phase locked loop of the present utility model;

FIG. 2 is a schematic diagram of a ring oscillator according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a ring oscillator according to an embodiment of the present utility model;

FIG. 4 is a schematic diagram of an inverter delay unit in a ring oscillator according to an embodiment of the utility model;

FIG. 5 is a schematic diagram of a phase locked loop according to an embodiment of the present utility model;

FIG. 6 is a schematic diagram of a charge pump in a PLL according to an embodiment of the present utility model;

fig. 7 is a schematic diagram of a bias current generation module in a phase locked loop according to an embodiment of the utility model.

Reference numerals illustrate:

101-an adjustment module;

1011-a first adjusting unit;

1012-a second adjustment unit;

1013-a third adjustment unit;

1014-a fourth adjustment unit;

1015-a fifth adjustment unit;

102-a switch module;

1021-a first switching unit;

1022-a second switching unit;

1023-a third switching unit;

1024-fourth switching units;

1025-a fifth switching unit;

103-an inverter delay module;

1031-a first inverter delay unit;

1032-a second inverter delay unit;

1033-a third inverter delay unit;

1034-fourth inverter delay units;

1035-a fifth inverter delay unit;

104-a first capacitance;

105-a second capacitance;

m1-a first MOS tube;

m2-a second MOS tube;

m3-a third MOS tube;

m4-a fourth MOS tube;

m5-a fifth MOS tube;

C _L -a voltage controlled capacitance;

2-phase frequency detector;

3-a charge pump;

301-a current replication unit;

302-a third capacitance;

303-fourth capacitance;

304-a first T-switch;

305-a second T-switch;

PM 1-a first PMOS tube;

PM 2-a second PMOS tube;

PM 3-third PMOS tube;

PM 4-fourth PMOS tube;

PM 5-fifth PMOS tube;

NM 1-a first NMOS tube;

NM 2-second NMOS tube;

NM 3-third NMOS tube;

NM 4-fourth NMOS tube;

NM 5-fifth NMOS tube;

a 4-switch loop filter;

5-a first frequency divider;

6-a second frequency divider;

7-a bias current generation module;

701-a first resistor;

702-an adjustable resistor;

703-an amplifier;

704-a first filter;

705-a second filter;

706-a fifth capacitance;

707-sixth capacitance;

708-seventh capacitance;

709-a first switch;

710-a second switch;

711-third switch;

712-fourth switch;

713-flip-flop;

m6-a sixth MOS tube;

m7-seventh MOS pipe.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The technical scheme of the utility model is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Before the present utility model was put forward, the applicant has made a thorough study on an oscillator and a phase-locked loop, and based on the study, put forward the phase-locked loop shown in fig. 1, for the phase-locked loop shown in fig. 1, comprising: the circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider; the output end of the phase frequency detector is connected with the input end of the charge pump, the output end of the charge pump is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the first end of the frequency divider, the second end of the frequency divider is connected with the input end of the phase frequency detector, and the output end of the voltage-controlled oscillator is also used for outputting frequency.

In the above scheme, since the existing voltage-controlled oscillator has only the voltage adjustment option, the output frequency of the voltage-controlled oscillator is changed by the voltage value, so that the frequency modulation range is reduced, and the bandwidth of the phase-locked loop is further affected.

In view of this, the present utility model provides a ring oscillator and a phase-locked loop, which can change the output frequency of the ring oscillator by controlling the magnitude of the current by using the ring oscillator and the bias current generating module, thereby increasing the bandwidth and reducing the power consumption of the phase-locked loop.

The scheme of the utility model is specifically described as follows:

referring to fig. 2, the present utility model provides a ring oscillator, which includes an inverter delay module 103, a regulating module 101, a switch module 102, a first capacitor 104 and a second capacitor 105;

the control end of the adjusting module 101 is connected to the first end of the first capacitor 104 and an input voltage end, where the input voltage end is used to output an input voltage to adjust the on-resistance of the adjusting module 101; a first end of the adjusting module 101 is connected with a power supply voltage end and a second end of the first capacitor 104, and a second end of the adjusting module 101 is connected with a first end of the switch module 102; the control end of the switch module 102 is connected with a reference voltage end, and the reference voltage end is used for inputting a reference voltage to drive the switch module 102; the second end of the switch module 102 is connected to the first end of the inverter delay module 103, so as to output an output current to the inverter delay module 103; a second end of the inverter delay module 103 is connected to a first end of the second capacitor 105, and a second end of the second capacitor 105 is grounded; the inverter delay module 103 includes a frequency output terminal for outputting an output frequency;

The switch module 102 is configured to: the target impedance of the adjusting module 101 is adjusted at one stage by being controlled by the reference voltage to be turned on or turned off, so as to obtain a first target impedance;

the adjusting module 101 is configured to: the first target impedance is controlled by the input voltage, and is subjected to secondary regulation under the action of the input voltage so as to obtain a second target impedance; and based on the first target impedance and the second target impedance

The inverter delay module 103 is configured to: and adjusting the output frequency under the control of the second target impedance.

In the above scheme, the first-stage adjustment and the second-stage adjustment, that is, coarse adjustment and fine adjustment, of the output current increase the adjustment range of the output frequency through the switch module 102 and the adjustment module 101.

With respect to the adjusting module 101, in a preferred implementation, please refer to fig. 3, the adjusting module 101 includes a plurality of adjusting units, the switching module 102 includes a plurality of switching units, the inverter delay module 103 includes a plurality of inverter delay units, and the number of the reference voltage terminals is a plurality; the plurality of regulating units are connected in parallel, the control end of each regulating unit is connected with the first end of the first capacitor 104 and the input voltage end, the first end of each regulating unit is connected with the power voltage end and the second end of the first capacitor 104, and the second end of each regulating unit is respectively connected with the first end of a corresponding switch unit; the control end of each switch unit is respectively connected with a reference voltage end so as to be controlled by an independent reference voltage end; the plurality of inverter delay units are sequentially connected in series, the output end of the former inverter delay unit is connected with the input end of the latter inverter delay unit, and the output end of the last inverter delay unit is connected with the input end of the first inverter delay unit; the control terminals of all inverter delay cells are connected to the first terminal of the second capacitor 105 and the second terminals of all switch cells are connected to the first terminal of the second capacitor 105.

With respect to the switch module 102, in a preferred embodiment, please continue to refer to fig. 3, the switch module 102 includes a first switch unit 1021, a second switch unit 1022, a third switch unit 1023, a fourth switch unit 1024, and a fifth switch unit 1025; the adjusting module 101 includes a first adjusting unit 1011, a second adjusting unit 1012, a third adjusting unit 1013, a fourth adjusting unit 1014, and a fifth adjusting unit 1015; the inverter delay module 103 includes a first inverter delay unit 1031, a second inverter delay unit 1032, a third inverter delay unit 1033, a fourth inverter delay unit 1034, and a fifth inverter delay unit 1035;

the control terminals of the first adjusting unit 1011 to the fifth adjusting unit 1015 are all connected to the input voltage terminal and the first terminal of the first capacitor 104, the first terminals of the first adjusting unit 1011 to the fifth adjusting unit 1015 are all connected to the power voltage terminal and the second terminal of the first capacitor 104, the second terminals of the first adjusting unit 1011 to the fifth adjusting unit 1015 are all connected to the first terminals of the first switching unit 1021 to the fifth switching unit 1025, the control terminals of the first switching unit 1021 to the fifth switching unit 1025 are all connected to a first reference voltage terminal, a second reference voltage terminal, a third reference voltage terminal, a fourth reference voltage terminal and a fifth reference voltage terminal, the second terminals of the first switching unit 1021 to the fifth switching unit 1025 are all connected to the power terminals of the first inverter delay unit 1031 to the fifth inverter delay unit 1035 and the second capacitor 105, the first switching unit 1021 to the fifth switching unit 1031 is connected to the fifth inverter delay unit 1035, and the output terminal is the output circuit 1035.

With respect to the inverting delay unit, in a preferred embodiment, referring to fig. 4, the inverter delay unit includes: first MOS tube M1, second MOS tube M2, third MOS tube M3, fourth MOS tube M4, fifth MOS tube M5 and voltage-controlled capacitor C _L ；

The control ends of the first MOS tube M1 to the fifth MOS tube M5 are all connected to a voltage input end, the first end of the first MOS tube M1 is connected to a power end, the second end of the first MOS tube M1 is connected to the first end of the second MOS tube M2, the second end of the second MOS tube M2 is connected to the first end of the third MOS tube M3, the second end of the third MOS tube M3 is connected to the first end of the fourth MOS tube M4, the second end of the fourth MOS tube M4 is connected to the first end of the fifth MOS tube M5, the second end of the fifth MOS tube M5 is grounded, the second end of the second MOS tube M2 is also connected to the first end of the fifth MOS tube M5, and the second end of the fifth MOS tube M5 is connected to the voltage-controlled capacitor C _L Is the first end of the voltage-controlled capacitor C _L Is connected to the power supply terminal.

In one example, the first to fifth MOS transistors M1 to M5 include NMOS transistors or PMOS transistors.

In a specific embodiment, the ring oscillator receives VCTL (i.e., input voltage) output by the low-pass filter to adjust the output frequency, and 2^5 =32 frequency modulation ranges are achieved by controlling on or off (primary adjustment) of the first switch unit to the fifth switch unit and impedance (secondary adjustment) of the first adjustment unit to the fifth adjustment unit; and a voltage-controlled capacitor and a MOS switch are connected to each inverter delay unit, so that the output rate adjustment range and the KVCO adjustment range of the ring oscillator are increased, and the ring oscillator has good noise performance.

Referring to fig. 5, the present utility model further provides a phase-locked loop, which includes the ring oscillator, the phase frequency detector 2, the charge pump 3, the switching loop filter 4, the first frequency divider 5, the second frequency divider 6, and the bias current generating module 7;

the first input end of the phase frequency detector 2 is connected with a reference signal end and the first input end of the bias current generation module 7, the output end of the phase frequency detector 2 is connected with the first input end of the charge pump 3, the output end of the charge pump 3 is connected with the output end of the switch loop filter 4, the output end of the switch loop filter 4 is connected with the input end of the first frequency divider 5 and the input end of the second frequency divider 6, the output end of the first frequency divider 5 is connected with the second input end of the bias current generation module 7, the output end of the bias current generation module 7 is connected with the second input end of the charge pump 3, and the output end of the second frequency divider 6 is connected with the second input end of the phase frequency detector 2;

the phase frequency detector 2 is used for: detecting a phase difference between a reference signal output by the reference signal end and a feedback signal output by the second frequency divider 6, and converting the phase difference into a voltage difference; to output a pulse signal to the charge pump 3;

The charge pump 3 is configured to: charging or discharging the switching loop filter 4 according to the pulse signal to control a control voltage of the ring oscillator;

the switching loop filter 4 is configured to: filtering high-frequency noise generated in the phase frequency detector 2 and outputting an output voltage to the ring oscillator;

the first frequency divider 5 and the second frequency divider 6 are configured to: dividing the output frequency, and configuring the output frequency by adjusting the frequency dividing ratio;

the bias current generation module 7 is configured to: based on the control reference signal and the output frequency, a current signal is generated and fed to the charge pump 3.

In one embodiment, the frequency division of the first frequency divider 5 is M, the frequency division of the second frequency divider 6 is N, and by adjusting the frequency division ratio, outputs with different frequencies can be obtained.

In the scheme, the ring oscillator increases the adjusting range of the output frequency of the phase-locked loop and improves the performance of phase noise of the phase-locked loop.

Regarding the phase frequency detector 2, in a preferred embodiment, the phase frequency detector 2 is configured to:

When the phase difference is greater than a first threshold value, the phase frequency detector 2 outputs a first pulse signal;

when the phase difference is smaller than a second threshold value, the phase frequency detector 2 outputs a second pulse signal;

when the phase difference is between the first threshold value and the second threshold value, the phase frequency detector 2 outputs no pulse signal.

In a specific embodiment, please continue to refer to fig. 5, a first input end of the phase frequency detector 2 receives the reference signal (fref) output by the reference signal end, a second input end of the phase frequency detector 2 receives the feedback signal (fbak) generated by the second frequency divider 6, the phase difference between the two signals (i.e. the reference signal and the feedback signal) is detected by the phase frequency detector 2, and then the phase difference is changed into a voltage output; specifically, the UP pulse UP (i.e., the first pulse signal) has an output signal when the phase of the reference signal leads, and the down pulse DN (i.e., the second pulse signal) has an output signal when the phase of the feedback signal leads.

Referring to fig. 6 for the charge pump 3, the charge pump 3 includes: the current replication unit 301, the third capacitor 302, the fourth capacitor 303, the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, the second NMOS transistor NM2, the first T-switch 304, and the second T-switch 305;

The input end of the current replication is connected to the output end of the bias current generating module 7, the output end of the current replication unit 301 is connected to the third capacitor 302 and the fourth capacitor 303, the first end of the third capacitor 302 is connected to the first PMOS pipe PM1 and the gate of the second PMOS pipe PM2, the second end of the third capacitor 302 is connected to the first end of the first T switch 304, the second end of the first T switch 304 is connected to the source of the first PMOS pipe PM1, the drain of the first PMOS pipe PM1 is connected to the source of the second PMOS pipe PM2, the drain of the second PMOS pipe PM2 is connected to the drain of the first NMOS pipe NM1, the source of the first NMOS pipe NM1 is connected to the drain of the second NMOS pipe NM2, the source of the second NMOS pipe NM2 is connected to the first end of the second T switch 305, and the second end of the second T switch 305 is grounded;

the first PMOS pipe PM1, the second PMOS pipe PM2, the first NMOS pipe NM1, and the second NMOS pipe NM2 are configured to:

when a reference voltage is input to the charge pump enabling end, the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are conducted;

when the charge pump is enabled to be grounded, the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are turned off, and the charge pump does not work;

The first T-switch 304 and the second T-switch 305 are configured to:

when the input signal is the first pulse signal, the first T switch 304 is turned off, and the second switch 710 is turned on;

when the input signal is the second pulse signal, the first T switch 304 is turned on, and the second switch 710 is turned off.

With respect to the T-switch, in a preferred embodiment, please continue to refer to fig. 6, the first T-switch 304 includes: the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5; the source electrode of the third PMOS tube PM3 is connected with an output voltage end, the drain electrode of the third PMOS tube PM3 is connected with the source electrodes of the fourth PMOS tube PM4 and the fifth PMOS tube PM5, the drain electrode of the fourth PMOS tube PM4 is connected with the source electrode of the first PMOS tube PM1, and the drain electrode of the fifth PMOS tube PM5 is grounded;

the input signals of the control ends of the third PMOS tube PM3 and the fourth PMOS tube PM4 are configured as inverse signals of the first pulse; the input signal of the control end of the fifth PMOS PM5 is configured as the first pulse signal.

In other preferred embodiments, the second T-switch 305 includes: a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5; the drain electrode of the third NMOS transistor NM3 is connected to the source electrode of the second NMOS transistor NM2, the source electrode of the third NMOS transistor NM3 is connected to the drain electrodes of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5, the source electrode of the fourth NMOS transistor NM4 is grounded, and the source electrode of the fifth NMOS transistor NM5 is connected to the output voltage terminal;

The input signals of the control ends of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are configured as the second pulse; the input signal of the control end of the fifth NMOS transistor NM5 is configured as an inverse signal of the second pulse signal.

In a specific embodiment, when the charge pump 3 detects an UP signal (i.e., a first pulse signal), the third PMOS tube PM3 and the fourth PMOS tube PM4 of the charge pump 3 are turned on, and the current charges the capacitor on the filter through the first PMOS tube PM1 and the second PMOS tube PM2, so as to increase the control voltage of the oscillator, thereby increasing the oscillation frequency of the oscillator to increase the phase; when the charge pump 3 detects the DN signal (i.e., the second pulse signal), the current discharges the capacitor through the third NMOS transistor NM3 and the fourth NMOS transistor NM4, and gradually decreases the control voltage of the oscillator, thereby decreasing the frequency of the oscillator and reducing the phase difference value.

Specifically, a T switch is added to the charge pump 3 to reduce subthreshold leakage, and the control end of the first T switch 304 is obtained by inverting an UP signal (i.e., a first pulse signal), so that when the UP signal (i.e., the first pulse signal) exists, the first T switch 304 is turned off, and the function of the charge pump 3 is not affected; when the UP signal (i.e., the first pulse signal) disappears, the first T switch 304 is turned on to connect the ground to the circuit, so that no voltage difference exists in other tubes, no sub-threshold leakage is caused, and the power is further reduced.

In the scheme, the bias current generating module 7 and the charge pump 3 are adopted, and the T switch is added in the charge pump 3, so that subthreshold leakage is reduced through the connection or disconnection of the T switch, and the power consumption of the phase-locked loop is further reduced.

Regarding the bias current generating module 7, in a preferred embodiment, the bias current generating module 7 comprises: a data selector and a bias current generator; the input end of the data selector is respectively connected with the first frequency divider 5 and the reference signal end, the output end of the data selector is connected with the input end of the bias current generator, and the output end of the bias current generator is connected with the charge pump 3 so as to output bias current.

In another preferred embodiment, referring to fig. 7, the bias current generator includes: the adjustable resistor 702, the first resistor 701, the amplifier 703, the first filter 704, the second filter 705, the sixth MOS transistor M6, the seventh MOS transistor M7, the fifth capacitor 706, the sixth capacitor 707, the seventh capacitor 708, the switch unit and the trigger 713;

the output voltage terminals are all connected to the first terminal of the first resistor 701, the first terminal of the first filter 704, the first terminal of the second filter 705, the first terminal of the sixth MOS transistor M6, the first terminal of the seventh MOS transistor M7, the second terminal of the first resistor 701 is connected to the first terminal of the adjustable resistor 702 and the inverting input terminal of the amplifier 703, the second terminal of the adjustable resistor 702 is grounded, the non-inverting input terminal of the amplifier 703 is connected to the first terminal of the switching unit, the output terminal of the amplifier 703 is connected to the second terminal of the second filter 705, the third terminal of the second filter 705 is connected to the control terminal of the seventh MOS transistor M7, the second terminal of the seventh MOS transistor M7 is connected to the second terminal of the switching unit and the third terminal of the fifth capacitor 706, the second terminal of the fifth capacitor 706 is grounded, the gate of the seventh MOS transistor M7 is also connected to the first terminal of the adjustable resistor 702 is grounded, the non-inverting input terminal of the amplifier 703 is connected to the first terminal of the switching unit, the output terminal of the fifth transistor M is connected to the third terminal of the switching unit, the third terminal of the seventh MOS transistor M7 is connected to the third terminal of the switching unit, the third terminal of the fifth capacitor M7 is connected to the third terminal of the switching unit, the third terminal of the switching unit is connected to the fifth terminal of the switching unit, and the output terminal of the switching unit is connected to the output terminal of the switching unit.

In other preferred embodiments, please continue to refer to fig. 7, the switch unit includes a first switch 709, a second switch 710, a third switch 711, and a fourth switch 712;

the first end of the first switch 709 is connected to the fifth capacitor 706 and the first end of the fourth switch 712, the second end of the first switch 709 is connected to the first end of the second switch 710 and the sixth capacitor 707, the second end of the second switch 710 is grounded, the second end of the fourth switch 712 is connected to the first end of the third switch 711 and the seventh capacitor 708, the second end of the third switch 711 is grounded, the control end of the third switch 711 is connected to the control end of the first switch 709 and the first end of the data selector, and the control end of the second switch 710 is connected to the control end of the fourth switch 712 and the second end of the data selector.

In an example, the sixth MOS transistor M6 and the seventh MOS transistor M7 each include an NMOS transistor or a PMOS transistor.

In a specific embodiment, the data selector selects a frequency and then generates a current I through the bias current generator _REF ，I _REF =vref×2cxxfp, wherein VREF is the input voltage adjusted by the adjustable resistor 702 and the first resistor 701, 2Cx is the sixth capacitor 707 and the seventh capacitor 708, f is the frequency selected by the data selector, and P is the mirror ratio of the sixth MOS transistor M6 to the seventh MOS transistor M7.

Specifically, the obtained reference current Iref is different due to the different frequencies selected by the data selector; in the fixed mode, iref is proportional only to the reference signal (i.e., fref); in the adaptive mode, iref is proportional to fref N/M.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims

1. The ring oscillator is characterized by comprising an inverter delay module, an adjusting module, a switch module, a first capacitor and a second capacitor;

the control end of the adjusting module is connected with the first end of the first capacitor and an input voltage end, and the input voltage end is used for inputting an input voltage to adjust the on-resistance of the adjusting module; the first end of the adjusting module is connected with the power supply voltage end and the second end of the first capacitor, and the second end of the adjusting module is connected with the first end of the switch module; the control end of the switch module is connected with a reference voltage end, and the reference voltage end is used for inputting a reference voltage to drive the switch module; the second end of the switch module is connected with the first end of the inverter delay module so as to output an output current to the inverter delay module; the second end of the inverter delay module is connected with the first end of the second capacitor, and the second end of the second capacitor is grounded; the inverter delay module comprises a frequency output end and a delay module, wherein the frequency output end is used for outputting an output frequency;

2. The ring oscillator of claim 1, wherein the regulation module comprises a number of regulation units, the switching module comprises a number of switching units, the inverter delay module comprises a number of inverter delay units, and the number of reference voltage terminals is a number; the control ends of the regulating units are connected with the first end of the first capacitor and the input voltage end, the first end of each regulating unit is connected with the power voltage end and the second end of the first capacitor, and the second end of each regulating unit is connected with the first end of a corresponding switch unit respectively; the control end of each switch unit is respectively connected with a reference voltage end so as to be controlled by an independent reference voltage end; the plurality of inverter delay units are sequentially connected in series, the output end of the former inverter delay unit is connected with the input end of the latter inverter delay unit, and the output end of the last inverter delay unit is connected with the input end of the first inverter delay unit; the control ends of all inverter delay units are connected to the first end of the second capacitor, and the second ends of all switch units are connected to the first end of the second capacitor.

3. The ring oscillator of claim 1, wherein the switching module comprises a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, and a fifth switching unit; the adjusting module comprises a first adjusting unit, a second adjusting unit, a third adjusting unit, a fourth adjusting unit and a fifth adjusting unit; the inverter delay module comprises a first inverter delay unit, a second inverter delay unit, a third inverter delay unit, a fourth inverter delay unit and a fifth inverter delay unit;

4. A ring oscillator as claimed in claim 3, wherein the inverter delay unit comprises: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the voltage-controlled capacitor;

5. The ring oscillator of claim 4, wherein the first to fifth MOS transistors comprise NMOS or PMOS transistors.

6. A phase locked loop comprising the ring oscillator of any one of claims 1-5, and a phase frequency detector, a charge pump, a switching loop filter, a first frequency divider, a second frequency divider, and a bias current generation module;

the bias current generation module is used for: and generating a current signal according to the reference signal and the output frequency and transmitting the current signal to the charge pump.

7. The phase locked loop of claim 6, wherein the phase frequency detector is configured to:

8. The phase locked loop of claim 7, wherein the charge pump comprises: the current replication unit, the third capacitor, the fourth capacitor, the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the first T switch and the second T switch;

when a reference voltage is input to the charge pump enabling end, the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are conducted, and when the charge pump enabling end is grounded, the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube are turned off, and the charge pump does not work;

The first T-switch and the second T-switch are configured to:

when the input signal is the first pulse signal, a third PMOS tube and a fourth PMOS tube in the first T switch are turned on, a fifth PMOS tube is turned off, a third NMOS tube and a fourth NMOS tube in the second T switch are turned off, and the fifth NMOS tube is turned on;

when the input signal is the second pulse signal, the third PMOS tube and the fourth PMOS tube in the first T switch are turned off, the fifth PMOS tube is turned on, the third NMOS tube and the fourth NMOS tube in the second T switch are turned on, and the fifth NMOS tube is turned off.

9. The phase-locked loop of claim 8, wherein the first T-switch comprises: the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube; the source electrode of the third PMOS tube is connected with the output voltage end, the drain electrode of the third PMOS tube is connected with the source electrodes of the fourth PMOS tube and the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the source electrode of the first PMOS tube, and the drain electrode of the fifth PMOS tube is grounded;

10. The phase-locked loop of claim 8, wherein the second T-switch comprises: the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube; the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrodes of the fourth NMOS tube and the fifth NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the source electrode of the fifth NMOS tube is connected with the output voltage end;

11. The phase locked loop of claim 8, wherein the bias current generation module comprises: a data selector and a bias current generator; the input end of the data selector is respectively connected with the first frequency divider and the reference signal end, the output end of the data selector is connected with the input end of the bias current generator, and the output end of the bias current generator is connected with the charge pump so as to output bias current.

12. The phase locked loop of claim 11, wherein the bias current generator comprises: the device comprises an adjustable resistor, a first resistor, an amplifier, a first filter, a second filter, a sixth MOS tube, a seventh MOS tube, a fifth capacitor, a sixth capacitor, a seventh capacitor, a switch unit and a trigger;

13. The phase locked loop of claim 12, wherein the switching unit comprises a first switch, a second switch, a third switch, and a fourth switch;

14. The phase-locked loop of claim 12, wherein the sixth MOS transistor and the seventh MOS transistor each comprise an NMOS transistor or a PMOS transistor.