CN100458639C - Device and method for compensating MOS device grid leakage current - Google Patents

Abstract

The invention discloses a device and method for compensating gate leakage current of a MOS device, comprising: mirror circuit to output mirror voltage to a feedback control unit to generate mirror current, where the proportion of gate leakage current to mirror current is a mirror proportion parameter; compensation current unit to generate regulating current and compensation current to compensate the gate leakage current by the control of the control current outputted by a feedback control unit, where the proportion of compensation current to regulating current is a mirror proportion parameter; feedback control unit to respectively receive input voltage reference and mirror voltage coming from the junction of the mirror circuit and the compensation current unit and output control voltage to the compensation current unit according to the voltage reference and the mirror voltage, and regulate the regulating current of the compensation current unit according to the mirror current to make the regulating current equal to the mirror current.

Description

Device and method for compensating MOS device grid leakage current

Technical Field

The invention relates to the technology of analog integrated circuits, in particular to a device and a method for compensating grid leakage current of a deep submicron MOS device.

Background

A Phase Locked Loop (PLL) is a feedback control system, in which the frequency of an output signal tracks the frequency of an input signal, and when the frequency of the output signal and the frequency of the input signal are fixed multiples, a fixed Phase difference is maintained between an output voltage and the input voltage, so the PLL is called a Phase Locked loop, which is called a Phase Locked loop for short.

A functional block diagram of the PLL circuit is shown in fig. 1, and mainly includes three parts, namely, a Phase comparator (PD) or a Phase frequency comparator (PFD), a Loop Filter (LF), and a Voltage Controlled Oscillator (VCO). In a PLL circuit requiring a relatively low phase locking speed, a phase difference between an input signal and a feedback signal is detected by a PD, and the phase difference is converted into a voltage signal u_D(t), referred to as error voltage; in a PLL circuit with high phase locking speed requirement, phase difference and frequency difference between an input signal and a feedback signal are detected by adopting a PFD (pulse frequency detector), and phase information can be reflected by the frequency information, so that the aim of quickly locking can be fulfilled by adopting the PFD, and the phase difference can be quickly converted into an error voltage u_D(t); thus, a PD or PFD is a phase difference-to-voltage conversion circuit. LF generally employs a Low Pass Filter (LPF) for filtering out high frequency components and interference signals in the error voltage output by PD or PFD, and outputting a stable voltage u_C(t), referred to as the filter voltage. The VCO is capable of converting the filtered voltage output by the LPF into an output signal having a frequency proportional to the voltage value thereof, and thus the VCO is a voltage-frequency conversion circuit whose oscillation frequency is determined by the filtered voltage; the VCO is capable of outputting a square wave, which is generally used to generate an ideal clock, so there is a high requirement for the stability of the input filtered voltage. The output signal of VCO becomes the above-mentioned feedback signal through a 1/K frequency divider, loopback to PD or PFD input end, form the feedback loop, the frequency divider makes the frequency of the feedback signal 1/K of the output signal frequency of VCO, finally, make the output signal frequency of PLL K times of the input signal frequency, the phase difference of keeping fixed phase place between input voltage and the output voltage, achieve the goal of phase locking.

FIG. 2 shows a conventional PLL circuit, which is mainly composed of three parts, PD or PFD, LPF and VCOThe sub-components, whether PD or PFD, are used, depend on the phase-locking speed requirements of the circuitry for which the PLL is specifically applied. The PD or PFD is used for detecting the phase difference of the input signal and the feedback signal and converting the phase difference into an error voltage; the error voltage output by PD or PFD removes high frequency component and interference signal by LPF to obtain stable filtering voltage V_ctl(ii) a Filtered voltage V output by LPF_ctlFor controlling VCO to generate ideal clock, the output signal of VCO is fed back to the input end of PD or PFD by means of a 1/K frequency divider to form feedback loop, and VCO is used for inputting V_ctlThe stability of (2) has higher requirements. The LPF consists of a resistor R and two N-channel MOS (NMOS) tubes M1 and M2, wherein M1 and M2 are used as the capacitor of the LPF. The MOS tube can be divided into a thin gate MOS tube and a thick gate MOS tube, and the thin gate MOS tube has larger capacitance per unit area. In the conventional PLL circuit, the areas of M1 and M2 are much larger than those of other parts, which directly determine the area and system consumption of the PLL circuit, and in order to reduce the circuit area and system consumption, the LPF generally uses thin gate MOS transistors.

As integrated circuit technology advances, the feature sizes of circuits and devices become smaller and smaller. Generally, an integrated circuit having a feature size of 0.8 to 0.35 μm is called a submicron level, an integrated circuit having a feature size of 0.25 μm or less is called a deep submicron level, and an integrated circuit having a feature size of 0.05 μm or less is called a nanoscale. At present, the mainstream production technology of integrated circuits in the world reaches the deep submicron level. In deep submicron, the gate of the MOS transistor has leakage current due to tunneling effect, and the leakage current affects the filtering voltage V of the input VCO in the PLL circuit_ctlThe stability of the PLL circuit, and thus the jitter (jitter), significantly affects the operating state of the PLL circuit.

The prior art solution is to select a thick gate MOS transistor as the capacitor of the LPF, and to reduce the leakage current by thickening the gate. The gate thickness of the thick-gate MOS tube is 2-3 times of that of the thin-gate MOS tube generally, and in order to obtain the same-size capacitance, the area of the thick-gate MOS tube needs to be increased to 2-3 times of that of the thin-gate MOS tube. Since the area of the MOS tube directly determines the circuit area and the system consumption, the circuit area and the system consumption are greatly increased, and the compensation precision of the scheme is not ideal and deviates from the development trend of miniaturization of integrated circuits.

Disclosure of Invention

The invention provides a device and a method for compensating grid leakage current of a deep submicron MOS device, which are used for solving the problem that the grid leakage current of the MOS device is compensated by using larger circuit area and system consumption in the prior art and improving the compensation precision.

The invention provides a device for compensating gate leakage current of a MOS device, which comprises: a mirror circuit, a compensation current unit, and a feedback control unit, wherein,

the mirror image circuit is used for outputting mirror image voltage to the feedback control unit to generate mirror image current, and the proportion of compensated grid leakage current and the mirror image current is called as mirror image proportion parameter;

the compensation current unit is used for generating an adjustment current and a compensation current for compensating the grid leakage current according to the control of the control voltage output by the feedback control unit, and the proportion of the compensation current and the adjustment current is a mirror image proportion parameter;

the feedback control unit is used for respectively receiving an input reference voltage and a mirror image voltage from a connection point of the mirror image circuit and the compensation current unit, outputting a control voltage to the compensation current unit according to the reference voltage and the mirror image voltage, and adjusting the adjustment current of the compensation current unit according to the mirror image current to enable the adjustment current to be equal to the mirror image current.

The device further comprises a compensated circuit, which is used for outputting the reference voltage to a feedback control unit and receiving the compensation current.

The circuit structure of the mirror image circuit corresponds to the compensated circuit, each element is a mirror image element of the corresponding element of the compensated circuit, and the ratio of the characteristic parameters of the mirror image element to the characteristic parameters of the corresponding element of the compensated circuit is a mirror image proportion parameter or the reciprocal of the mirror image proportion parameter.

The mirror image circuit comprises two N-channel MOS tubes and a resistor, the area ratio of the two N-channel MOS tubes to the two corresponding N-channel MOS tubes in the compensated circuit is the reciprocal of a mirror image proportion parameter, and the resistance ratio of the resistor to the corresponding resistor in the compensated circuit is the mirror image proportion parameter.

The compensation current unit includes:

and the two voltage-controlled current sources are simultaneously controlled by the control voltage output by the feedback control unit, one voltage-controlled current source is used for generating the adjusting current input to the mirror circuit, and the other voltage-controlled current source is used for providing the compensating current.

The two voltage-controlled current sources are implemented by two P-channel MOS tubes, the lengths of the channels of the two P-channel MOS tubes are the same, and the ratio of the channel width of the MOS tube for outputting the compensation current to the channel width of the MOS tube for outputting the adjustment current is a mirror image proportion parameter.

The feedback control unit is implemented by an operational amplifier, wherein the reference voltage is used as an input of a negative input terminal, and the mirror voltage is used as an input of a positive input terminal.

The invention provides a method for compensating gate leakage current of an MOS device, which comprises the following steps:

after the circuit is electrified, the compensated circuit generates grid leakage current, the mirror circuit generates mirror current, and the proportion of the grid leakage current and the mirror current is a mirror proportion parameter;

the feedback control unit takes the output voltage of the compensated circuit as the input reference voltage, takes the voltage of the connection point of the mirror circuit and the compensation current unit as the input mirror voltage, outputs a control voltage according to the reference voltage and the mirror voltage, controls the compensation current unit to generate the compensation current input to the compensated circuit and the adjustment current input to the mirror circuit, and adjusts the adjustment current according to the mirror current so that the adjustment current is equal to the mirror current, wherein the proportion of the compensation current and the adjustment current is a mirror proportion parameter.

The adjusting the adjustment current according to the mirror current includes:

when the feedback control unit determines that the adjustment current is larger than the mirror current, the mirror voltage is pulled to a low level to turn off the compensation current unit, the adjustment current is rapidly reduced, and when the adjustment current is smaller than the mirror current, the mirror voltage is pulled to a high level to rapidly increase the adjustment current,

when the adjusting current is larger than the mirror current, repeating the adjusting process until the adjusting current is equal to the mirror current;

or,

the feedback control unit pulls the image voltage to a high level to rapidly increase the adjustment current when determining that the adjustment current is smaller than the image current, pulls the image voltage to a low level to turn off the compensation current unit and rapidly decrease the adjustment current when the adjustment current is larger than the image current,

and when the adjusting current is smaller than the mirror current, repeating the adjusting process until the adjusting current is equal to the mirror current.

The proportion of the grid leakage current and the mirror image current is a mirror image proportion parameter, and the grid leakage current and the mirror image current are realized by setting circuit parameters of a compensated circuit and a mirror image circuit.

The compensation current unit comprises two voltage-controlled current sources, the proportion of the compensation current and the adjustment current is a mirror ratio parameter, and the compensation current unit is realized by setting circuit parameters of the two voltage-controlled current sources.

Compared with the prior art, the invention has the following beneficial effects:

1. the grid leakage current compensation device is arranged to realize the compensation of the grid leakage current of the MOS device, the circuit areas of the feedback control unit and the compensation current unit can be basically ignored, and the circuit area of the mirror image circuit is a determining factor of the circuit area of the grid leakage current compensation device, so that the increased circuit area is greatly reduced compared with the prior scheme, the compensation of the grid leakage current of the MOS device is realized by using smaller system cost, and the system consumption is greatly saved.

2. The scheme provided by the invention has the system compensation precision of more than 99 percent, stabilizes the output voltage of a compensated circuit, reduces the jitter (jitter) of a PLL circuit under the deep submicron condition, and improves the working state of the PLL circuit.

3. The invention has wider application range, and can be applied to products using PLL circuits under the process that the line width is lower than 0.13 mu m; meanwhile, the method is a generally applicable method for compensating the gate leakage current of the MOS device under the deep submicron condition.

Drawings

FIG. 1 is a functional block diagram of a PLL;

FIG. 2 is a schematic diagram of a conventional PLL;

FIG. 3 is a schematic diagram illustrating a gate leakage compensation device according to an embodiment;

FIG. 4 is a circuit diagram of a second gate leakage compensation device according to an embodiment;

FIG. 5 is a circuit diagram of an exemplary tri-gate leakage current compensation device.

Detailed Description

In deep submicron, the circuit with the MOS tube can generate grid leakage current which influences the stability of the output voltage of the circuit.

Example one

Referring to fig. 3, a schematic diagram of a structure of a gate leakage current compensation device according to an embodiment of the present invention mainly includes: the circuit comprises a mirror circuit, a compensation current unit and a feedback control unit.

The mirror circuit is used for outputting mirror voltage to the feedback control unit to generate mirror current, the proportion of the grid leakage current of the compensated circuit and the mirror current is called as mirror proportion parameter, and the determined mirror proportion parameter can be obtained by setting the circuit parameters of the compensated circuit and the mirror circuit; the structure of the mirror image circuit corresponds to the compensated circuit to form a mirror image thereof;

the compensation current unit is a unit which is controlled by input control voltage to output stable current and comprises two voltage-controlled current sources, wherein one voltage-controlled current source is used for providing compensation current of grid leakage current for a compensated circuit, and the other voltage-controlled current source generates adjustment current; the compensation current and the adjustment current are controlled by the same input voltage, and the proportion of the compensation current and the adjustment current is a mirror image proportion parameter; the circuit parameters of the two voltage-controlled current sources are set, so that the proportion of the compensation current and the adjustment current is the mirror ratio parameter.

And the feedback control unit is used for taking the output voltage from the compensated circuit as an input reference voltage, taking the voltage from a connection point of the mirror circuit and the compensation current unit as an input mirror voltage, outputting a control voltage to the compensation current unit according to the reference voltage and the mirror voltage, and adjusting the adjustment current of the compensation current unit according to the mirror current so that the adjustment current is equal to the mirror current.

The working principle of the MOS device grid leakage current compensation device comprises the following steps:

101. after the circuit is electrified, the compensated circuit generates grid leakage current, the mirror image circuit generates mirror image current, and the grid leakage current and the mirror image current are proportional to each other to form mirror image proportion parameters by setting circuit parameters of the compensated circuit and the mirror image circuit;

102. the voltage output by the compensated circuit is used as a reference voltage input into the feedback control unit, the voltage of a connection point of the mirror circuit and the compensation current unit is used as a mirror voltage input into the feedback control unit, and the feedback control unit outputs a control voltage according to the reference voltage and the mirror voltage;

103. the compensation current unit generates two currents under the control of the control voltage output by the feedback control unit, wherein one current is the compensation current input to the compensated circuit, the other current is the adjustment current input to the mirror image circuit, and the compensation current and the adjustment current are in proportion to be a mirror image proportion parameter by setting the circuit parameter of the compensation current unit;

104. under the action of the feedback control unit, the adjusting current is adjusted according to the mirror current, and the specific adjusting process is as follows:

when the feedback control unit determines that the adjusting current is larger than the mirror current, the mirror voltage is pulled to a low level, the compensating current unit is turned off, the adjusting current is rapidly reduced, when the adjusting current is smaller than the mirror current, the mirror voltage is pulled to a high level, the adjusting current is rapidly increased, and when the adjusting current is larger than the mirror current, the adjusting process is repeated; repeating the steps until a stable state is reached, namely adjusting the current to be equal to the mirror current and adjusting the reference voltage to be equal to the mirror voltage;

or,

when the feedback control unit determines that the adjusting current is smaller than the mirror current, the mirror voltage is pulled to a high level to enable the adjusting current to be increased rapidly, when the adjusting current is larger than the mirror current, the mirror voltage is pulled to a low level to enable the compensating current unit to be turned off, the adjusting current is decreased rapidly, and when the adjusting current is smaller than the mirror current, the adjusting process is repeated; repeating the steps until a stable state is reached, namely adjusting the current to be equal to the mirror current and adjusting the reference voltage to be equal to the mirror voltage;

105. after the circuit is stabilized, the adjusting current is equal to the mirror image current, and the proportion of the grid leakage current and the mirror image current is a mirror image proportion parameter, and the proportion of the compensating current and the adjusting current is a mirror image proportion parameter, so that the compensating current is equal to the grid leakage current, the purpose of compensating the grid leakage current is realized, and the output voltage of the compensated circuit also reaches a stable state.

Example two

Referring to fig. 4, a circuit diagram of a gate leakage compensation device of a MOS device applied to a PLL circuit according to an embodiment of the present invention is shown.

In the figure, the PD or PFD, the VCO, the LPF and the 1/K frequency divider are all part of a conventional PLL circuit. The LPF consists of a resistor R and NMOS transistors M1 and M2, and M1 and M2 are thin gate MOS transistors with large unit area capacitance. Filtered voltage V output by LPF_ctlIs the input voltage of the VCO. Under the condition of deep submicron, the MOS transistor may generate gate leakage current due to the tunneling effect, and this leakage current may affect the stability of the filtering voltage in the PLL circuit, and bring about large jitter (jitter), thereby seriously affecting the operating state of the PLL circuit.

In this embodiment, the compensated circuit is the LPF, and a gate leakage current compensation circuit of an MOS device is added in the dashed line frame to compensate the gate leakage current of the MOS device in the LPF, so as to achieve a stable V_ctlThe object of (1), the circuit comprising: the LPF comprises a mirror image circuit, a feedback control unit and two voltage-controlled current sources. The selection and connection of the various devices is illustrated as follows:

the mirror image circuit of the LPF consists of two NMOS tubes Mc1 and Mc2 and a resistor Rc, and the connection mode corresponds to the LPF; mc1 is a mirror image of M1, with an area of 1/N of M1, and N is a mirror scale parameter, typically between 5 and 10, although the range of N is not so limited; mc2 is a mirror image of M2, with an area of 1/N of M2; rc is a mirror image of R and has a resistance N times that of R; the mirror image circuit is used for outputting mirror image voltage to the feedback control unit to generate mirror image current, and the ratio of grid leakage current generated by the LPF to the mirror image current is N;

two voltage-controlled current sources I1 and I2 for outputting a stable current under the control of an input control voltage, I1 for generating an adjustment current, and I2 for supplying a compensation current of a gate leakage current to the LPF; under the same control voltage, the output current of I2 is N times of I1;

a feedback control unit for outputting the filtered voltage V from the LPF_ctlA reference voltage as an input; the voltage V from the connection point of the mirror circuit and the I1_mirrorAs an input mirror voltage, a control voltage V is output to two voltage-controlled current sources according to a reference voltage and the mirror voltage_c. And adjusting the adjusting current generated by I1 according to the mirror current to make the adjusting current equal to the mirror current.

Based on the design of the compensation circuit, the invention realizes the compensation of the gate leakage current of the MOS device in the deep submicron PLL, and the working principle of the specific compensation process comprises the following steps:

201. after the circuit is powered on, the grid leakage current of M1 in the LPF is I_leak1The gate leakage current of M2 is I_leak2The gate leakage current of the LPF is I_leak＝I_leak1+I_leak2；

202. In the mirror circuit, the gate leakage current of Mc1 is I_mc1The gate leakage current of Mc2 is I_mc2Mc1 is a mirror image of M1 and has an area of 1/N of M1, so I_mc1Is I_leak1The mirror current of (a) is, $I_{\mathrm{mcl}}=\frac{1}{N}{I}_{\mathrm{leak}1};$ mc2 is a mirror image of M2 and has an area of 1/N of M2, and the same principle is that $I_{\mathrm{mc}2}=\frac{1}{N}{I}_{\mathrm{leak}2},$ Then the mirror current of the mirror circuit $I_{\mathrm{mirror}}=I_{\mathrm{<figure-callout\; id="1"\; label="mc"\; filenames="C20071006457000171.png,C20071006457000172.png"\; state="\{\{state\}\}">mc</figure-callout>}1}+I_{\mathrm{mc}2}=\frac{1}{N}{I}_{\mathrm{leak}};$

203. The filtered voltage V output by LPF_ctlAs a reference voltage input to the feedback control unit, the voltage V of the connection point of the mirror circuit and I1_mirrorAs a mirror voltage input to the feedback control unit, the feedback control unit outputs a control voltage V based on the reference voltage and the mirror voltage_c；

204. The voltage-controlled current sources I1 and I2 output control voltage V at the feedback control unit_cThe current output by I1 is I₁Referred to as the regulated current, the current output of I2 is I₂Called compensation current, by setting circuit parameters of two voltage-controlled current sources₂＝N·I₁；

205. Under the action of a feedback control unit according to I_mirrorTo I₁And (3) adjusting, wherein the specific adjusting process is as follows:

when the feedback control unit determines I₁＞I_mirrorWhen it is, V will be_mirrorPulled to a low level V_ddLet I1 be turned off, resulting in I₁Rapidly decreases; when I is₁＜I_mirrorThen, V is put_mirrorIs pulled to a high level V_ssSo that a large current is generated at I1, resulting in I₁Rapidly increase;

when I is₁＞I_mirrorThen, repeating the above adjusting process; so the contraryUntil a steady state is reached, i.e. I₁＝I_mirror，V_mirror＝V_ctl；

Or,

when the feedback control unit determines I₁＜I_mirrorWhen it is, V will be_mirrorIs pulled to a high level V_ssSo that a large current is generated at I1, resulting in I₁Rapidly increase; when I is₁＞I_mirrorThen, V is put_mirrorPulled to a low level V_ddLet I1 be turned off, resulting in I₁Rapidly decreases;

when I is₁＜I_mirrorThen, repeating the above adjusting process; repeating the above steps until a steady state is reached, i.e. I₁＝I_mirror，V_mirror＝V_ctl；

206. After circuit stabilization I₁＝I_mirrorAnd due to $I_{\mathrm{mirror}}=\frac{1}{N}{I}_{\mathrm{lesk}},$ I₂＝N·I₁Therefore I is₂＝I_leakThe purpose of compensating the grid leakage current of the LPF is achieved, and the filtering voltage output by the LPF is stabilized.

The circuit compensates the grid leakage current of the LPF by using the compensation current output by the voltage-controlled current source I2, achieves the aim of stabilizing the voltage output by the LPF, reduces the jitter (jitter) of the PLL under the deep submicron condition and improves the working state of the PLL.

EXAMPLE III

Fig. 5 shows another specific embodiment of the gate leakage compensation circuit of the MOS device in the deep submicron PLL, which is a specific implementation manner of the second embodiment, wherein the feedback control unit is implemented by an Operational Amplifier (OPAMP), and the voltage-controlled current source is implemented by a P-channel MOS (pmos) transistor. In this embodiment, the compensated circuit is an LPF, and the MOS device gate leakage current compensation circuit includes: the mirror image of the LPF, two PMOS transistors P1 and P2, an OPAMP. The selection and connection of the devices is illustrated as follows:

the mirror image circuit of the LPF consists of two NMOS tubes Mc1 and Mc2 and a resistor Rc, and the connection mode corresponds to the LPF; mc1 is a mirror image of M1, the area is 1/N of M1, and N is a mirror image proportion parameter; mc2 is a mirror image of M2, with an area of 1/N of M2; rc is a mirror image of R and has a resistance N times that of R; the mirror image circuit is used for outputting mirror image voltage to the positive input end of the OPAMP to generate mirror image current, and the ratio of the grid leakage current to the mirror image current is N;

two PMOS tubes P1 and P2 for outputting current under the control of the inputted control voltage, P1 for generating adjustment current, P2 for outputting compensation current to LPF; the channel length of P1 is the same as that of P2, the channel width of P2 is N times of P1, and the output current of P2 is N times of P1 under the control of the same control voltage;

OPAMP for filtering the filtered voltage V from the LPF output_ctlAs a reference voltage for the negative input; the voltage V from the connection point of the mirror circuit and P1_mirrorAs the mirror voltage of the positive input end, a control voltage V is output to the two PMOS tubes according to the reference voltage and the mirror voltage_c. The adjustment current generated by P1 is adjusted for the mirror current so that the adjustment current is equal to the mirror current.

Based on the design of the compensation circuit, the working principle of the specific compensation process comprises the following steps:

301. after the circuit is powered on, the grid leakage current of M1 in the LPF is I_leak1The gate leakage current of M2 is I_leak2The gate leakage current of the LPF is I_leak＝I_leak1+I_leak2；

302. In the mirror circuit, the gate leakage current of Mc1 is I_mc1The gate leakage current of Mc2 is I_mc2Mc1 is a mirror image of M1, having an area of 1/N of M1,so I_mc1Is I_leak1The mirror current of (a) is, $I_{\mathrm{<figure-callout\; id="1"\; label="mc"\; filenames="C20071006457000171.png,C20071006457000172.png"\; state="\{\{state\}\}">mc</figure-callout>}1}=\frac{1}{N}{I}_{\mathrm{leak}1};$ mc2 is a mirror image of M2 and has an area of 1/N of M2, and the same principle is that $I_{\mathrm{mc}2}=\frac{1}{N}{I}_{\mathrm{leak}2},$ The mirror current of the mirror circuit is $I_{\mathrm{mirror}}=I_{\mathrm{<figure-callout\; id="1"\; label="mc"\; filenames="C20071006457000171.png,C20071006457000172.png"\; state="\{\{state\}\}">mc</figure-callout>}1}+I_{\mathrm{mc}2}=\frac{1}{N}{I}_{\mathrm{leak}};$

303. The filtered voltage V output by LPF_ctlAs a reference voltage to the negative input terminal of OPAMP, a voltage V at the junction of the mirror circuit and P1_mirrorAs a mirror voltage input to the positive input terminal of the OPAMP, the OPAMP outputs a control voltage V for controlling the two PMOS transistors according to the reference voltage and the mirror voltage_c；

304. Control voltage V of PMOS transistors P1 and P2 at OPAMP output_cThe current output by P1 is I_p1Called regulated current, P2 outputThe output current is I_p2The channel length of P1 is set to be the same as that of P2, the channel width of P2 is N times of P1, so that the characteristics of MOS transistor show that I is controlled by the same voltage_p2Is I_p1N times of (I)_p2＝N·I_p1；

305. Under the action of OPAMP, according to I_mirrorTo I_p1And (3) adjusting, wherein the specific adjusting process is as follows:

when OPAMP determines I_p1＞I_mirrorWhen it is, V will be_mirrorPulled to a low level V_ddLet P1 be turned off, resulting in I_p1Rapidly decreases; when I is_p1＜I_mirrorThen, V is put_mirrorIs pulled to a high level V_ssSo that a large current is generated on P1, resulting in I_p1Rapidly increase;

when I is_p1＞I_mirrorThen, repeating the above adjusting process; repeating the above steps until a steady state is reached, i.e. I_p1＝I_mirror，V_mirror＝V_ctl；

Or,

when OPAMP determines I_p1＜I_mirrorWhen it is, V will be_mirrorIs pulled to a high level V_ssSo that a large current is generated on P1, resulting in I_p1Rapidly increase; when I is_p1＞I_mirrorThen, V is put_mirrorPulled to a low level V_ddLet P1 be turned off, resulting in I_p1Rapidly decreases;

when I is_p1＜I_mirrorThen, repeating the above adjusting process; repeating the above steps until a steady state is reached, i.e. I_p1＝I_mirror，V_mirror＝V_ctl；

306. After circuit stabilization I_p1＝I_mirrorAnd due to $I_{\mathrm{mirror}}=\frac{1}{N}{I}_{\mathrm{lesk}},$ I^p2＝N·I_p1Therefore I is_p2＝I_leakThe purpose of compensating the grid leakage current of the LPF is achieved, and the voltage output by the LPF is stabilized.

The circuit compensates the grid leakage current of the LPF by the compensation current output by the PMOS tube P2, achieves the aim of stabilizing the filtering voltage output by the LPF, reduces the jitter (jitter) of the PLL of deep submicron level, and improves the working state of the PLL.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (11)

1. An apparatus for compensating for gate leakage current in a MOS device, the apparatus comprising: a mirror circuit, a compensation current unit, and a feedback control unit, wherein,

the mirror image circuit is used for outputting mirror image voltage to the feedback control unit to generate mirror image current, and the proportion of compensated grid leakage current and the mirror image current is called as mirror image proportion parameter;

the compensation current unit is used for generating an adjustment current and a compensation current for compensating the grid leakage current according to the control of the control voltage output by the feedback control unit, and the proportion of the compensation current and the adjustment current is a mirror image proportion parameter;

the feedback control unit is used for respectively receiving an input reference voltage and a mirror image voltage from a connection point of the mirror image circuit and the compensation current unit, outputting a control voltage to the compensation current unit according to the reference voltage and the mirror image voltage, and adjusting the adjustment current of the compensation current unit according to the mirror image current to enable the adjustment current to be equal to the mirror image current.

2. The apparatus of claim 1, further comprising a compensated circuit to output the reference voltage to a feedback control unit to receive the compensation current.

3. The apparatus of claim 2, wherein the circuit configuration of the mirror circuit corresponds to the compensated circuit, each element is a mirror element of a corresponding element of the compensated circuit, and a ratio of a mirror element characteristic to a corresponding element characteristic of the compensated circuit is a mirror scale parameter or an inverse of the mirror scale parameter.

4. The apparatus of claim 3, wherein the mirror circuit comprises two N-channel MOS transistors and a resistor, the area ratio of the two N-channel MOS transistors to the two corresponding N-channel MOS transistors in the compensated circuit is the inverse of the mirror ratio parameter, and the ratio of the resistance value of the resistor to the corresponding resistor in the compensated circuit is the mirror ratio parameter.

5. The apparatus of claim 1, the compensation current unit comprising:

and the two voltage-controlled current sources are simultaneously controlled by the control voltage output by the feedback control unit, one voltage-controlled current source is used for generating the adjusting current input to the mirror circuit, and the other voltage-controlled current source is used for providing the compensating current.

6. The apparatus of claim 5, wherein the two voltage-controlled current sources are two P-channel MOS transistors, the channel lengths of the two P-channel MOS transistors are the same, and the channel width of the MOS transistor for outputting the compensation current is proportional to the channel width of the MOS transistor for outputting the adjustment current as a mirror ratio parameter.

7. The apparatus of any of claims 1 to 6, wherein the feedback control unit is an operational amplifier having the reference voltage as an input to a negative input terminal and the mirror voltage as an input to a positive input terminal.

8. A method for compensating gate leakage current of a MOS device is characterized by comprising the following steps:

after the circuit is electrified, the compensated circuit generates grid leakage current, the mirror circuit generates mirror current, and the proportion of the grid leakage current and the mirror current is a mirror proportion parameter;

the feedback control unit takes the output voltage of the compensated circuit as the input reference voltage, takes the voltage of the connection point of the mirror circuit and the compensation current unit as the input mirror voltage, outputs a control voltage according to the reference voltage and the mirror voltage, controls the compensation current unit to generate the compensation current input to the compensated circuit and the adjustment current input to the mirror circuit, and adjusts the adjustment current according to the mirror current so that the adjustment current is equal to the mirror current, wherein the proportion of the compensation current and the adjustment current is a mirror proportion parameter.

9. The method of claim 8, wherein adjusting the adjustment current based on the mirror current comprises:

when the feedback control unit determines that the adjustment current is larger than the mirror current, the mirror voltage is pulled to a low level to turn off the compensation current unit, the adjustment current is rapidly reduced, and when the adjustment current is smaller than the mirror current, the mirror voltage is pulled to a high level to rapidly increase the adjustment current,

when the adjusting current is larger than the mirror current, repeating the adjusting process until the adjusting current is equal to the mirror current;

or,

the feedback control unit pulls the image voltage to a high level to rapidly increase the adjustment current when determining that the adjustment current is smaller than the image current, pulls the image voltage to a low level to turn off the compensation current unit and rapidly decrease the adjustment current when the adjustment current is larger than the image current,

and when the adjusting current is smaller than the mirror current, repeating the adjusting process until the adjusting current is equal to the mirror current.

10. The method of claim 8 or 9, wherein the gate leakage current is proportional to the mirror current as a mirror ratio parameter by setting circuit parameters of the compensated circuit and the mirror circuit.

11. The method of claim 8 or 9, wherein the compensation current unit comprises two voltage controlled current sources, the compensation current is proportional to the adjustment current as a mirror ratio parameter, and the compensation current is proportional to the adjustment current by setting circuit parameters of the two voltage controlled current sources.

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