WO2004111596A3 - Interface pour bus seriels et procede d'interconnexion serielle de dispositifs numeriques a duree critique - Google Patents
Interface pour bus seriels et procede d'interconnexion serielle de dispositifs numeriques a duree critique Download PDFInfo
- Publication number
- WO2004111596A3 WO2004111596A3 PCT/EP2004/050633 EP2004050633W WO2004111596A3 WO 2004111596 A3 WO2004111596 A3 WO 2004111596A3 EP 2004050633 W EP2004050633 W EP 2004050633W WO 2004111596 A3 WO2004111596 A3 WO 2004111596A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- response
- slave
- master
- time
- gets
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002529132A CA2529132A1 (fr) | 2003-06-13 | 2004-04-28 | Interface pour bus seriels et procede d'interconnexion serielle de dispositifs numeriques a duree critique |
JP2006516103A JP2006527549A (ja) | 2003-06-13 | 2004-04-28 | 時間依存型デジタル装置を直列に相互接続するためのシリアル・バス・インターフェースおよび方法 |
EP04729898A EP1636706A2 (fr) | 2003-06-13 | 2004-04-28 | Interface pour bus seriels et procede d'interconnexion serielle de dispositifs numeriques a duree critique |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03013287.2 | 2003-06-13 | ||
EP03013287 | 2003-06-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004111596A2 WO2004111596A2 (fr) | 2004-12-23 |
WO2004111596A3 true WO2004111596A3 (fr) | 2005-12-01 |
Family
ID=33547587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2004/050633 WO2004111596A2 (fr) | 2003-06-13 | 2004-04-28 | Interface pour bus seriels et procede d'interconnexion serielle de dispositifs numeriques a duree critique |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1636706A2 (fr) |
JP (1) | JP2006527549A (fr) |
CN (1) | CN100527102C (fr) |
CA (1) | CA2529132A1 (fr) |
WO (1) | WO2004111596A2 (fr) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2147532B1 (fr) * | 2007-05-08 | 2011-05-04 | Qualcomm Incorporated | Structure de paquet pour interface numérique à affichage mobile |
US8356331B2 (en) * | 2007-05-08 | 2013-01-15 | Qualcomm Incorporated | Packet structure for a mobile display digital interface |
US8031626B2 (en) | 2007-11-13 | 2011-10-04 | Qualcomm Incorporated | Packet structure for a mobile display digital interface |
JP5231533B2 (ja) * | 2008-05-06 | 2013-07-10 | クゥアルコム・インコーポレイテッド | モバイル・ディスプレイ・ディジタル・インターフェース用パケット構造 |
JP5220501B2 (ja) * | 2008-07-15 | 2013-06-26 | 株式会社日立超エル・エス・アイ・システムズ | シリアル通信方法と双方向シリアル通信システム及び自動販売機 |
JP2011087259A (ja) * | 2009-10-19 | 2011-04-28 | Sony Corp | 通信集中制御システムおよび通信集中制御方法 |
CN102147778B (zh) * | 2010-02-05 | 2013-09-11 | 杭州华三通信技术有限公司 | 基于半双工串行总线的数据传输系统及传输控制方法 |
TWI461922B (zh) * | 2011-05-03 | 2014-11-21 | Ind Tech Res Inst | 主從式全雙工序列傳輸系統及主從式全雙工序列傳輸方法 |
EP2775655B1 (fr) * | 2013-03-08 | 2020-10-28 | Pro Design Electronic GmbH | Procédé de distribution d'un signal d'horloge, système de distribution d'horloge et système électronique comprenant un système de distribution d'horloge |
JP6226370B2 (ja) * | 2013-10-07 | 2017-11-08 | 東洋電機製造株式会社 | 通信装置 |
CN103631226B (zh) * | 2013-11-27 | 2016-02-10 | 晶焱科技股份有限公司 | 串列传输推动方法 |
CN104980186B (zh) * | 2014-04-03 | 2018-05-15 | 奇点新源国际技术开发(北京)有限公司 | 回波干扰消除方法及相关装置 |
EP3217240A1 (fr) * | 2016-03-07 | 2017-09-13 | Aldebaran Robotics | Bus de communication de données pour un robot |
US11030142B2 (en) * | 2017-06-28 | 2021-06-08 | Intel Corporation | Method, apparatus and system for dynamic control of clock signaling on a bus |
CN107734849B (zh) * | 2017-09-18 | 2020-06-16 | 苏州浪潮智能科技有限公司 | 一种布线方法及电路板 |
US20200356511A1 (en) * | 2018-01-23 | 2020-11-12 | Sony Semiconductor Solutions Corporation | Control circuit, communication device, and communication system |
WO2019232482A1 (fr) * | 2018-05-31 | 2019-12-05 | Synaptics Incorporated | Bus de données à faible consommation, à large bande passante et à faible latence |
JP6498827B1 (ja) * | 2018-08-28 | 2019-04-10 | 帝人株式会社 | 通信システム |
JP7187966B2 (ja) * | 2018-10-17 | 2022-12-13 | ヤマハ株式会社 | 信号伝送システム、送信装置及び通信ユニット |
CN110222000B (zh) * | 2019-06-21 | 2021-06-08 | 天津市滨海新区信息技术创新中心 | 一种AXI stream数据帧总线合路装置 |
US20210184454A1 (en) * | 2019-12-13 | 2021-06-17 | Texas Instruments Incorporated | Bandwidth-boosted bidirectional serial bus buffer circuit |
CN114035524A (zh) * | 2021-11-11 | 2022-02-11 | 成都卡诺普机器人技术股份有限公司 | 控制方法和自动控制系统 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6191663B1 (en) * | 1998-12-22 | 2001-02-20 | Intel Corporation | Echo reduction on bit-serial, multi-drop bus |
-
2004
- 2004-04-28 JP JP2006516103A patent/JP2006527549A/ja active Pending
- 2004-04-28 EP EP04729898A patent/EP1636706A2/fr not_active Withdrawn
- 2004-04-28 WO PCT/EP2004/050633 patent/WO2004111596A2/fr active Search and Examination
- 2004-04-28 CA CA002529132A patent/CA2529132A1/fr not_active Abandoned
- 2004-04-29 CN CNB2004100420697A patent/CN100527102C/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6191663B1 (en) * | 1998-12-22 | 2001-02-20 | Intel Corporation | Echo reduction on bit-serial, multi-drop bus |
Also Published As
Publication number | Publication date |
---|---|
WO2004111596A2 (fr) | 2004-12-23 |
CN1573719A (zh) | 2005-02-02 |
CA2529132A1 (fr) | 2004-12-23 |
EP1636706A2 (fr) | 2006-03-22 |
JP2006527549A (ja) | 2006-11-30 |
CN100527102C (zh) | 2009-08-12 |
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