WO2004088621A1 - Verfahren und schaltungsanordnung zur simulation von bei matrixadressierten displays auftretenden pixel- und subpixeldefekten - Google Patents
Verfahren und schaltungsanordnung zur simulation von bei matrixadressierten displays auftretenden pixel- und subpixeldefekten Download PDFInfo
- Publication number
- WO2004088621A1 WO2004088621A1 PCT/EP2004/003097 EP2004003097W WO2004088621A1 WO 2004088621 A1 WO2004088621 A1 WO 2004088621A1 EP 2004003097 W EP2004003097 W EP 2004003097W WO 2004088621 A1 WO2004088621 A1 WO 2004088621A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pixel
- signal
- sub
- pixel defect
- synchronization signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/10—Dealing with defective pixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Definitions
- the invention relates to a method and a circuit arrangement for simulating pixel and sub-pixel defects occurring in matrix-addressed displays.
- the plasma screens are a matrix of small gas discharge areas, three of which each represent a picture element. Such a picture element is called a pixel, the three associated gas discharge areas represent the subpixels.
- the above-mentioned LCD screens are matrix-shaped liquid crystal display devices.
- an image point or pixel is formed by three liquid crystal cells lying next to one another, which represent the colors red, green and blue and are also referred to as subpixels.
- the category of matrix-addressed displays also includes projection display devices that use a matrix of picture elements located in the beam path of a light source, such as, for. B. rear projection screens or video projectors.
- the matrix of picture elements works on the reflection principle such as LCOSs (Liquid Crystal On Silicon) or DiVIDs (Digital Micromirror Device) or on the transmitted light principle such as e.g. B. LCDs (Liquid Crystal Display).
- Display control is applied, which enables a very simple change of the error images on the one hand and a display of the error images independent of the display type.
- Fig. 1 shows a circuit arrangement for generating pixel and / or sub-pixel defects in a control signal for a screen.
- FIG. 2 shows a detail of the circuit arrangement according to FIG. 1
- a video data signal 1 is fed to a video data processing unit 2.
- an RGB signal 10 is generated from the video data signal 1 and, on the other hand, e in a horizontal synchronization signal 9 and a vertical synchronization signal 8.
- the RGB signal 10 generated in the video data processing unit 2 is applied to a screen control circuit via a switching array 5 6 switched through, which is also supplied with the horizontal synchronization signal 9 and the vertical synchronization signal 8 from the video data processing unit 2.
- the screen control circuit 6 in turn controls the screen 7, so that an image that corresponds to the video data signal 1 normally appears on the screen 7.
- a programmable pixel defect simulation unit 3 is used, which is acted upon on the one hand by the horizontal synchronization signal 9 and the vertical synchronization signal 8 from the video data processing unit 2 and on the other hand has a connection to a programming device 4.
- Pixel error data or sub-pixel error data are transferred to the programmable pixel defect simulation unit 3 via the programming device 4, these error data defining on the one hand the type of error and on the other hand the location of the error on the screen surface.
- the programmable pixel defect simulation unit 3 From the addressed pixel error data, the programmable pixel defect simulation unit 3 on the one hand generates an R'-G ' -B ' signal 11, which represents the respective pixel or sub-pixel error, on the other hand, the programmable pixel defect simulation unit 3 generates the horizontal synchronization signal 9 and the like Vertical synchronization signal 8 and the data parts that define the location of the respective error on the screen, a switching signal 18 with which the switching array 5 is acted upon such that the R ' -G ' -B ' signal 11, which the programmable pixel defect simulation unit has also briefly applied to the inputs of the screen control circuit 6 becomes. After the time defined by the pixel error data has elapsed, the programmable pixel data simulation unit 3 switches the switching array 5 back to its initial state, so that the normal RGB signal 10 is switched through again to the screen control circuit 6.
- Pixel defects or sub-pixel defects are defined via the programming device 4 and are then transferred in the form of binary data into a memory 12 of the programmable pixel defect simulation unit 3.
- the binary data contained in the memory 12 contain, on the one hand, information about how the R ' -G ' -B ' signal should look in order to represent the respective pixel defects and, on the other hand, information about where the respective errors should appear on the screen.
- the last-mentioned information that is to say that which relate to the location of the display on the screen, are count values with which a comparator 13 is applied.
- the comparator 13 is also supplied with the counter reading of a counter 14, the counter 14 being set to a defined counter value as a function of the horizontal synchronization signal 9 or the vertical synchronization signal 8. From this defined counter value, the counter 14 counts the clock signals on the horizontal synchronization signal 9 or the vertical synchronization signal 8 synchronized clock generator 15 and offers the counter reading to the comparator 13 for comparison. If the comparator 13 determines the equality between the counter reading of the counter 14 and the count value taken over from the memory 12, the comparator 13 generates at its output a signal which is sent via the switching signal generator 17 to the switching array 5, which is already in connection with FIG 1 is described.
- R'-G ' -B ' data 19 are already present on the pixel defect generator, from which the pixel defect generator 16 generates an R ' -G ' -B ' signal 11.
- this R ' -G'-B' signal 1 is briefly applied to the screen control circuit 6 by means of the switching array 5, which is acted upon by the switching signal generator 17 with a switching signal 18, which generates a corresponding representation on the screen 7.
- the arrangement shown in FIG. 2 is of course only exemplary, in particular the arrangement shown in the example according to FIG. 2 can contain a large number of comparators 13 counters 14 and switching signal generators 17 in order to also easily display pixel or sub-pixel defects that are close together can.
- the programmable pixel defect simulation unit 3 by means of a microprocessor which simulates the functioning of the circuit parts described. However, this does not change the principle of operation.
- the method and the arrangement for the simulation of the pixel or sub-pixel defects regardless of the type of screen used.
- the method and arrangement can be used equally for plasma screens, LCD screens, LCOS and DMD projectors and their respective subspecies, in short all matrix-addressable display types.
- the prerequisite here is that a screen 7 is used to display the pixel or sub-pixel defects, which itself has as few such pixel or sub-pixel defects as possible, since otherwise the image impression to be simulated would be distorted.
- the described arrangement and the described method can also be used in connection with cathode ray picture tubes, so that it is possible to display on a cathode ray picture tube the picture impression that a plasma screen or LCD screen with pixel or sub-pixel defects would provide ,
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Transforming Electric Information Into Light Information (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04722816A EP1636777A1 (de) | 2003-03-29 | 2004-03-24 | Verfahren und schaltungsanordnung zur simulation von bei matrixadressierten displays auftretenden pixel- und subpixeldefekten |
JP2006504832A JP2006523854A (ja) | 2003-03-29 | 2004-03-24 | マトリックス形アドレス指定方式ディスプレイで起こるピクセル欠陥及びサブピクセル欠陥をシミュレーションするための方法と回路構成 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10314268.1 | 2003-03-29 | ||
DE2003114268 DE10314268B3 (de) | 2003-03-29 | 2003-03-29 | Verfahren und Schaltungsanordnung zur Simulation von bei matrixadressierten Displays auftretenden Pixel- und Subpixeldefekten |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004088621A1 true WO2004088621A1 (de) | 2004-10-14 |
Family
ID=32731159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2004/003097 WO2004088621A1 (de) | 2003-03-29 | 2004-03-24 | Verfahren und schaltungsanordnung zur simulation von bei matrixadressierten displays auftretenden pixel- und subpixeldefekten |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1636777A1 (zh) |
JP (1) | JP2006523854A (zh) |
CN (1) | CN100466031C (zh) |
DE (1) | DE10314268B3 (zh) |
WO (1) | WO2004088621A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020208558A1 (en) * | 2019-04-09 | 2020-10-15 | Vuereal Inc. | Repair techniques for micro-led devices and arrays |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06201516A (ja) | 1992-12-25 | 1994-07-19 | Sony Corp | 液晶パネル用疑似欠陥発生装置 |
JPH09257639A (ja) | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | 液晶パネルの欠陥画素検査方法及びその装置 |
US5986697A (en) | 1995-01-03 | 1999-11-16 | Intel Corporation | Method and apparatus for raster calibration |
JP2000111858A (ja) * | 1998-10-06 | 2000-04-21 | Toshiba Corp | 平面表示装置のシミュレーション方法、シミュレーション装置、検査方法、および検査装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3297950B2 (ja) * | 1993-07-13 | 2002-07-02 | シャープ株式会社 | 平面型表示パネル検査装置 |
AU741959B2 (en) * | 1996-12-27 | 2001-12-13 | Suiden Co., Ltd. | Large scale cleaning vehicle |
IT1296643B1 (it) * | 1997-12-16 | 1999-07-14 | Cselt Centro Studi Lab Telecom | Procedimento e apparecchiatura per l'introduzione di distorsioni di riferimento in segnali video. |
-
2003
- 2003-03-29 DE DE2003114268 patent/DE10314268B3/de not_active Expired - Lifetime
-
2004
- 2004-03-24 WO PCT/EP2004/003097 patent/WO2004088621A1/de active Application Filing
- 2004-03-24 CN CNB2004800086967A patent/CN100466031C/zh not_active Expired - Fee Related
- 2004-03-24 JP JP2006504832A patent/JP2006523854A/ja not_active Withdrawn
- 2004-03-24 EP EP04722816A patent/EP1636777A1/de not_active Ceased
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06201516A (ja) | 1992-12-25 | 1994-07-19 | Sony Corp | 液晶パネル用疑似欠陥発生装置 |
US5986697A (en) | 1995-01-03 | 1999-11-16 | Intel Corporation | Method and apparatus for raster calibration |
JPH09257639A (ja) | 1996-03-19 | 1997-10-03 | Fujitsu Ltd | 液晶パネルの欠陥画素検査方法及びその装置 |
JP2000111858A (ja) * | 1998-10-06 | 2000-04-21 | Toshiba Corp | 平面表示装置のシミュレーション方法、シミュレーション装置、検査方法、および検査装置 |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 07 29 September 2000 (2000-09-29) * |
See also references of EP1636777A1 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020208558A1 (en) * | 2019-04-09 | 2020-10-15 | Vuereal Inc. | Repair techniques for micro-led devices and arrays |
Also Published As
Publication number | Publication date |
---|---|
DE10314268B3 (de) | 2004-08-19 |
EP1636777A1 (de) | 2006-03-22 |
CN1795482A (zh) | 2006-06-28 |
CN100466031C (zh) | 2009-03-04 |
JP2006523854A (ja) | 2006-10-19 |
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