WO2004066388A1 - 強誘電体キャパシタおよびその製造方法 - Google Patents
強誘電体キャパシタおよびその製造方法 Download PDFInfo
- Publication number
- WO2004066388A1 WO2004066388A1 PCT/JP2003/000379 JP0300379W WO2004066388A1 WO 2004066388 A1 WO2004066388 A1 WO 2004066388A1 JP 0300379 W JP0300379 W JP 0300379W WO 2004066388 A1 WO2004066388 A1 WO 2004066388A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ferroelectric
- layer
- lower electrode
- capacitor according
- ferroelectric capacitor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Definitions
- the present invention relates to a ferroelectric capacitor mainly used for a nonvolatile memory device and a method for manufacturing the same.
- PZT [P b (Z r x T i ! _ X) O Form 3] is a Berobusukai preparative crystal structure materials having ferroelectric properties and electrical-optical properties, non-volatile memory device having a large spontaneous polarization And electro-optical devices.
- the formation of the ferroelectric thin film has been performed by various film forming methods.
- thin film formation technology can be divided into physical vapor deposition (PVD) technology and chemical processing technology.
- the PVD technology used for forming the ferroelectric thin film includes an electron beam evaporation method, a sputtering method, and a laser abrasion method.
- Chemical processing techniques include chemical solution deposition (CSD) and chemical vapor deposition (CVD).
- P VD technology mainly 1 0- 5 P a film can be formed at a low pressure of less, high purity and high cleaning degree is obtained, has a Ruiu advantage compatibility is obtained between the semiconductor integrated circuit technology, It has disadvantages such as low deposition rate, difficulty in controlling stoichiometric composition, and high temperature annealing after deposition.
- the CSD method has advantages such as uniformity of molecules, high deposition rate, reproducibility of composition, and easy introduction of dopants.However, cracks occur in the film due to heat treatment after deposition, Impurities are not used because There are also problems such as the necessity of changing the starting materials in order to change the composition.
- MOCVD has the advantages of excellent film uniformity and composition controllability, high film density, high deposition rate, and excellent step coverage.
- the step coverage obtained by the MOC VD method cannot be obtained by other methods.
- the composition of the film, for example, PZT can be easily changed by using the same raw material and the flow rate of each raw material.
- Pt is used as the lower electrode, as is often done with ferroelectric capacitors.
- an amorphous layer formed by sputtering or sol-gel method is deposited.
- An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a ferroelectric capacitor having good morphology and formed such that a ferroelectric has a dominant orientation axis.
- the present invention includes a lower electrode layer, a ferroelectric layer on the lower electrode layer, and an upper electrode layer on the ferroelectric layer, wherein the ferroelectric material has a dominant orientation axis on the lower electrode layer.
- the lower electrode layer has a multilayer structure, and the lower electrode layer is made of a ferroelectric constituent element or a compound composed of a constituent element that is larger as the layer is closer to the ferroelectric layer.
- a ferroelectric capacitor having a diffusion coefficient to a lower electrode.
- the ferroelectric capacitor according to the present invention includes the steps of: forming a ferroelectric layer by metal organic chemical vapor deposition; heating the substrate when forming the ferroelectric layer; Yes, including at least one species
- the ferroelectric layer is formed on the lower electrode by flowing the metal raw material, and the constituent elements of the first layer in contact with the ferroelectric layer of the lower electrode and the constituent elements of the ferroelectric layer are changed. It can be manufactured by a method including a step of alloying or compounding.
- FIG. 1 is a cross-sectional SEM image of a PZT film grown on Pt.
- FIG. 2 is a cross-sectional SEM image of the PZT film formed on Ir.
- FIG. 3 is an X-ray diffraction pattern of the PZT film formed on Ir shown in FIG.
- FIG. 4 (a) to 4 (e) are schematic diagrams showing the steps of manufacturing the ferroelectric capacitor of Example 1.
- FIG. 4 (a) to 4 (e) are schematic diagrams showing the steps of manufacturing the ferroelectric capacitor of Example 1.
- FIG. 5 is an XRD pattern of the PZT film of Example 1.
- FIG. 6 is a graph showing the dependence of the amount of polarization on the applied voltage in the PZT film of Example 1.
- FIG. 7 (a) to 7 (f) are schematic diagrams showing the steps of manufacturing the ferroelectric capacitor of Example 2.
- FIG. 7 (a) to 7 (f) are schematic diagrams showing the steps of manufacturing the ferroelectric capacitor of Example 2.
- FIG. 8 is an SEM image of the ferroelectric film of Example 2.
- FIG. 9 is a schematic cross-sectional view of the semiconductor device of the third embodiment.
- 10 (a) to 10 (h) are schematic views showing a manufacturing process of the semiconductor device of the third embodiment.
- the present invention it is necessary to adopt a configuration in which the lattice constant mismatch between the material forming the first layer in contact with the ferroelectric layer of the lower electrode and the material forming the ferroelectric layer is reduced.
- the lattice constant mismatch between the material forming the first layer in contact with the ferroelectric layer of the lower electrode and the material forming the ferroelectric layer is reduced.
- the ferroelectric capacitor according to the present invention comprises a ferroelectric constituent element or a concentration of a compound consisting of a constituent element in the i-th and (i + 1) -th lower electrode layers counted from the ferroelectric layer side.
- ni and ni + 1 respectively, then iii> ni + 1 .
- the first layer in contact with the ferroelectric layer of the lower electrode may be formed of an alloy or a compound containing a ferroelectric constituent element.
- the ferroelectric layer contains, for example, Pb and Ti, or Pb, Zr, and Ti as constituent elements.
- the ferroelectric layer contains, for example, Pb and Ti, or Pb, Zr and Ti as constituent elements, and further comprises La, Ca, Sr, and Nb It contains at least one member selected from the group.
- the ferroelectric layer is made of, for example, a ferroelectric containing Pb and Ti or Pb, Zr and Ti as constituent elements, and has a crystal orientation plane of (111).
- the ferroelectric layer is made of, for example, a ferroelectric containing Pb and Ti, or Pb, Zr, and Ti as constituent elements, and has a crystal orientation plane of (001).
- the thickness of the first layer in contact with the ferroelectric layer of the lower electrode may be, for example, 20 nm or less.
- the first layer in contact with the ferroelectric layer of the lower electrode contains, for example, Pt as a constituent element, and the second lower electrode layer in contact with the first lower electrode layer It contains Ir as a constituent element.
- the ferroelectric layer is made of a perovskite ferroelectric containing Pb, and Pb is formed immediately before the formation of the ferroelectric layer.
- the first lower electrode layer is formed of a compound containing Pb by flowing an organic metal material containing, a carrier gas, and an oxidizing gas, and then a ferroelectric layer is formed.
- the ferroelectric layer is made of, for example, a ferroelectric containing Pb, Zr, and Ti as constituent elements.
- Pb (THD) 2 is used as a Pb raw material
- Z r material as Z r (DMF D) 4 is used
- T i (i P r O ) 2 (THD) 2 as a T i raw material is used.
- a ferroelectric thin film can be formed on this lower electrode so as to have a dominant orientation axis.
- a material having strong self-orientation and a small lattice mismatch with the thin film may be used for the underlayer.
- a thin film is formed into a two-layer structure, and a crystal nucleus called an initial layer or a seed layer is grown as the first layer, and the thin film is grown using the nucleus as a nucleus.
- the process becomes complicated and parameter control during thin film growth becomes difficult, and it is desirable to make the process as simple as possible.
- PZT Pt with small lattice mismatch is often used.
- FIG. 1 shows a cross-sectional SEM image of the PZT film grown on Pt. A reaction layer of Pt and Pb was observed at the interface between PZT and Pt, indicating that the morphology was deteriorated due to the volume expansion of the reaction layer of Pt and Pb.
- FIG. 2 shows a cross-sectional SEM image of the PZT film formed on Ir. No reactant was found at the interface between PZT and Ir, and a good interface was formed. However, as shown in Fig. 3, the orientation is random.
- a Pt layer having a smaller thickness than Ir is deposited on Ir, and a Pb material is first supplied to form a PbPt alloy on Ir.
- Pb supplied on Pt diffuses and reacts with Pt, but the reaction between Ir and Pb is lower than Pt, so the diffusion of Pb is suppressed at the Pt-Ir interface.
- Pb diffuses uniformly in the Pt layer in the horizontal direction with respect to the substrate. This As a result, a uniform PtPb alloy is formed on Ir.
- the thickness of Pt is small and Pb diffuses more evenly, the volume expansion due to alloying is uniform, and no local expansion occurs. Since the PtPb alloy has a smaller lattice mismatch with PZT than Pt, the subsequent PZT layer is significantly influenced by the orientation of PtPb and is significantly oriented.
- a 6-inch Si (100) substrate was used as the substrate.
- a 100 nm thick SiO 2 layer was formed (Fig. 4 (a)).
- An Ir layer was formed thereon with a thickness of 150 nm by sputtering (FIG. 4 (b)).
- T i layer as an adhesion layer between the S i O 2 and I r, may form a T i 0 2 layers.
- a PtPb layer was deposited to a thickness of about 10 nm by a sputtering method using a PtPb alloy target (FIG. 4 (c)).
- Metalorganic vapor phase deposition was used to deposit PZT.
- organometallic materials include Pb (THD) 2 [lead bis (tetramethylheptanedione)], Zr (DMHD) 4 [zirconium dimethyl trakis (dimethylheptadionate)], and Ti (iPr).
- the starting material was a liquid obtained by dissolving these materials in a THF (tetrahydrofuran) solvent at a concentration of 0.3 mol ZL.
- the flow rate of the liquid raw material was controlled by a liquid mass flow controller, and the liquid raw material was introduced into a vaporizer maintained at 260 ° C to be gasified.
- carrier gas N 2
- the gasified organometallic raw material and carrier gas are transferred to the gas It was mixed with oxygen gas in the mixing chamber and introduced into the CVD reaction chamber through the shower head.
- - as a wafer using a P b P t / I r / S i O 2 / S i obtained above.
- the wafer is placed on the susceptor above the heating heater and heated for 240 seconds so that the substrate temperature becomes uniform at 580 ° C.
- the pressure in the reaction chamber was adjusted so as to be 670 Pa in total pressure.
- the flow rate of oxygen gas was 250 sccm.
- the source gas vaporized by the vaporizer was flowed to the exhaust line and was not sent to the CVD reaction chamber.
- the raw material gas is mixed with oxygen gas in the gas mixing chamber, and introduced into the reaction chamber through the glass head.
- Each raw material was adjusted to a ratio of 0.78 in PbZ (Zr + Ti) flow ratio and 0.46 in Zr / (Zr + Ti) flow ratio.
- TH FZ (Pb + Zr + Ti) Flowed at a flow rate of 1.33 and introduced into the vaporizer.
- the valve connecting the vaporizer to the exhaust line is closed, and at the same time, the pulp of the piping from the vaporizer to the gas mixing chamber is opened, and the carrier gas is introduced into the mixing chamber. Meanwhile, oxygen gas was also introduced into the mixing chamber and mixed with the raw material gas.
- the gas mixed in the gas mixing chamber was sent to the deposition chamber maintained at 670 Pa through the shower head, and was deposited on the substrate to a thickness of 120 nm (Fig. 4 (d)).
- the PZT film formed by the above method has a strong (111) orientation as shown in FIG. (111)
- the orientation ratio is 90% or more.
- the X-ray diffraction pattern when PZT is deposited directly on Ir is also shown. Further, as shown in FIG. 6, it has a polarization amount of 60 C / C m 2 or more at an applied voltage of 1.8 V.
- Example 2 A 6-inch Si (100) substrate was used as the substrate.
- An SiO 2 layer having a thickness of 100 nm was formed by thermally oxidizing the Si substrate (FIG. 7 (a)).
- An Ir layer with a thickness of 15 O nm was formed thereon by sputtering (Fig. 7 (b)).
- T i layer as an adhesion layer between the S i O 2 and I r may form a T i 0 2 layers.
- a Pt layer was deposited to a thickness of about 10 nm by sputtering (Fig.
- Metalorganic vapor phase deposition was used to deposit PZT.
- organometallic materials include Pb (DPM) 2 [lead bis (dipipalylmethanate)], Zr (DMHD) 4 [zirconium tetrakis (dimethylheptadionate)], Ti (iPrO) ) 2 (DMP) 2 [titanium (disopropoxy) bis (dipipalloylmethanate)] was used.
- the starting material was a liquid obtained by dissolving these materials in a THF (tetrahydrofuran) solvent at a concentration of 0.3 mol /.
- the flow rate of the liquid raw material was controlled by a liquid mass flow controller, and the liquid raw material was introduced into a vaporizer maintained at 260 ° C. and gasified.
- carrier gas N 2
- the gasified organometallic raw material and carrier gas were mixed with oxygen gas in the gas mixing chamber at the top of the reaction chamber, and introduced into the CVD reaction chamber through the shower head.
- oxygen gas was also introduced into the mixing chamber and mixed with the source gas.
- the gas mixed in the gas mixing chamber was sent to the deposition chamber maintained at 670 Pa through the shower head, and the film was formed on the substrate to a thickness of 120 nm (Fig. 7 ( e))).
- the I r O x was formed with a thickness of about 1 0 0 nm as by Ri upper electrode Supattari ring method to form a capacitor (FIG. 7 (f)).
- the PZT film formed by the above method shows 90% or more (111) orientation as in the case of Example 1.
- FIG. 8 shows a cross-sectional SEM image of the PZT film.
- the Pt layer is thin, the volume expansion due to the reaction between Pt and Pb at the PZT / Pt interface as seen on the thick Pt (see Fig. 1) can be seen. And a good interface state is obtained.
- Example 3
- FIG. 9 is a schematic cross-sectional view showing the structure of a semiconductor device according to this embodiment
- FIG. 10 is a process cross-sectional view showing a method for manufacturing a semiconductor device.
- a memory cell transistor having a gate electrode formed through a gate insulating film and source / drain diffusion layers formed on the silicon substrate on both sides of the gate electrode is formed on the silicon substrate. Is formed.
- An interlayer insulating film is formed on the silicon substrate on which the memory cell transistor is formed.
- a plug electrically connected to the source Z drain diffusion layer is embedded in the interlayer insulating film.
- a bit line electrically connected to the source / drain diffusion layer via a plug is formed on the interlayer insulating film.
- An interlayer insulating film is further formed on the interlayer insulating film on which the bit lines are formed.
- a plug electrically connected to the source Z drain diffusion layer is embedded in the interlayer insulating film.
- a barrier metal and a lower electrode are formed on the interlayer insulating film with the buried plugs.
- Ir is used as the lower electrode, Ir is formed, followed by a PtPb layer or a Pt layer.
- a capacitor dielectric film made of a PZT film is formed on the lower electrode.
- an upper electrode made of P t and I r or I r O x, are formed on the dielectric film.
- a ferroelectric capacitor including the lower electrode, the capacitor dielectric film, and the upper electrode is formed.
- an element separation film is formed on a silicon substrate by, for example, a shear wrench method.
- the gate electrode formed via the gate insulating film and the silicon on both sides of the gate electrode are formed in the same manner as in a normal MOS transistor formation method.
- a memory cell transistor having a source Z drain diffusion layer formed on a substrate is formed (FIG. 10 (a)).
- a silicon oxide film is deposited on the silicon substrate on which the memory cell transistors are formed by, for example, a CVD method, and silicon oxide is deposited.
- An interlayer insulating film made of an oxide film is formed.
- the surface of the interlayer insulating film is polished by, for example, CMP (chemical mechanical polishing), and the surface of the interlayer insulating film is planarized.
- CMP chemical mechanical polishing
- a tungsten (W) film is deposited by a sputtering method, and then polished by a CMP method until the surface of the interlayer insulating film is exposed. This forms a plug that is embedded in the contact hole and electrically connected to the source nodrain diffusion layer.
- the W film is patterned by lithography and etching techniques, and the W film is formed, and the source Z drain diffusion layer is formed through a plug.
- the connected bit lines are formed (Fig. 10 (c)).
- a silicon oxide film is deposited on the interlayer insulating film on which the bit lines are formed, for example, by a CVD method, to form an interlayer insulating film made of the silicon oxide film.
- a W film is deposited by a sputtering method, and then polished by a CMP method until the surface of the interlayer insulating film is exposed.
- a plug is formed which is embedded in the contact hole and electrically connected to the source / drain diffusion layer.
- a paria metal and a lower electrode Ir are formed with a thickness of 150 nm (FIG. 10E).
- organometallic materials include Pb (DPM) 2 [lead bis (dipipalloyl methanate)], Zr (DMHD) 4 [zirconium tetrakis (dimethylheptadionate)], Ti (iPrO ) 2 (DPM)
- a liquid obtained by dissolving these materials in a THF (tetrahydrofuran) solvent at a concentration of 0.3 mol L was used as a starting material.
- the flow rate of the liquid raw material was controlled by a liquid mass flow controller, and introduced into a vaporizer maintained at 260 ° C. to gasify the raw material.
- carrier gas (N 2 ) was simultaneously introduced into the vaporizer at a flow rate of 300 sccm.
- the gasified organometallic raw material and carrier gas were mixed with oxygen gas in a gas mixing chamber at the upper part of the reaction chamber, and introduced into the CVD reaction chamber through a shutter head.
- the source gases Pb, Zr and Ti are mixed with oxygen gas in a gas mixing chamber and introduced into the reaction chamber through a shower head. Adjust each raw material to a ratio of 0.78 in Pb / (Zr + Ti) flow ratio, 0.46 in Zr / (Zr + Ti) flow ratio, and only THF solvent To TH (P b + Zr + Ti) Flowed at a flow rate of 1.33, and introduced into the vaporizer.
- the valve connecting the exhaust line to the vaporizer is closed, and at the same time, the valve of the pipe from the vaporizer to the gas mixing chamber is opened, and the carrier gas is introduced into the mixing chamber. Meanwhile, oxygen gas was also introduced into the mixing chamber and mixed with the raw material gas.
- the gas mixed in the gas mixing chamber was sent to the deposition chamber maintained at 670 Pa through the shower head to form a film on the substrate to a thickness of 120 nm (Fig. 1 0 (f)).
- the present invention it is possible to provide a ferroelectric capacitor having good morphology and formed so that the ferroelectric has a dominant orientation axis.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/000379 WO2004066388A1 (ja) | 2003-01-17 | 2003-01-17 | 強誘電体キャパシタおよびその製造方法 |
JP2004567106A JPWO2004066388A1 (ja) | 2003-01-17 | 2003-01-17 | 強誘電体キャパシタおよびその製造方法 |
EP03701774A EP1585176A4 (en) | 2003-01-17 | 2003-01-17 | FERROELECTRIC CAPACITOR AND METHOD FOR PRODUCING THE SAME |
CNB038223007A CN100470807C (zh) | 2003-01-17 | 2003-01-17 | 铁电电容器及其制造方法 |
US11/062,856 US20050167713A1 (en) | 2003-01-17 | 2005-02-23 | Ferroelectric capacitor and method of production of same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/000379 WO2004066388A1 (ja) | 2003-01-17 | 2003-01-17 | 強誘電体キャパシタおよびその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/062,856 Continuation US20050167713A1 (en) | 2003-01-17 | 2005-02-23 | Ferroelectric capacitor and method of production of same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004066388A1 true WO2004066388A1 (ja) | 2004-08-05 |
Family
ID=32750555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/000379 WO2004066388A1 (ja) | 2003-01-17 | 2003-01-17 | 強誘電体キャパシタおよびその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20050167713A1 (ja) |
EP (1) | EP1585176A4 (ja) |
JP (1) | JPWO2004066388A1 (ja) |
CN (1) | CN100470807C (ja) |
WO (1) | WO2004066388A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008294345A (ja) * | 2007-05-28 | 2008-12-04 | Seiko Epson Corp | 強誘電体メモリ装置の製造方法及び強誘電体メモリ装置 |
KR101763434B1 (ko) | 2011-06-24 | 2017-08-01 | 서울시립대학교 산학협력단 | 태양전지 및 그 제조방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106409818B (zh) * | 2016-10-17 | 2019-01-22 | 北京工业大学 | 一种非破坏性得到柔性铁电薄膜电容的方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0698918A1 (en) * | 1994-08-01 | 1996-02-28 | Texas Instruments Incorporated | A conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes |
US5508953A (en) * | 1993-05-14 | 1996-04-16 | Texas Instruments Incorporated | Capacitor, electrode structure, and semiconductor memory device |
JPH11204744A (ja) * | 1998-01-14 | 1999-07-30 | Sony Corp | 強誘電体材料、キャパシタおよびメモリならびにそれらの製造方法 |
WO1999042282A1 (en) * | 1998-02-20 | 1999-08-26 | Advanced Technology Materials, Inc. | A-site and/or b-site modified pbzrtio3 materials and films |
JPH11261028A (ja) * | 1998-03-12 | 1999-09-24 | Toshiba Corp | 薄膜キャパシタ |
JP2000351784A (ja) * | 1999-04-30 | 2000-12-19 | Pohang Eng College | 有機金属錯体およびその製造方法並びにそれを用いた有機金属化学成長法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030001189A1 (en) * | 2000-02-24 | 2003-01-02 | Tetsuo Fujiwara | Ferroelectric capacitor and semiconductor device |
EP1117132A1 (en) * | 1998-09-22 | 2001-07-18 | Hitachi, Ltd. | Ferroelectric device and semiconductor device |
US6316797B1 (en) * | 1999-02-19 | 2001-11-13 | Advanced Technology Materials, Inc. | Scalable lead zirconium titanate(PZT) thin film material and deposition method, and ferroelectric memory device structures comprising such thin film material |
US6396094B1 (en) * | 2000-05-12 | 2002-05-28 | Agilent Technologies, Inc. | Oriented rhombohedral composition of PbZr1-xTixO3 thin films for low voltage operation ferroelectric RAM |
JP2002212129A (ja) * | 2001-01-12 | 2002-07-31 | Mitsubishi Materials Corp | 金属キレート錯体及びその合成方法 |
JP4428500B2 (ja) * | 2001-07-13 | 2010-03-10 | 富士通マイクロエレクトロニクス株式会社 | 容量素子及びその製造方法 |
-
2003
- 2003-01-17 EP EP03701774A patent/EP1585176A4/en not_active Withdrawn
- 2003-01-17 CN CNB038223007A patent/CN100470807C/zh not_active Expired - Fee Related
- 2003-01-17 JP JP2004567106A patent/JPWO2004066388A1/ja not_active Withdrawn
- 2003-01-17 WO PCT/JP2003/000379 patent/WO2004066388A1/ja not_active Application Discontinuation
-
2005
- 2005-02-23 US US11/062,856 patent/US20050167713A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508953A (en) * | 1993-05-14 | 1996-04-16 | Texas Instruments Incorporated | Capacitor, electrode structure, and semiconductor memory device |
EP0698918A1 (en) * | 1994-08-01 | 1996-02-28 | Texas Instruments Incorporated | A conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes |
JPH11204744A (ja) * | 1998-01-14 | 1999-07-30 | Sony Corp | 強誘電体材料、キャパシタおよびメモリならびにそれらの製造方法 |
WO1999042282A1 (en) * | 1998-02-20 | 1999-08-26 | Advanced Technology Materials, Inc. | A-site and/or b-site modified pbzrtio3 materials and films |
JPH11261028A (ja) * | 1998-03-12 | 1999-09-24 | Toshiba Corp | 薄膜キャパシタ |
JP2000351784A (ja) * | 1999-04-30 | 2000-12-19 | Pohang Eng College | 有機金属錯体およびその製造方法並びにそれを用いた有機金属化学成長法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1585176A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008294345A (ja) * | 2007-05-28 | 2008-12-04 | Seiko Epson Corp | 強誘電体メモリ装置の製造方法及び強誘電体メモリ装置 |
KR101763434B1 (ko) | 2011-06-24 | 2017-08-01 | 서울시립대학교 산학협력단 | 태양전지 및 그 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
CN100470807C (zh) | 2009-03-18 |
JPWO2004066388A1 (ja) | 2006-05-18 |
EP1585176A1 (en) | 2005-10-12 |
EP1585176A4 (en) | 2007-10-03 |
US20050167713A1 (en) | 2005-08-04 |
CN1682371A (zh) | 2005-10-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5572052A (en) | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer | |
KR100269851B1 (ko) | 반도체장치의 제조방법 | |
JP5719849B2 (ja) | 薄膜製造方法 | |
US6800567B2 (en) | Method for forming polyatomic layers | |
JP3133922B2 (ja) | 強誘電体薄膜被覆基板、その製造方法、及びキャパシタ構造素子 | |
KR100373079B1 (ko) | 다층 전극을 갖는 납 게르마네이트 강유전성 구조 및 그의퇴적 방법 | |
US6333066B1 (en) | Method for forming PZT thin film using seed layer | |
TW527665B (en) | Chemical vapor deposition process for fabricating layered superlattice materials | |
JPH10182291A (ja) | 強誘電体薄膜の製造方法、強誘電体薄膜被覆基板及びキャパシタ | |
JP3109485B2 (ja) | 金属酸化物誘電体膜の気相成長方法 | |
JP3971645B2 (ja) | 半導体装置の製造方法 | |
US7629183B2 (en) | Method for manufacturing semiconductor device and computer storage medium | |
US7811834B2 (en) | Methods of forming a ferroelectric layer and methods of manufacturing a ferroelectric capacitor including the same | |
JP3137004B2 (ja) | 半導体素子のキャパシタ構造の作製方法 | |
EP1115148A1 (en) | Vapor growth method for metal oxide dielectric film and vapor growth device for metal oxide dielectric material | |
US20050167713A1 (en) | Ferroelectric capacitor and method of production of same | |
WO2002013251A1 (fr) | Procede de depot en phase vapeur pour film dielectrique en oxyde metallique | |
JP2001220676A (ja) | 強誘電体材料薄膜の成膜方法とその用途 | |
US6863726B2 (en) | Vapor phase growth method of oxide dielectric film | |
JP4628954B2 (ja) | 酸化物薄膜製造方法 | |
JPH0689986A (ja) | 電子デバイスおよびその製造方法 | |
JP2004079695A (ja) | Pzt強誘電体薄膜の形成方法、並びにそれにより形成したpzt強誘電体薄膜及びこれを用いた半導体装置 | |
JP2004281762A (ja) | 強誘電体薄膜の形成方法 | |
JP3886921B2 (ja) | 化学気相堆積方法 | |
JP2005166965A (ja) | 薄膜製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN JP US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2004567106 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2003701774 Country of ref document: EP Ref document number: 11062856 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 20038223007 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2003701774 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2003701774 Country of ref document: EP |