WO2004066259A1 - ラッチ、ラッチの駆動方法、フラットディスプレイ装置 - Google Patents
ラッチ、ラッチの駆動方法、フラットディスプレイ装置 Download PDFInfo
- Publication number
- WO2004066259A1 WO2004066259A1 PCT/JP2003/016865 JP0316865W WO2004066259A1 WO 2004066259 A1 WO2004066259 A1 WO 2004066259A1 JP 0316865 W JP0316865 W JP 0316865W WO 2004066259 A1 WO2004066259 A1 WO 2004066259A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- latch
- cmos
- cell
- latch cell
- cmos latch
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
- H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
Definitions
- the present invention relates to a latch, a method of driving a latch, and a flat display device, and can be applied to, for example, a horizontal drive circuit of a liquid crystal display device, a liquid crystal display device using the horizontal drive circuit, and the like.
- the CMOS latch cell disconnected from the power supply, the input of the CMOS latch cell is connected to the preceding circuit to set the corresponding data, and then the input of the CMOS latch cell is disconnected from the preceding circuit.
- power consumption can be reduced and the configuration can be simplified as compared with the conventional case.
- a driving circuit for the liquid crystal display panel is provided on a glass substrate, which is an insulating substrate constituting the liquid crystal display panel. It is designed to be provided as an integral component.
- image data is converted from digital to analog by selecting a plurality of reference voltages in accordance with the image data.
- a method of generating a signal has been adopted.
- FIG. 1 is a connection diagram showing a digital-to-analog conversion circuit according to this method.
- the digital-to-analog conversion circuit 1 is provided with a plurality of series circuits each including a switch circuit that is turned on and off in accordance with the logical value of each bit b0 to b4 of the image data D1 corresponding to the gradation.
- FIG. 1 shows the case where the image data D1 is 5 bits, and the switch circuit is a conductive type MOS (Metal Oxide Semiconductor) transistor.
- MOS Metal Oxide Semiconductor
- the N-channel and the P-channel are appropriately arranged so that a reference voltage formed by a resistor and corresponding to the value of the image data D1 can be selected.
- the digital-to-analog conversion circuit 1 selects and outputs the reference voltages V0 to V31 according to the image data D1.
- each bit b0 to b4 of the image data D1 is level-shifted and input to the digital-analog conversion circuit 1.
- the conduction type MOS transistor constituting the switch circuit of the digital / analog conversion circuit is reliably turned on / off.
- FIG. 2 is a connection diagram showing a 1-bit processing system of the image data D 1 input to the digital-to-analog conversion circuit 1.
- this 1-bit processing system is provided for the number of bits of the image data D1, and together with the digital-to-analog conversion circuit 1 of FIG. 1, the gradation of one liquid crystal cell is increased.
- the horizontal drive circuit is formed by setting and sequentially forming a configuration corresponding to the one liquid crystal cell in response to a liquid crystal cell that is continuous in the horizontal direction.
- this processing system includes a sampling latch 3 for sampling the image data DATA input in the raster scanning order at a corresponding timing, a second latch for latching the latch result by the sampling latch in a horizontal scanning cycle, and then performing a level shift. And a latch 4.
- the sampling latch 3 includes an N-channel MOS (hereinafter referred to as NMOS) transistor Q1 and a P-channel MOS (hereinafter referred to as PMOS) transistor Q2 whose gates and drains are commonly connected.
- NMOS N-channel MOS
- PMOS P-channel MOS
- the CMOS inverter 5 and the CMOS inverter 6 composed of the NMOS transistor Q 3 and the PMOS transistor Q 4 whose gate and drain are connected in common, respectively, are connected to the power supply VDD 1 and the ground. Are connected in parallel.
- the output of the CMOS inverter 5 is input to the CMOS inverter 6, and the output of the CMOS inverter 6 is output from the CMOS inverter 5 via the NMOS transistor Q 5 that is turned on and off by the inverted signal of the sampling pulse sp.
- the sampling latch 3 forms a CMOS latch cell 7 having a comparator configuration. It has been made to be.
- 1-bit data DATA of image data is input to the CMOS inverter 5 via the NMOS transistor Q6 which is turned on and off by the sampling pulse sp. In this case, in the data DATA, the signal level changes by about 0 to 3 [V] according to the logical value.
- the sampling latch 3 outputs a latch result latched by the CMOS latch cell 7 having such a comparator configuration to a CMOS inverter 8 composed of an NMOS transistor Q7 and a PMOS transistor Q8, followed by a second latch 4
- the inverted output of the CMOS inverter 8 is output to the second latch 4 via the CMOS inverter 9 including the NMOS transistor Q 9 and the PMOS transistor 10.
- the data DATA (FIG. 3 (A)) is latched by the sampling pulse sp (FIG. 3 (B).
- the latch result 1 L out (Fig. 3 (C)).
- the second latch 4 has a comparator configuration including a CMOS inverter 10 including an NMOS transistor Q11 and a PMOS transistor Q12 and a CMOS inverter 11 including an NMOS transistor Q13 and a PMOS transistor Q14.
- a CMOS latch cell 12 is formed, and the latched result 1 L out of the sampling latch 3 is output to the inverted output of the latched result 1 L out via NMOS transistors Q 15 and Q 16 operated by the latch pulse oe 1. Input to CMOS latch cells 1 and 2.
- the second latch 4 receives a predetermined pulse o e 2 and an inverted signal x o e 2 of the pulse o e 2 via the NMOS transistors Q 17 and Q 19 which are turned on and off complementarily.
- the CMOS latch cell 12 is connected to the ground VSS 1 and the negative power supply VSS 2, and the CMOS latch cell 12 is connected through the same PMOS transistors Q 20 and Q 22.
- the output of the OS latch cell 12 is output to the corresponding bit of the digital-to-analog conversion circuit 1 via the CMOS inverter 13 composed of the NMOS transistor Q23 and the PMOS transistor Q24.
- the pulse oe 2 After setting the power supply of the CMOS latch cell 12 to the same power supply as the power supply VDD1 of the sampling latch 3 (time tl) by the setting in Fig. 3 (E)), the latch pulse oe1 (Fig. 3 (D))
- the latch result of the sampling latch 3 is latched in the CMOS latch cell 12 (time t 2).
- the present invention has been made in view of the above points, and has an object to propose a latch, a latch driving method, and a flat display device with a simple configuration, which consume less power than conventional ones. .
- a CMOS latch cell and a CMOS latch cell are connected to a power supply by applying the present invention to a latch for sampling continuous image data or a latch for latching a latch result of a preceding sampling latch.
- Power switch, and an input switch disposed in the input stage of the CMOS latch cell.
- the power of the CMOS latch cell is turned on, and the data set in the CMOS latch cell is level-shifted.
- the power supply switch and the input switch are turned on / off complementarily, so that the data to be latched is set in the CMOS latch cell while the CMOS latch cell is disconnected from the power supply.
- the connection to one power supply can be processed. Accordingly, a through current when switching the power supply can be effectively avoided, and power consumption can be reduced accordingly.
- the control related to the power supply is simplified, the overall configuration can be simplified.
- CMOS latch cell that samples and latches continuous image data
- CMOS latch that latches the latch result of the preceding sampling latch
- the input of the CMOS latch cell is disconnected from the circuit in the preceding stage, and the power supply of the CMOS latch cell is turned on to shift the level of the data set in the CMOS latch cell.
- a display unit having pixels arranged in a matrix and a driving circuit for driving the pixels of the display unit are applied to a flat display device integrally formed on a substrate, and the Among the circuits, a horizontal drive circuit that sets the gradation of the pixels in the display section includes a sampling latch that sequentially latches continuous image data, and a second latch that latches the latched result of the sampling latch in one line cycle.
- a digital-to-analog conversion circuit that converts the output of the second latch to digital-to-analog and outputs the converted output to the display unit.
- FIG. 1 is a connection diagram showing a digital-to-analog conversion circuit based on a method of selecting a reference voltage.
- FIG. 2 is a connection diagram showing a conventional sampling latch and a second latch.
- FIG. 3 is a time chart for explaining the operations of the sampling latch and the second latch of FIG.
- FIG. 4 is a block diagram showing a portable terminal device with a liquid crystal display unit using a sampling latch and a second latch according to the first embodiment of the present invention. .
- FIG. 5 is a block diagram showing the horizontal drive circuit of FIG.
- FIG. 6 is a connection diagram showing the sampling latch and the second latch of FIG.
- FIG. 7 is a time chart for explaining the operations of the sampling latch and the second latch of FIG.
- FIG. 8 is a connection diagram showing a sampling latch and a second latch according to a second embodiment of the present invention.
- FIG. 9 is a time chart for explaining the operation of the sampling latch and the second latch of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 4 is a block diagram illustrating an image display unit according to the mobile terminal device according to the first embodiment of the present invention.
- This mobile terminal device is, for example, a mobile phone, a PDA, or the like.
- a desired image is displayed by the image display unit 31 of the first embodiment. Therefore, in the image display section 31, the image data D 1 is stored in an image memory built in the image processing circuit 32, and the image data D 1 is sequentially output to the liquid crystal display device 33.
- the master clock MCK, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HS YNC are output in synchronization with the output of the image data D1.
- the portable terminal device inputs the image data D 1, the master clock MCK, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC to a built-in liquid crystal display device 33, and displays an image on the liquid crystal display device 33.
- the liquid crystal display device 33 is a flat display formed by integrally forming a display section 34 in which pixels are arranged in a matrix and a drive circuit 35 for driving the pixels of the display section 34 on a glass substrate.
- the pixels of the display section 34 are composed of a liquid crystal cell, a polysilicon TFT for switching the liquid crystal cell, and an auxiliary capacitor.
- the drive circuit 35 inputs the master clock MCK, the vertical synchronizing signal V SYNC, and the horizontal synchronizing signal H SYNC to the timing generator (TG) 37 via the interface (IF) 36, and here, the various operation standards Generate timing signals.
- the DC-DC converter (DDC) 41 is operated by a predetermined timing signal generated by the timing generator 37, and necessary for the operation of each part from the power supply VDD supplied to the liquid crystal display device 33. Generate power supply VDD 2, VVS S 2, HVS S 2, etc.
- the vertical drive circuit 38 operates by a predetermined timing signal generated by the timing generator 37, and outputs a selection signal for selecting a line of the display unit 34.
- the reference voltage generation circuit 39 generates a reference voltage required for the processing of the horizontal drive circuit 40, and the horizontal drive circuit 40 sets the gradation of the corresponding pixel of the display section 34 by the gradation data based on the image data D1. I do.
- the horizontal drive circuit 40 comprises a sampling latch 51, a second latch 52, and a digital-to-analog converter (DAC) 53, as shown in FIG.
- the digital / analog conversion circuit 53 has the same configuration as the digital / analog conversion circuit 1 described above with reference to FIG.
- the sampling rack 51 is also described above with reference to FIG.
- the configuration is the same as that of the sampling latch 3.
- the transistors Q22 and Q17 disposed on the power supply and the ground are omitted, and the transistors Q19 and Q20 are used as the output terminals for controlling the input of the second latch 52.
- the configuration is the same as that of the second latch 4 having the conventional configuration described above with reference to FIG. 2, except that it is commonly controlled by one pull oe.
- the sampling latch 51 in the same manner as in the prior art, the amplitude of 0 to 3 [V] is obtained by the sampling pulse sp of amplitude 0 to 6 [V] (FIG. 7 (B)).
- the data DATA (Fig. 7 (A)) is latched, and as a result, a latch result 1 L out (Fig. 7 (C)) with an amplitude of 0 to 3 [V] is output.
- data to be latched is set in the CMOS latch cell 12 in a state where the CMOS latch cell 12 of the CMOS configuration used for the latch is disconnected from the power supplies VDD 2 and VSS 2. After that, the input of the CMOS latch cell 12 is disconnected from the circuit of the preceding stage, and the power supply of the CMOS latch cell 12 is turned on by the transistors Q19 and Q20. Even without switching between the two power supplies VDD 1 and VDD 2 according to 20, the data signal 2 L out can be level-shifted and output.
- the horizontal drive circuit 40 two transistors can be omitted in each of the second latches related to 1-bit processing, thereby simplifying the configuration and narrowing the frame. .
- the wiring of the power supply can be made smaller, so that the overall configuration can be simplified. .
- the data to be latched is set in this CMOS latch cell 12,
- the two power supplies 1 Data signals can be level-shifted and output without switching VDD2. As a result, power consumption can be reduced and the configuration can be simplified as compared with the conventional case.
- FIG. 8 shows a sampling latch 61 and a second latch 62 according to the second embodiment, which are applied instead of the sampling latch 51 and the second latch 52 described above with reference to FIG.
- the sampling latch 61 and the second latch 62 are latched by the sampling latch 61, they are also level-shifted. That is, in the sampling latch 61, the CMOS latch cell 7 is connected to the power supply by the transistors Q31 and Q32 which are turned on and off by the sampling pulse sp. As a result, as shown in FIG. With the latch cell 7 disconnected from the power supplies VDD 2 and VSS 2, the data to be latched is set in this CMOS latch cell 7 (Fig.
- the processing systems may be grouped and these transistors may be arranged in each group to collectively control the power supply, and furthermore, all the processing systems may collectively control the power supply. You may.
- the present invention is not limited to this, and can be widely applied to a flat display device including pixels by various display means.
- the CMOS latch cell in a state where the CMOS latch cell is disconnected from the power supply, the input of the CMOS latch cell is connected to the circuit of the preceding stage, and the corresponding data is set.
- the power consumption is reduced compared to the past.
- the configuration can be simplified. Industrial applicability
- the present invention relates to a latch, a latch driving method, and a flat display device, and can be applied to, for example, a horizontal drive circuit of a liquid crystal display device, a liquid crystal display device using the horizontal drive circuit, and the like.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/542,250 US7391403B2 (en) | 2003-01-24 | 2003-12-26 | Latch, latch driving method , and flat display apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-015637 | 2003-01-24 | ||
JP2003015637A JP4085324B2 (ja) | 2003-01-24 | 2003-01-24 | ラッチ、ラッチの駆動方法、フラットディスプレイ装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004066259A1 true WO2004066259A1 (ja) | 2004-08-05 |
Family
ID=32767445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/016865 WO2004066259A1 (ja) | 2003-01-24 | 2003-12-26 | ラッチ、ラッチの駆動方法、フラットディスプレイ装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7391403B2 (ja) |
JP (1) | JP4085324B2 (ja) |
KR (1) | KR20050094442A (ja) |
CN (1) | CN100403389C (ja) |
TW (1) | TWI244627B (ja) |
WO (1) | WO2004066259A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006133551A (ja) * | 2004-11-08 | 2006-05-25 | Nec Electronics Corp | カラー表示装置及びその駆動回路 |
US20090128585A1 (en) * | 2007-11-19 | 2009-05-21 | Seiko Epson Corporation | Electrophoretic display device, method for driving electrophoretic display device, and electronic apparatus |
CN106128378B (zh) * | 2016-06-28 | 2020-01-07 | 厦门天马微电子有限公司 | 移位寄存单元、移位寄存器及显示面板 |
US10571516B2 (en) * | 2017-08-30 | 2020-02-25 | Arm Limited | CMOS process skew sensor |
US11869623B2 (en) * | 2021-08-30 | 2024-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Latch type sense amplifier |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07199873A (ja) * | 1993-12-29 | 1995-08-04 | Casio Comput Co Ltd | 液晶表示装置 |
JPH11289246A (ja) * | 1998-04-06 | 1999-10-19 | Nec Corp | 半導体集積回路 |
JP2000221926A (ja) * | 1999-02-01 | 2000-08-11 | Sony Corp | ラッチ回路およびこれを搭載した液晶表示装置 |
WO2001018962A1 (fr) * | 1999-09-03 | 2001-03-15 | Lucent Technologies Inc. | Circuit a bascule, et procede de maintien et de synchronisation de donnees utilisant un signal d'horloge |
JP2002311920A (ja) * | 2001-04-19 | 2002-10-25 | Matsushita Electric Ind Co Ltd | 液晶表示装置、画像表示応用機器、及び情報携帯端末機器 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100204909B1 (ko) * | 1997-02-28 | 1999-06-15 | 구본준 | 엘씨디 소스 드라이버 |
JPH11112297A (ja) * | 1997-10-06 | 1999-04-23 | Nec Corp | ラッチ回路及びこのラッチ回路を有する半導体集積回路 |
TW461180B (en) * | 1998-12-21 | 2001-10-21 | Sony Corp | Digital/analog converter circuit, level shift circuit, shift register utilizing level shift circuit, sampling latch circuit, latch circuit and liquid crystal display device incorporating the same |
JP4576648B2 (ja) | 1998-12-21 | 2010-11-10 | ソニー株式会社 | 液晶表示装置 |
JP2000242207A (ja) | 1999-02-24 | 2000-09-08 | Toshiba Corp | 画像表示装置 |
KR100345285B1 (ko) | 1999-08-07 | 2002-07-25 | 한국과학기술원 | 액정표시기용 디지털 구동회로 |
US6377098B1 (en) * | 2000-04-21 | 2002-04-23 | International Business Machines Corporation | CMOS latch having a selectable feedback path |
-
2003
- 2003-01-24 JP JP2003015637A patent/JP4085324B2/ja not_active Expired - Fee Related
- 2003-12-26 US US10/542,250 patent/US7391403B2/en not_active Expired - Fee Related
- 2003-12-26 KR KR1020057013273A patent/KR20050094442A/ko not_active Application Discontinuation
- 2003-12-26 CN CNB2003801091440A patent/CN100403389C/zh not_active Expired - Fee Related
- 2003-12-26 WO PCT/JP2003/016865 patent/WO2004066259A1/ja active Application Filing
-
2004
- 2004-01-19 TW TW093101421A patent/TWI244627B/zh not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07199873A (ja) * | 1993-12-29 | 1995-08-04 | Casio Comput Co Ltd | 液晶表示装置 |
JPH11289246A (ja) * | 1998-04-06 | 1999-10-19 | Nec Corp | 半導体集積回路 |
JP2000221926A (ja) * | 1999-02-01 | 2000-08-11 | Sony Corp | ラッチ回路およびこれを搭載した液晶表示装置 |
WO2001018962A1 (fr) * | 1999-09-03 | 2001-03-15 | Lucent Technologies Inc. | Circuit a bascule, et procede de maintien et de synchronisation de donnees utilisant un signal d'horloge |
JP2002311920A (ja) * | 2001-04-19 | 2002-10-25 | Matsushita Electric Ind Co Ltd | 液晶表示装置、画像表示応用機器、及び情報携帯端末機器 |
Also Published As
Publication number | Publication date |
---|---|
TW200424989A (en) | 2004-11-16 |
JP4085324B2 (ja) | 2008-05-14 |
CN1742316A (zh) | 2006-03-01 |
US7391403B2 (en) | 2008-06-24 |
JP2004226776A (ja) | 2004-08-12 |
KR20050094442A (ko) | 2005-09-27 |
TWI244627B (en) | 2005-12-01 |
US20060055652A1 (en) | 2006-03-16 |
CN100403389C (zh) | 2008-07-16 |
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