Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/01—Manufacture or treatment
  • H10D10/051—Manufacture or treatment of vertical BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/40—Vertical BJTs
  • H10D10/421—Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/281—Base electrodes for bipolar transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
  • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
  • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures

Definitions

• the present invention relates in general to semiconductor devices and, more particularly, to vertical gate transistors.
• previous high frequency power transistors require advanced photolithographic equipment capable of resolving small feature sizes in order to provide the shorter length channels necessary to reduce switching losses .
• Some previous high frequency transistors are formed with vertical gate structures in which the channel lengths are defined by the thickness of the deposited gate electrode rather than a feature size of a photolithographic tool. This approach reduces the need for expensive photolithographic equipment, which reduces the cost of building the devices.
• previous vertical gate devices require numerous masking steps and a complex sequence of processing steps, which reduces the die yield and increases the manufacturing cost of the devices.
• FIG. 1 is a cross-sectional view of a semiconductor device after a first fabrication stage
• FIG. 2 is a cross-sectional view of the semiconductor device after a second fabrication stage
• FIG. 3 is a cross-sectional view of the semiconductor device after a third fabrication stage.
• FIG. 4 is a cross-sectional view of the semiconductor device after a fourth fabrication stage.
• FIG. 5 is a top view of the semiconductor device showing features of the device layout.
• FIG. 1 is a cross-sectional view of a cell of a semiconductor device 10 formed with a semiconductor substrate 12 after a first processing stage.
• semiconductor device 10 operates as a switching metal-oxide-semiconductor field effect transistor operating at a current greater than one ampere .
• a base layer 14 is formed to have a thickness of about two hundred fifty micrometers.
• base layer 14 is heavily doped to have an n-type conductivity and a resistivity of about 0.01 ohm-centimeters to provide a low on-resistance for semiconductor device 10.
• base layer 14 comprises monocrystalline silicon.
• An epitaxial layer 16 is grown to a thickness of about three micrometers over base layer 14.
• epitaxial layer 16 comprises monocrystalline silicon doped to have an n-type conductivity and a doping concentration of about 3.0*10 16 atoms/centimeter 3 .
• a blanket n-type implant is applied to substrate 12 to produce a region 17 whose doping concentration is about 1.0*10 17 atoms/centimeter 3 to prevent a low voltage breakdown due to drain pinchoff .
• region 17 is formed to a depth of about 0.5 micrometers .
• a gate dielectric layer 18 is formed over epitaxial layer 16 to a thickness of about three hundred fifty angstroms.
• dielectric layer 18 is formed with a thermally grown silicon dioxide.
• a dielectric layer 19 is formed over dielectric layer 18 to a thickness of about one thousand five hundred angstroms.
• dielectric layer 19 comprises silicon nitride.
• a dielectric layer 20 is formed over dielectric layer 19 to a thickness of about six thousand angstroms.
• dielectric layer 20 is formed with a tetra- ethyl orthosilicate (TEOS) process to form a deposited silicon dioxide.
• TEOS tetra- ethyl orthosilicate
• a conductive semiconductor layer 21 is deposited over dielectric layer 20 to a thickness of about one thousand eight hundred angstroms.
• semiconductor layer 21 comprises polycrystalline silicon which is heavily doped to provide a low resistance.
• Semiconductor layer 21 may include a film of platinum, tungsten or titanium silicide or similar material to provide an even lower resistance.
• a dielectric layer 22 is formed over semiconductor layer 21 to a thickness of about four thousand angstroms. In one embodiment, dielectric layer 22 is formed with a TEOS process to comprise a deposited silicon dioxide.
• a surface 29 of substrate 12 is patterned in a first photoresist step to mask a series of standard etch steps that successively remove exposed portions of dielectric layer 22, semiconductor layer 21 and dielectric layers 19 and 18 to form a raised pedestal structure 24.
• a recessed region 34 adjacent to pedestal structure 24 is bounded by vertical walls or surfaces 28 which typically are separated by a distance ranging between two and three micrometers, approximately, depending on the subsequent film thicknesses and desired voltage breakdown.
• Vertical walls 28 are used to mask or define an implant into a body region 31 of substrate 12 that inverts to form a channel of semiconductor device 10 as described below. Hence, body region 31 is self-aligned to vertical walls 28.
• An isotropic silicon nitride etch is then applied to undercut dielectric layer 19 to recess its vertical surface 32 relative to vertical walls 28.
• Recessing surface 32 in this fashion ensures that a channel (not shown) formed in body region 31 extends to a boundary or edge 33 of body region 31 to allow channel current to flow into epitaxial layer 14.
• Recessing vertical surface 32 also increases the operating voltage of semiconductor device 10 by increasing its channel length.
• dielectric layer 19 is recessed a distance of about 0.1 micrometers.
• a semiconductor layer 35 is deposited on substrate 12 as shown to a thickness of about four thousand angstroms. Semiconductor layer 35 typically is doped to have the same conductivity type as semiconductor layer 21 and a low resistance. Note that semiconductor layers 21 and 35 are electrically coupled to each other along vertical wall 28. [0020] FIG.
• FIG. 2 is a cross-sectional view of semiconductor device 10 after a second fabrication stage.
• An anisotropic etch is applied to semiconductor layer 35 to form spacers adjacent to pedestal structure 24 operating as vertical gates 40.
• a vertical gate refers to a control electrode formed with a gate material deposited on a first surface to control a conduction channel formed on a second surface perpendicular to the first surface.
• channels 50 are formed at a surface 48 of body region 31, which is considered to be a horizontal surface.
• the control electrode film, i.e., semiconductor layer 35 is deposited along walls 28, which run perpendicular to surface 48 and therefore are referred to a vertical walls 28. As a result, the channel length is determined by the thickness of the vertical gate 40 film.
• a control signal applied to vertical gates 40 causes body region 31 to invert at top surface 48 to form channels 50 with a length about equal to the thickness of semiconductor layer 35.
• a thin thermal oxide is grown on exposed semiconductor surfaces to prevent contamination or static charge from accumulating through surfaces of vertical gates 40 during subsequent processing. In one embodiment, this process step results in about one hundred angstroms of silicon dioxide being grown on vertical gates 40.
• a bipolar transistor with vertical gate 40 functioning as a base electrode can be formed by omitting the etch step that recesses dielectric layer 19 and etching dielectric layer 18 to deposit semiconductor layer 35 directly on body region 31. After semiconductor layer 35 is anisotropically etched, vertical gates 40 are electrically coupled to body region 31 to form a base of the bipolar transistor. Subsequent processing is as described below, with the source and drain operating as the emitter and collector, respectively, of the bipolar device. [0023] In a second photoresist step, dielectric layer 22 is patterned and etched to form a gate contact 54 as shown.
• a blanket implant is then applied to semiconductor device 10 to form a source region 45 that is defined by, or self-aligned to, vertical gates 40.
• the blanket implant also dopes gate contact 54 to reduce its contact resistance.
• source region has an n-type conductivity and a doping concentration between about 10 19 and about 10 20 atoms/centimeter 3 .
• source region 45 defines one end of channel 50 and boundary 33 of body region 31 defines the other end. Since boundary 33 is self-aligned to vertical wall 28 and source region 45 is self-aligned to vertical gate 40, the length of channel 50 is substantially determined by the thickness of the vertical gate 40 film. In one embodiment, channel 50 has an effective length of about 0.4 micrometers, while the smallest feature size of the photolithographic processes used to this point may be as large as about three micrometers. Hence, a short channel is formed using a less expensive photolithographic tool, thereby providing a high frequency performance at a reduced cost. Moreover, performance is more consistent because the film thicknesses can be controlled more precisely than can the dimensions of surface features defined by masking. [0026] FIG.
• FIG. 3 shows a cross-sectional view of integrated circuit 10 after a third fabrication stage.
• a dielectric material is deposited on semiconductor substrate 12 and anisotropically etched to produce dielectric spacers 55 adjacent to side surfaces 49 of vertical gates 40.
• the dielectric material preferably is deposited with a film thickness greater than the thickness of semiconductor layer 35 in order to ensure that thinning of dielectric spacers 55 over topographic steps does not result in exposing vertical gates 40 during the anisotropic etch step.
• semiconductor layer 35 has a thickness of about four thousand angstroms
• the dielectric material used to form spacers 55 has a thickness of about five thousand angstroms.
• FIG. 4 is a cross-sectional view of semiconductor device 10 after a fourth fabrication stage.
• a standard semiconductor metal film is deposited on surfaces of substrate 12.
• a thin layer of platinum is deposited and annealed to form a platinum silicide layer that provides a low resistance electrical connection to the semiconductor material exposed in gate contact 54 and source contact 56.
• a titanium layer is formed to a thickness of one hundred twenty angstroms followed by an eight hundred angstrom barrier layer of titanium nitride.
• a layer of aluminum is deposited with a thickness between three and four micrometers.
• a third photoresist step is used to pattern the metal film to form a source terminal 60 and a gate terminal 62.
• a similar blanket metal film is deposited on bottom surface 63 of substrate 12 to form a drain terminal 64 with a thickness between three and four micrometers.
• a passivation layer (not shown) is deposited and patterned to produce a finished device. Note that additional masking steps may be included to provide additional or different features. For example, one additional photo asking step may be used to form semiconductor device 10 as a lateral or planar device, rather than a vertical one, by patterning a drain electrode and/or terminal on the same surface as the source electrode/terminal .
• an additional photomask may be used to pattern a field shaping region around semiconductor device 10.
• FIG. 5 shows a simplified top view of semiconductor device 10 showing selected features of the vertical gate transistor layout.
• pedestal structure 24 is formed over most of the central portion of substrate 12 with source contacts 56 arranged in multiple rows for contacting by source terminal 60 in a large region at the center of substrate 12 to provide a low on resistance.
• Gate terminal 62 is formed to surround source terminal 60 as shown and to contact semiconductor layer 21 at gate contact 54 to maintain vertical gates 40 at a constant potential .
• a field termination structure is formed around the peripheral portions of substrate 12 using an additional photomask step.
• the field termination structure shapes electric fields resulting from high voltages applied to drain terminal 64 to prevent a localized breakdown that reduces the specified performance of semiconductor device 10.
• the present invention provides a semiconductor device with a vertical gate to provide a fast switching speed and high frequency performance.
• a pedestal structure is formed on a top surface of a substrate.
• a conductive material is disposed along a side surface of the pedestal structure to self align an edge of a source electrode of the semiconductor device.
• a dielectric spacer is formed along a side surface of the conductive material to self align a contact area of the source electrode.
• a pedestal structure is formed with a single photomasking step and the gate, source and source contact are successively self aligned to a side surface or vertical wall of the pedestal structure.
• the transistor in an embodiment where the transistor is formed as a vertical power device with a drain terminal on a bottom surface of the substrate, the transistor can be fabricated using only four photomasking steps including forming the gate contact, metallization and passivation layers. One or more masking steps can be added to form field terminations for high voltage operation or a top surface drain terminal to configure the transistor as a p1anar device .

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Junction Field-Effect Transistors (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

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Family Applications (1)

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Cited By (5)

Families Citing this family (12)

Citations (5)

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• 2002
  • 2002-08-16 US US10/219,190 patent/US7045845B2/en not_active Expired - Lifetime
• 2003
  • 2003-07-28 KR KR1020057002625A patent/KR101026953B1/ko not_active Expired - Fee Related
  • 2003-07-28 CN CNB038193604A patent/CN100438071C/zh not_active Expired - Fee Related
  • 2003-07-28 EP EP03788285A patent/EP1535344B1/en not_active Expired - Lifetime
  • 2003-07-28 WO PCT/US2003/023558 patent/WO2004017419A1/en not_active Ceased
  • 2003-07-28 AU AU2003254226A patent/AU2003254226A1/en not_active Abandoned
  • 2003-07-28 JP JP2004529203A patent/JP5036130B2/ja not_active Expired - Fee Related

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