Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
  • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
  • H10D84/401—Combinations of FETs or IGBTs with BJTs
  • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors

Definitions

• the present invention relates to the field of integrated circuits and, more particularly, to integrated circuits that support digital circuits, analog circuits, and Radio-Frequency (RF) circuits on a single microchip.
• RF Radio-Frequency
• placing each of these various device types on a single IC often allows inter-circuit interaction through the IC substrate. Such interaction can greatly degrade and inhibit the expected operation of the IC when digital, analog, and RF circuit elements are placed on the same substrate.
• Analog circuitry is sensitive to electrical noise produced by other circuits and devices. To function effectively, analog circuitry is isolated from electrical noise. On the other hand, digital circuits are far less sensitive to electrical noise due to their digital nature. The low voltage swing of an analog device produces little noise. Further, the current bases for analog circuitry keeps noise levels low. Consequently, analog circuits produce low noise levels. However, digital circuits produce a significant amount of electrical noise due to the large rail to rail voltage swings of the devices. Integrating analog and digital circuit elements onto a single IC typically exposes the analog circuit elements to the high noise component produced by the digital circuit elements. To integrate analog and digital circuit components on a single IC, analog circuit components must be isolated and insulated from the electrical noise produced by digital circuit components.
• latch-up Another problem spawned by dissimilar circuitry is latch-up.
• digital CMOS circuits become “stuck" in a specific logic state.
• latch-up is caused by an internal feedback mechanism associated with parasitic
• Crosstalk also plagues dissimilar device circuitry.
• Crosstalk is interference caused by two or more signals becoming partially superimposed on each other due to electromagnetic (inductive) or electrostatic (capacitive) coupling between devices or conductors carrying the signals.
• electromagnetic inductive
• electrostatic capacitive
• this interference between devices can produce false switching in other parts of the system. Consequently, it is highly desirable to develop an IC that can support analog, digital, and RF components while reducing crosstalk to ensure high performance and reliability.
• Signal losses in the RF circuit, especially in the high frequency region are also often exhibited in mixed device ICs.
• One measure of an RF circuit is the quality factor. Efficient RF circuits with minimal signal losses have a high quality factor. RF components with a low quality factor typically require additional circuitry stages that are necessary to compensate for the consequent signal and energy losses. These additional stages consume valuable chip space and reduce the efficiency of the overall device.
• One of the causes of this signal and energy degradation, measured by the quality factor is undesirable capacitive coupling between RF devices and the substrate. This coupling reduces the quality factor.
• electrical eddy currents within the substrate also reduce the quality factor of RF devices. It is, therefore, highly desirable to develop an IC structure that has RF devices with a high quality factor to improve the overall IC operation for high frequency applications and reduce the amount of circuitry needed to support the applications.
• CMOS components To maximize the efficiency and operation of ICs for high frequency applications, it is not desirable to place all active CMOS components on a high resistivity layer. It is also desirable to develop a single integrated circuit that can support digital, analog, and RF circuit elements using BiCMOS technology.
• the present invention provides a semiconductor structure that facilitates the integration of digital, analog, and RF circuits into a single IC. More specifically, the present invention provides a structure that reduces the interaction of digital circuits, analog circuits, and RF circuits on a single IC through the substrate. The present invention reduces cross-circuit interaction through the substrate by strategically positioning the various components over either a patterned low resistivity layer or the remaining high resistivity substrate region. For the p-type substrate, the low resistivity layer is a patterned p+ buried layer. The high resistivity region is the region outside of the p+ buried layer.
• the low resistivity layer is a patterned n+ buried layer and the high resistivity region is the area outside of the n+ buried layer.
• the formation of the patterned buried layer can be achieved by high energy ion implantation or by formation of a highly doped region followed by an epitaxial silicon deposition.
• the epitaxial layer is high resistivity and can be p-type, n-type or intrinsic.
• digital CMOS circuitry is positioned over a low resistivity layer that provides good latch-up immunity and allows for dense PAD I/O.
• Analog CMOS circuitry rests on an isolated well region in the high resistivity substrate region to minimize signal crosstalk.
• Analog BJT devices rest in the highly resistive substrate region within their own well structures to minimize parasitic capacitances and encourage for high frequency device switching.
• RF passive elements such as inductors and capacitors, rest in or over the highly resistive substrate region to minimize signal losses that may occur at high frequencies.
• the strategic placement of the circuit components in or over either the low or high resistivity regions insulates and isolates the various components from noise produced from other devices or circuits located on the IC.
• Low resistivity regions reduce noise by providing a low resistance path that signals can travel through away from regions where noise sensitive circuits reside.
• High resistivity regions within the substrate reduce signal crosstalk by attenuating the electrical signals.
• Figure 1 depicts a cross section that illustrates a preferred embodiment of the present invention.
• Figure 2 depicts a semiconductor having a preferred structure of patterning a low resistivity buried layer in a preferred embodiment of the present invention.
• Figure 3 depicts a semiconductor having an alternative structure of patterning a low resistivity buried layer in a preferred embodiment of the present invention.
• Figure 4 depicts a cross section of an isolated analog circuit element in a preferred embodiment of the present invention.
• Figure 5 depicts a view of an isolated digital circuit block fabricated in accordance with a preferred embodiment of the present invention.
• Figure 6 depicts a heterojunction bipolar transistor formed in a integrated circuit made in accordance with a preferred embodiment of the present invention.
• Figure 7 depicts a varactor formed in a integrated circuit made in accordance with a preferred embodiment of the present invention.
• Figure 1 depicts a cross section of an Integrated Circuit (IC) 2 fabricated in accordance with a preferred embodiment of the present invention in a p-type substrate.
• IC 2 supports digital components 4, analog components 6, passive RF components 8, and active RF components 10.
• IC 2 is able to support digital components 4, analog components 6, passive RF components 8, and active RF components 10 through having an isolating structure 12 that reduces electrical interaction between these various components through high resistivity substrate 14.
• substrate 14 is essentially a resistor that connects all devices on IC 2.
• a CMOS digital circuit element 22 rests on a low resistivity buried layer 16.
• Passive RF circuit elements 8 such as, for example, inductor 24 rest on a highly resistive substrate 14.
• Analog circuit elements 6 such as NMOS 26 or NPN BJT 28 rest within an isolated well 30 in a highly resistive substrate 14.
• Active RF elements 10 such as Heterojunction Bipolar Transistor (HBT) 32 rest in a high resistivity region 14 to maximize the performance of HBT 32.
• HBT Heterojunction Bipolar Transistor
• CMOS 22 is comprised of a PMOS 34 and an NMOS device 36.
• MOS device 22 has a gate 38, a source 40, and a drain 42.
• Placing CMOS digital circuit element 22 on low resistivity buried layer 16 has several advantages. First, buried layer 16 reduces the occurrence of latch-up between CMOS devices 22. Latch-up is a condition under which significant current flows through substrate 14 between NMOS 36 and PMOS 34 parts of CMOS 22 and degrades its performance. Latch-up causes the CMOS circuitry 22 to fix in a specific logic state. Simply stated, latch-up is caused by an internal feedback mechanism associated with parasitic PNPN-like action. However, through providing a low resistance current path under CMOS 22, buried layer 16 reduces the occurrence of latch-up.
• the low resistivity buried layer 16 acts like a noise sink.
• CMOS digital circuitry 22 produces significant levels of noise due to the large rail to rail voltage swing of the devices 22. This electrical noise is diverted from the device through the low resistivity buried layer 16.
• buried layer 16 is strategically positioned under just digital CMOS components 22. In this manner, the noise in buried layer 16 is generally restricted to digital CMOS components 22.
• Analog CMOS components 44 rest on a highly resistive substrate 14. Highly resistive substrate 14 attenuates the noise from the buried layer 16 thereby isolating and insulating analog CMOS components 44 from digital CMOS components 22. While the remaining digital CMOS components 22 are exposed to the noise from buried layer 16, the digital nature of CMOS components 22 makes them relatively insensitive to noise.
• Buried layer 16 while depicted in conjunction with digital CMOS 22, is also used along with various well structures to isolate other electrically noisy devices within IC 2.
• An example of an electrically noisy device is a charge pump. By placing a charge pump in an isolated well 20 which is surrounded by regions of n-well 46 and p-well 48, it is possible to isolate the surrounding components from the electrical noise produced by the charge pump. To further bolster the isolation, p-well 48 is placed over a p+ buried layer 16. Due to its low resistivity, electrical noise within IC 2 and collected by p-well 48 can be effectively removed from IC 2. In this manner, the combination of p-well 48 and p+ buried layer 16 reduce the propagation of noise when integrating digital components 4, analog components 6, passive RF components 8, and active RF components 10 on single IC 2.
• Active RF elements 10 such as heterojunction bipolar transistor 32 rest on high resistivity substrate 14.
• Figure 1 includes the depiction of an NPN HBT device on a p-type substrate. Through placing HBT 32 on a highly resistive substrate 14, the capacitance between a collector well 60 and the substrate 14 depicted as Ccs, is minimized. Minimizing collector 60 substrate 14 capacitance maximizes the performance of HBT 32.
• active RF component 10 is surrounded by p-well 48 which serves to isolate HBT 32 from outside noise produced elsewhere on IC 2.
• p-well 48 rests upon a p+ buried layer 16. Due to its low resistivity, electrical noise within IC 2 is collected by p-well 48 from where it is removed from IC 2. In this manner, p-well 48 reduces the amount of noise that reaches HBT 32 that is produced elsewhere on IC 2. Electrical noise within IC 2 is also collected by p+ buried layer 16 due to its low resistivity from where it is removed from IC 2. In this manner, p+ buried layer 16 reduces the amount of noise that reaches HBT 32 from elsewhere on IC 2.
• Passive RF circuit elements 8 such as inductor 70, for example, rest in or over a highly resistive region 16.
• the performance of passive RF components 8 is measured by the device quality factor. Passive components 8 having a low quality factor are undesirable in high frequency RF circuits. Low quality factor devices typically require the use of additional input stages to compensate for the loss of signal. Such additional input stages require additional chip space and increase device cost.
• Inductor 70 is shown as a series of broken lines representing the coil that forms inductor 70. High resistivity substrate 14 attenuates noise signals generated elsewhere on IC 2 from reaching passive RF elements 8 such as inductor 70.
• substrate 14 enhances the performance of inductor 70 and improves the quality factor through reducing inductor 70' s exposure to noise.
• the improvement of the quality factor is most significant at high frequencies.
• Another passive RF element 8 is a capacitor, where although not shown, the same principles apply.
• substrate 14 through attenuating the signals generated elsewhere on IC 2, substrate 14 also reduces cross-talk.
• the quality factor of inductor is further improved by its placement over high resistivity substrate 14.
• the high resistivity of substrate 14 retards the generation of electrical eddy currents beneath the inductor that degrade the performance of inductor 70.
• a further manner of isolating passive RF elements 8 such as inductor 70 is by surrounding the high resistivity substrate 14 with a p-well isolation structure 72 and a p+ buried layer 74.
• the combination of p-well 72 and p+ buried layer 74 reduces the amount of electrical noise that inductor 70 is exposed to from the remainder of IC 2. Due to its low resistivity, this structure is able to collect and remove these signals from IC 2. In this manner, p-well 72 in combination with p+ buried layer 74 reduces the amount of noise that reaches inductor 70.
• Isolating structure 12 comprised of patterned buried layer 16, high resistivity substrate 14, p-well 46 and 72, and n-well 48, reduces the problems of IC 2 noise and cross-talk that would inhibit the operation of analog 6 and RF components 8 and 10. Further, isolating structure 12 enhances the overall performance of digital components 4, analog components 6, passive RF components 8, and active RF components 10 through addressing the various parasitic problems encountered by each of these components.
• a single buried layer 16 extends under all digital CMOS components 22 in a single digital circuit block 76.
• the occurrence of latch-up within these devices 22 is greatly reduced.
• electrical noise produced from any area of block 76 is transmitted to every other area and device 22 within block 76 through buried layer 16.
• the performance of these devices 22 is not significantly degraded.
• Having a single buried layer 16 simplifies device architecture and reduces manufacturing processes and overall cost. Included in digital block 76 are CMOS 22, resistors 77, and other digital components 79.
• buried layer 16 is broken into a series of blocks 78 extending under digital CMOS components 22 in a single digital circuit block 22. Between these blocks 78 is the highly resistive region 14. It can be desirable to break the buried layer 16 into a series of smaller blocks 78 in order to limit the transmission of electrical noise within the single digital circuit block 76. While electrical noise can travel relatively easily within the buried layer blocks 78, the highly resistive regions 14 between the buried layer blocks 78 impede and attenuate the transmission of noise from one buried layer block 78 to another buried layer block 78. Inter-block delineation with highly resistive regions 14 therefore limits noise transmission within single digital block 76.
• Figure 4 depicts a cross section of an isolated analog circuit element 6 in a preferred embodiment of the present invention.
• the example shown assumes use of a p-type substrate. Various regions shield the analog circuit from the noise produced by digital CMOS 22.
• the analog circuit 6 rests in a high resistivity region 14.
• the high resistivity of substrate 14 attenuates electrical signals produced from other devices. This high attenuation reduces the occurrence of device crosstalk.
• on NMOS device 26 is comprised of a gate 80, a source 82, and a drain 84.
• a bulk contact 86 is provided for electrical communication with bulk region 88.
• the NMOS device 26 sits within an isolated p-well 90.
• N-isolation region 92 is connected to either or both the n-well ring 98 or n-well 46 to completely isolate the isolated p-well 90 from the p-type substrate 14 shown in this example.
• n-wells 46 and n-well ring 98 are maintained at the same level of potential.
• N-wells 46 and n-well ring 98 are connected through n-isolation region 92.
• Contact 94 removes any electrical signal collected by n-wells 46, n-well ring 98, or n-isolation region 92 from IC 2.
• n-wells 46, n-well ring 98, or n-isolation region 92 serve to insulate and isolate the various circuit components on IC 2 from electrical noise produced by digital CMOS 22 or other noisy electrical components like charge pumps.
• Figure 5 depicts a view of an isolated digital circuit block 76 fabricated in accordance with a preferred embodiment of the present invention.
• digital block 76 is comprised of digital CMOS circuitry 22 along with resistors 77 and other digital electrical components 79.
• Digital block 76 rests on single p+ buried layer 16. Through having single p+ buried layer 16 extend under the entire single digital circuit block 76, the likelihood of latch-up within these devices 22 is greatly reduced. Due to the large rail to rail voltage swings of digital CMOS 22, circuits 22 are electrically noisy. This electrical noise produced by digital CMOS 22 will propagate through substrate 14 to analog 6 and RF components 8 and 10 on IC 2 unless blocked or removed.
• an n- well ring 98 is placed around digital block 76. This n-well ring 98 collects the electrical signals produced by digital CMOS 22. Contacts 94 connected to n-well ring 98 then remove electrical signals from IC 2. The n-well ring 98 is surrounded by an isolation p-well ring 100. A p+ source drain ring 102 is placed outside of isolation p-well ring 100. Together, these well rings 98, 100, 102 collect and remove electrical signals produced by digital CMOS 22.
• FIG. 6 depicts a heterojunction bipolar transistor (HBT) 32 formed in a integrated circuit 2 made in accordance with a preferred embodiment of the present invention.
• HBT 32 is comprised of quasi self-aligned structure 104 having an emitter 106, base 108, and a collector 110.
• Self-aligned structure 104 has reduced complexity and topography. It is desirable to use HBT 32 devices for active RF functions due to their ability to be integrated with CMOS components 22.
• Emitter 112, base 114, and collector contact regions 116 are provided on a top surface of HBT 32. Vias 118 connect emitter 112, base 114, and collector contact regions. Insulating these vias is a dielectric material 122.
• a major source of HBT 32 performance degradation is the capacitance that forms between collector well 124 and the substrate 14. In order to maximize HBT 32 performance, it is necessary to minimize this collector 124 substrate 14 capacitance. Through placing HBT 32 directly on highly resistive substrate 14, this parasitic collector 124 substrate 14 capacitance is minimized.
• HBT 32 is then isolated and insulated from electrical noise produced by other devices on IC 2 through the use of p-well 48 and p+ buried layer 16.
• P- well 48 and p+ buried layer 16 collect electrical signals produced elsewhere on the IC 2 and removes them from the system thereby isolating HBT 32. In this manner, electrical noise and cross-talk problems are reduced thereby enhancing the performance of HBT 32.
• FIG. 7 depicts a varactor 126 formed in a integrated circuit 2 made in accordance with a preferred embodiment of the present invention.
• the term "varactor” comes from the words variable reactor and means a device whose reactance can be varied in a controlled manner with a bias voltage. Varactors 126 are widely used in parametric amplification, harmonic generation, mixing, detection, and voltage-variable tunning applications. Varactor 126, depicted in Figure 7, over a p-type substrate and has gates 128 and base contacts 130 provided on n-well 132. Varactor 126 is placed over a p+ buried layer 16. As an active RF component 10, it is highly desirable to maximize the quality factor of varactor 126. Through placing varactor 126 in n-well 132, the quality factor is improved due to the low resistivity and isolation provided by n-well 132.

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2002
  • 2002-06-24 US US10/178,672 patent/US20030234438A1/en not_active Abandoned
• 2003
  • 2003-05-21 CN CNA03800917XA patent/CN1547775A/zh active Pending
  • 2003-05-21 KR KR10-2004-7002733A patent/KR20050013190A/ko not_active Withdrawn
  • 2003-05-21 EP EP03761029A patent/EP1518276A1/en not_active Withdrawn
  • 2003-05-21 JP JP2004515710A patent/JP2005531143A/ja not_active Withdrawn
  • 2003-05-21 AU AU2003248560A patent/AU2003248560A1/en not_active Abandoned
  • 2003-05-21 WO PCT/US2003/016286 patent/WO2004001850A1/en not_active Ceased

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