WO2003107520A1 - Pwmインバータ制御方法 - Google Patents
Pwmインバータ制御方法 Download PDFInfo
- Publication number
- WO2003107520A1 WO2003107520A1 PCT/JP2003/006538 JP0306538W WO03107520A1 WO 2003107520 A1 WO2003107520 A1 WO 2003107520A1 JP 0306538 W JP0306538 W JP 0306538W WO 03107520 A1 WO03107520 A1 WO 03107520A1
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- WO
- WIPO (PCT)
- Prior art keywords
- switching
- control method
- switches
- pwm
- pwm inverter
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M7/525—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency
- H02M7/527—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency by pulse width modulation
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
- H02M7/53876—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times
Definitions
- the present invention relates to reducing the noise of a PWM inverter that performs variable speed driving of a motor or the like and system linking. Background technology>
- FIG. 13 is a configuration diagram of a conventional PWM inverter.
- 1 is a controller
- 2 is a noise reduction PWM generation circuit
- 4 is a current detection circuit
- 5 is a DC power supply
- 11 is a smoothing capacitor
- 101 to 106 are switching elements
- 201 to 206 are filters. This is a wheel diode.
- the command and the output current detection value from the current detection circuit 4 are input to the controller 1.
- the controller 1 creates a low-noise-specific PWM switching pattern using the low-noise PWM creation circuit 2 according to these inputs, and outputs a command to turn on / off the switching element.
- FIG. 2 shows a typical PWM pulse pattern.
- the symbols on the space vector diagram in Fig. 2, a, b, Op, and On vector ⁇ / correspond to the switching patterns for each phase shown in Fig. 3, H indicates the upper switching element is ON, and L indicates the lower side. Indicates that the switching element is ON.
- the PWM inverter normally outputs a pattern as shown in Fig. 3, but further outputs a noise reduction pattern as shown in Fig. 4 in which the pulse pattern is rearranged by the PWM generation circuit 2. .
- This noise reduction pattern has the same time average as the normal pattern in Fig. 3, and generates a pulse pattern as shown in Fig. 4 in which the pulses are divided and concentrated or dispersed, and the noise variance is reduced. To achieve low noise I have.
- the present invention provides a PWM control method that can freely set the switching of each phase, disperses the peaks of those noises, and sets a lower limit and an upper limit to the number of switching times to set the switching loss to a set value.
- the purpose is to provide a PWM inverter control method that can achieve both low noise measures and energy savings by suppressing the following.
- the invention according to claim 1 is characterized in that two or more sets of two or more sets of rectifying elements connected in series and anti-parallel connected to each other are connected in series.
- the switching of the series-connected switching elements is performed when the operating frequency of the inverter is low.
- an arbitrary voltage is output.At that time, the lower limit of the number of switches is set so that the number of switches does not become too small.
- the set values of the number of switches and the timing are changed to the operating frequency.
- the number of switches is increased at a fixed ratio with the number, but the upper limit of the number of switches is set and limited so that the number of switches does not exceed a certain set value.
- the invention according to claim 2 has a configuration in which two or more sets of four or more even-numbered switches composed of rectifying elements connected in anti-parallel with the switching elements are connected in series.
- the multi-level PWM control method for controlling the switching of the series-connected switching elements to freely change the switching for each group and outputting a PWM pulse of three or more levels as an output level.
- the switching elements connected in series and the switching frequency and timing are set so that the frequency components of noise due to switching are not concentrated, and an arbitrary voltage is output.
- Set a lower limit on the number of switches so that the number of switches does not become too small, while increasing the operating frequency of the inverter.
- the set values of the number of times of switching and the timing are increased at a fixed ratio with the operating frequency.However, an upper limit is set on the number of times of switching so that the number of times of switching does not exceed a certain set value.
- the upper limit value of the number of times of the switching is set to be equal to or less than a set value having a time average of a switching port generated by a switching element. It is characterized by setting so that
- the upper limit of the number of times of switching is set so that the time average of the switching loss becomes equal to or less than the set value. Can be.
- the upper limit of the number of times of the switch is set so that the heat generation of the PWM inverter is equal to or less than a certain set value. It is characterized by.
- the upper limit of the switch count limit is set to the inverter Since the heat generation is set to be equal to or less than the set value, it is possible to determine and control the upper limit of the number of times of the switch using the heat generation amount as a control amount.
- the frequency component of the set number of times of switching is determined by the resonance frequency of the motor connected to the output side.
- the feature is to skip the frequency so that they are not equal.
- FIG. 1 is a diagram showing a circuit example of a PWM inverter control method according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a spatial vector of the impeller shown in FIG.
- FIG. 3 is a diagram showing a normal switching pattern of the inverter shown in FIG.
- FIG. 4 is a diagram showing a switching pattern in which the noise of the pattern shown in FIG. 3 is reduced.
- FIG. 5 is a diagram showing a switching pattern in which the inverter shown in FIG. 1 is reduced in noise and the number of times of switching is limited.
- FIG. 6 is a diagram showing a graph representing the switch count limit shown in FIG.
- FIG. 7 is a diagram showing skip frequency bands of the graph shown in FIG.
- FIG. 8 is a diagram illustrating a circuit example of a PWM inverter control method according to the second embodiment of the present invention.
- FIG. 9 is a diagram showing a spatial vector of the inverter shown in FIG.
- FIG. 10 is a diagram showing a normal switching pattern of the inverter shown in FIG.
- FIG. 11 is a diagram showing a switching pattern in which the noise of the pattern shown in FIG. 10 is reduced.
- FIG. 12 is a diagram showing a switching pattern in which the inverter shown in FIG. 8 is reduced in noise and the number of times of switching is limited.
- FIG. 13 is a diagram showing a circuit example of a conventional PWM inverter device.
- 1 is a controller
- 2 is a noise reduction PWM generation circuit
- 3 is a switch count limiting circuit
- 4 is a current detection circuit
- 5 is a DC power supply
- 11 is a smoothing capacitor
- 1 and 1 3 is a voltage dividing capacitor
- 101 to 118 is a switching element
- 201 to 218 is a free wheel diode
- 301 to 306 is a clamp diode.
- FIG. 1 is a diagram illustrating a circuit example of a PWM inverter control method according to the first embodiment.
- FIG. 2 is a diagram showing a space vector of the inverter shown in FIG.
- FIG. 3 is a diagram showing a normal switching pattern of the inverter shown in FIG.
- FIG. 4 is a diagram showing a switching pattern in which the noise of the pattern shown in FIG. 3 is reduced.
- FIG. 5 is a diagram showing a switching pattern in which the inverter shown in FIG. 1 is reduced in noise and the number of times of switching is limited.
- FIG. 6 is a graph showing a switch count limit shown in FIG.
- FIG. 7 is a diagram showing skip frequency bands of the graph shown in FIG.
- 1 is a controller
- 2 is a noise reduction PWM generation circuit
- 3 is a switch count limiting circuit
- 4 is a current detection circuit
- 5 is a DC power supply
- 11 is a smoothing capacitor
- 101 to 106 Is a switching element
- 201 to 206 are free wheel diodes.
- FIG. 1 In a three-phase two-level PWM inverter as shown in Fig. 1, when a command is input from the controller 1, based on the spatial vector shown in Fig. 2 according to the command value, as shown in Fig. 3, Create a new PWM pulse pattern.
- Figure 2 Spatial vector symbol a, b, Op, and On correspond to the switching patterns of each phase U, V, and W shown in Fig. 3, and H indicates that the upper switching elements 101, 103, and 105 turn on.
- L indicates a state in which the lower switching elements 102, 104, and 106 are ON.
- the switching elements “101, 102” correspond to the U phase
- 105, 106” correspond to the W phase.
- the PWM pulse pattern is changed to a noise-reduced PWM switching pattern by the noise-reducing PWM generating circuit 2.
- the noise output concentrates on a specific frequency because the U, V, and W phases are evenly switched, but in the noise reduction pattern of Fig. 4, the output voltage While keeping the average value the same as in Fig. 3, the pattern is divided and rearranged, and the frequency is adjusted so as not to output a specific frequency (such as a frequency in the unpleasant audio band).
- the uniform pulse of the U-phase in Fig. 3 is re-arranged in the U-phase in Fig.
- the switching pattern whose noise has been reduced in this way is input to the switch count limiting circuit 3 to determine whether or not the set switch count is satisfied.
- a limit is set so that the number of switches does not exceed the set number of times in order to suppress heat generation due to switching loss. This limit may be set based on the characteristics of the switching element (IGBT, etc.) when designing the PWM inverter, or may be set by actual measurement based on the amount of heat generated under the conditions actually used. Is not set as a specific fixed value.
- the number of switches increases at the same time as the operating frequency increases.However, if the number of switches exceeds the set value as judged by the switch frequency limiting circuit 3, the frequency limiting function works as shown in Fig. Switches are limited.
- the PWM generation circuit 2 divides the PWM pattern in units of carrier cycles and the like so that the time-average number of times of switching remains constant. Switch by reducing the number or changing the distribution method Adjustments are made to reduce the number of times.
- Fig. 5 shows a noise reduction pattern in which the number of switches is limited.
- the period of T1 is the same as the pulse pattern shown in Fig. 4, but the period changes from T1 to T2 and the operating frequency changes. If rises, the pulse is reduced due to the limit of the number of switches.
- the number of switches in each control period is the same as that of FIG. 4 in which the T1 period is 11 times, but is reduced to 7 times in the T2 period.
- the number of switches is almost equalized in the overall time average, and the time average of the switching loss is kept below the set value ⁇ iit, thereby suppressing the heat generation of the switching element.
- the switch frequency is skipped as a process of the switch frequency limiting circuit 3 so that the resonance frequency of the motor connected as the load does not match the switch frequency of the output PWM pulse pattern. To process.
- FIG. 8 is a diagram illustrating a circuit example of a method of controlling a PWM inverter according to the second embodiment.
- FIG. 9 is a diagram showing the spatial vector of the inverter shown in FIG.
- FIG. 10 is a diagram showing a normal switching pattern of the inverter shown in FIG.
- FIG. 11 is a diagram showing a switching pattern in which the noise shown in FIG. 10 is reduced.
- Fig. 12 shows a switch in which the inverter shown in Fig. It is a figure showing a tuning pattern.
- Figure 8 shows an example of application to a three-phase three-level inverter, where 1 is a controller, 2 is a noise reduction PWM creation circuit, 3 is a switch count limiting circuit, 4 is a current detection circuit, 5 is a DC power supply, and 1 and 2 ⁇ 13 is a smoothing capacitor, 107 to 118 are switching elements (switching elements 107 to; L10 corresponds to U phase, 111 to 114 corresponds to phase, and 115 to 118 corresponds to W phase)
- Reference numerals 201 to 206 denote free wheel diodes, and reference numerals 301 to 310 denote clamp diodes for intermediate level output.
- the PWM vector that can be output is represented by a spatial vector diagram as shown in Fig. 9, and a general pulse pattern using this is shown in Fig. 10.
- the symbols in the space vector, a, b, ap, an, bp, bn, Op, On, and O o correspond to the switching patterns of each phase shown in Fig. 10, and H, 0, and L are H
- the switching element is ON
- O is the middle point where the capacitor-divided neutral point voltage is output
- the two switching elements are ON.
- L indicates the lower switching element is ON. .
- noise reduction PWM generation circuit 2 changes the pattern to a noise-reduced PWM switch pattern as shown in FIG.
- This noise reduction PWM pattern has the same time average as the normal uniform pattern shown in Fig. 10 and the time average of the voltage, and generates the noise reduction pattern shown in Fig. 11 by dividing and concentrating or dispersing the pulses. In addition, noise is dispersed and noise is reduced.
- the number of switches is limited by the switch number limiting circuit 3 so as not to exceed the number of switches set in order to suppress heat generation due to switching gloss, as shown in FIG.
- a switch frequency limiting pattern as shown in FIG. 12 is generated.
- the period of T1 is the same as that of Fig. 11, but the operating frequency rises and the switch count is limited.
- the number of switches is reduced and the number of pulse divisions is reduced. ing. Therefore, even if the operating frequency further increases, the number of divided PWM patterns is reduced.
- the switch pattern of each phase is rearranged so as to disperse the noise peaks,
- the switch pattern of each phase is rearranged so as to disperse the noise peaks
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03723402.8A EP1533887B1 (en) | 2002-06-12 | 2003-05-26 | Pwm inverter control method |
US10/517,658 US7042741B2 (en) | 2002-06-12 | 2003-05-26 | PWM inverter control method |
KR1020047018416A KR100812481B1 (ko) | 2002-06-12 | 2003-05-26 | Pwm 인버터 제어 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-171395 | 2002-06-12 | ||
JP2002171395A JP3864308B2 (ja) | 2002-06-12 | 2002-06-12 | Pwmインバータ制御方法 |
Publications (1)
Publication Number | Publication Date |
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WO2003107520A1 true WO2003107520A1 (ja) | 2003-12-24 |
Family
ID=29727806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/006538 WO2003107520A1 (ja) | 2002-06-12 | 2003-05-26 | Pwmインバータ制御方法 |
Country Status (7)
Country | Link |
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US (1) | US7042741B2 (ja) |
EP (1) | EP1533887B1 (ja) |
JP (1) | JP3864308B2 (ja) |
KR (1) | KR100812481B1 (ja) |
CN (1) | CN100418296C (ja) |
TW (1) | TW200404401A (ja) |
WO (1) | WO2003107520A1 (ja) |
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WO2006001169A1 (ja) * | 2004-06-25 | 2006-01-05 | Matsushita Electric Industrial Co., Ltd. | インバータ装置およびこれを搭載した車両用空調装置 |
JP4784207B2 (ja) * | 2004-11-18 | 2011-10-05 | パナソニック株式会社 | 直流電源装置 |
US20060268975A1 (en) * | 2005-05-13 | 2006-11-30 | Bors Douglas A | Pulse width modulation (PWM) utilizing a randomly generated pattern subsequently modified to create desired control characteristics |
KR100789441B1 (ko) * | 2005-12-30 | 2007-12-28 | 엘에스산전 주식회사 | 인버터의 전류 검출 장치 및 방법 |
JP5050395B2 (ja) * | 2006-04-24 | 2012-10-17 | 日産自動車株式会社 | 電力制御装置及び電力制御方法 |
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US7782005B2 (en) * | 2006-11-07 | 2010-08-24 | Nissan Motor Co., Ltd. | Power converter control |
JP5396948B2 (ja) * | 2009-03-17 | 2014-01-22 | 株式会社ジェイテクト | モータ制御装置及び電動パワーステアリング装置 |
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JP5742110B2 (ja) * | 2010-04-14 | 2015-07-01 | 日産自動車株式会社 | 電力変換装置 |
EP2590311A4 (en) * | 2010-09-29 | 2014-04-23 | Panasonic Corp | POWER CONVERTER APPARATUS |
JP5648654B2 (ja) * | 2012-04-23 | 2015-01-07 | 株式会社デンソー | 回転機の制御装置 |
CN102868291B (zh) * | 2012-09-19 | 2015-08-19 | 华为技术有限公司 | 二极管中点箝位型三电平逆变器限流控制方法及相关电路 |
KR101865954B1 (ko) * | 2012-09-21 | 2018-06-08 | 현대자동차주식회사 | 소음 저감을 위한 친환경 자동차의 인버터 제어 방법 |
US9379606B2 (en) * | 2013-05-30 | 2016-06-28 | Apple Inc. | Discrete narrow-band switching frequency avoidance of a switch mode power converter |
CN106208729B (zh) * | 2015-05-25 | 2020-01-21 | 松下知识产权经营株式会社 | 电力变换装置 |
JP7259608B2 (ja) * | 2018-08-01 | 2023-04-18 | 株式会社安川電機 | 電力変換装置及び制御方法 |
CN111220844A (zh) * | 2020-01-20 | 2020-06-02 | 东风汽车集团有限公司 | 一种非接触式的三相电流检测系统 |
CN113114061B (zh) * | 2021-03-26 | 2022-06-24 | 台达电子企业管理(上海)有限公司 | 变换器及抑制变换器的环流干扰的方法 |
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- 2002-06-12 JP JP2002171395A patent/JP3864308B2/ja not_active Expired - Lifetime
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2003
- 2003-05-26 KR KR1020047018416A patent/KR100812481B1/ko not_active IP Right Cessation
- 2003-05-26 CN CNB038135450A patent/CN100418296C/zh not_active Expired - Lifetime
- 2003-05-26 EP EP03723402.8A patent/EP1533887B1/en not_active Expired - Fee Related
- 2003-05-26 WO PCT/JP2003/006538 patent/WO2003107520A1/ja active Application Filing
- 2003-05-26 US US10/517,658 patent/US7042741B2/en not_active Expired - Lifetime
- 2003-06-12 TW TW092115998A patent/TW200404401A/zh not_active IP Right Cessation
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JPH0956195A (ja) * | 1995-06-08 | 1997-02-25 | Denso Corp | インバータ制御装置 |
JPH09182452A (ja) * | 1995-12-25 | 1997-07-11 | Mitsubishi Electric Corp | 3レベルインバータ装置 |
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See also references of EP1533887A4 * |
Also Published As
Publication number | Publication date |
---|---|
US20060067093A1 (en) | 2006-03-30 |
EP1533887B1 (en) | 2015-10-28 |
CN1659775A (zh) | 2005-08-24 |
US7042741B2 (en) | 2006-05-09 |
CN100418296C (zh) | 2008-09-10 |
JP2004023814A (ja) | 2004-01-22 |
EP1533887A1 (en) | 2005-05-25 |
TW200404401A (en) | 2004-03-16 |
KR100812481B1 (ko) | 2008-03-10 |
JP3864308B2 (ja) | 2006-12-27 |
KR20050003459A (ko) | 2005-01-10 |
EP1533887A4 (en) | 2008-07-02 |
TWI311005B (ja) | 2009-06-11 |
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