WO2003090277A1 - Circuit board, process for producing the same and power module - Google Patents
Circuit board, process for producing the same and power module Download PDFInfo
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- WO2003090277A1 WO2003090277A1 PCT/JP2003/005054 JP0305054W WO03090277A1 WO 2003090277 A1 WO2003090277 A1 WO 2003090277A1 JP 0305054 W JP0305054 W JP 0305054W WO 03090277 A1 WO03090277 A1 WO 03090277A1
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- circuit board
- conductive layer
- ceramic substrate
- insulating ceramic
- grain size
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12007—Component of composite having metal continuous phase interengaged with nonmetal continuous phase
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
- Y10T428/12576—Boride, carbide or nitride component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
Definitions
- the present invention relates to a power module, a circuit board used for the power module, and a method for manufacturing the same.
- this technology can be suitably applied to a power module for a highly reliable inverter module used in an HEV (Hybrid Electric Vehicle) or the like. Background technology.
- a conductive layer made of Cu or A1 and a heat radiating plate are formed on the front and back surfaces of a ceramic substrate such as alumina, veleria, silicon nitride, and aluminum nitride, respectively.
- Circuit boards are used. Such a circuit board is more stable in insulation than a composite board of a resin board and a metal board, or a resin board.
- the conductive layer and heat sink are made of Cu, thermal stress due to the difference in thermal expansion with the ceramic substrate and solder cannot be avoided, and long-term reliability tends to be insufficient.
- the conductive layer and the heat sink are A1, although they are inferior to Cu in heat conductivity and electric conductivity, they are easily plastically deformed when subjected to thermal stress, and the stress is relaxed. Therefore, reliability is high and there are advantages.
- the cause of the warpage is that the A 1 crystal in the conductive layer grows abnormally large in the brazing step, as shown in FIG. 3A. Crystal grain size is remarkably large This causes anisotropy in the mechanical properties of the conductive layers formed on both sides of the insulating ceramic substrate, and causes warpage due to stress imbalance.
- the thicknesses of the respective conductive layers are equal from the viewpoint of stress balance.
- the grain size of the A1 crystal can be suppressed by increasing the amount of the added element, but the stress relaxation effect decreases as the amount of the added element increases. For this reason, the 0.2% work hardening resistance index of 8.1 is larger than the reference value, and for example, when a temperature cycle test at 140 to 125 ° C is performed, there is a possibility that the ceramic substrate may crack. is there.
- the present invention has been made in view of the above circumstances, and has as its object to reduce the warpage of a circuit board and to prevent cracking of a ceramic substrate. Disclosure of the invention,
- a conductive layer is bonded to both surfaces of the insulating ceramic substrate, the conductive layer contains 99.98% by mass or more of aluminum, and has an average crystal grain size of 0.5 mm or more and 5 mm or less.
- the standard deviation ⁇ of the crystal grain size is less than 2 mm.
- the grain size of the conductive layer is determined by etching the surface of the conductive layer with an NaOH aqueous solution, HF, or Ga to expose the conductive layer's macrostructure, and then using an optical microscope or an electron microscope (SEM). It can be measured by observing.
- the conductive layer may contain at least 20 ppm of each of Cu, Fe, and Si, and may be rolled.
- the conductive layer may be rolled at a rolling reduction of 15% or more. In this case, the abnormal growth of the A1 crystal can be suppressed, and the effect of reducing the variation in crystal grain size can be obtained.
- the area of the crystal having the maximum crystal grain size may be 15% or less of the area of the insulating ceramic substrate. In this case, the effect of preventing the mechanical properties of the conductive layer from being anisotropic is further enhanced.
- Said insulating ceramic substrate A 1 2 ⁇ 3, A 1 N, and may be formed by one or even a few of S i 3 N 4.
- the conductive layer may be joined to the surface of the insulating ceramic substrate using a brazing material.
- the brazing filler metals are A1-Si, A1-Ge, A1-Mn, A1-Cu, A1-Mg, A1-Si-Mg, One or two or more brazing materials selected from A1-Cu-Mn-based and A1-Cu-Mg-Mn-based brazing materials. In this case, the bonding between the conductive layer and the insulating ceramic substrate is improved. '
- a power module according to the present invention includes the circuit board and a radiator plate that supports the circuit board. At least a part of the conductive layer of the circuit board may be joined to the heat sink with a brazing material having a lower melting point than the brazing material.
- a conductive layer containing 99.8% by mass or more of aluminum is disposed on an insulating ceramic substrate via a brazing material, and these are placed at 50 kPa or more.
- the conductive layer and the insulating ceramic substrate are heated by heating at 600 ° C. or more in a vacuum or an inert gas while being pressed against each other with a force of 300 kPa or less, so that the brazing material is used.
- the bonding is performed, the average crystal grain size of the conductive layer is 0.5 mm or more and 5 mm or less, and the standard deviation ⁇ of the crystal grain size is 2 mm or less.
- the manufacturing method further includes a step of obtaining a conductive layer by heat-treating a plate material containing 99.98% by mass or more of aluminum and then rolling it at a rolling reduction of 15% or more. You may. More the reduction ratio of the final heat treatment is more than 1 5% 0 of the conductive layer. 2% yield strength of 3 5 N / mm 2 approximately below the working hardness index of A 1 member 0. About 1 8 It can be: Therefore, the effect of preventing the ceramic substrate from being cracked when repeatedly exposed to the temperature change can be enhanced. For example, when a temperature cycle test of 140 ° C. to 125 ° C. is performed, the number of totals until the substrate cracks can be increased. The temperature cycle test is, for example, a test in which a circuit board is repeatedly subjected to a temperature treatment in which a cycle is performed at 140 ° C. for 30 minutes and 125 ° C. for 30 minutes using a thermal shock tester.
- the mechanical properties of the conductive layer are anisotropic. And the warpage of the circuit board can be reduced.
- the conductive layer contains 99.98% by mass or more of aluminum, it has a large stress relaxation ability, and is unlikely to crack the ceramic mix substrate even when exposed to a temperature change. Therefore, according to the present invention, it is possible not only to reduce the warpage of the circuit board, but also to prevent the ceramic board from having a problem such as cracking even when exposed to a temperature change.
- the mechanical properties of the conductive layer become anisotropic, and the substrate is likely to be warped. If the average crystal grain size is less than 0.5 mm, mechanical properties such as work hardening will increase and deformation resistance will increase when exposed to temperature changes, cracking of the ceramic substrate and soldering of semiconductor chips Cracks are more likely to occur in the damaged part. If the standard deviation of the crystal grain size is 2 mm or more, the variation in the crystal grain size of the conductive layer becomes too large, which may cause anisotropy in mechanical properties.
- the average crystal grain size of the conductive layer is 0.8 mm or more and 1.5 mm or less, and the standard deviation ⁇ of the crystal grain size is 1 mm or less. In this case, problems such as cracking of the ceramic substrate when exposed to a temperature change can be further prevented.
- FIG. 1 is a sectional view showing an embodiment of a circuit board according to the present invention.
- FIG. 2 is a cross-sectional view for explaining the amount of warpage.
- FIG. 3A and 3B are schematic diagrams for explaining the crystal grain size measurement.
- FIG. 3A shows an example of a crystal in the related art
- FIG. 3B shows the crystal in the conductive layer of the circuit board of the present invention.
- FIG. 3A shows an example of a crystal in the related art
- FIG. 3B shows the crystal in the conductive layer of the circuit board of the present invention.
- FIG. 4 is a sectional view showing an embodiment of the power module according to the present invention.
- FIG. 5 is a graph showing the relationship between the average crystal grain size and the temperature cycle life in the example according to the present invention.
- FIG. 6 is a graph showing the relationship between the ratio of the area of the largest crystal to the area of the ceramic substrate and the amount of warpage in the example according to the present invention.
- FIG. 7 is a graph showing the concentration distribution of Si diffused into the A1 plate after bonding.
- FIG. 1 is a cross-sectional view showing a circuit board 1 according to a first embodiment of the present invention.
- the circuit board 1 is provided on both sides of an insulating ceramic substrate 2 with a brazing material layer 4 interposed therebetween.
- Plate (conductive layer) 3 is joined.
- the material of the insulating ceramic substrate 2 is not limited, and preferably from one or two of the composite is selected from S i 3 N 4, A 1 N or A 1 2 0 3. Of these, A 1 N is particularly preferred.
- This A 1 N has a high thermal conductivity of 170 to 20 OW / mK, which is close to A 1 of the conductive layer, so that the heat of the Si chip mounted on the conductive layer is quickly radiated. be able to.
- the thickness of the insulating ceramic substrate 2 is not limited, but is, for example, about 0.3 to 1.5 mm.
- the shape of the insulating ceramic substrate 2 is generally rectangular, but may be other shapes.
- a 1 plate 3 Contains 99.98% or more of A 1 by mass. If the A1 content is lower than that, the stress relaxation effect of the A1 plate 3 is reduced, and the circuit substrate 1 is likely to warp and the ceramic substrate 2 to be cracked when exposed to a temperature change.
- the thickness of the A1 plate 3 is not limited, but is set to 0.25 to 0.6 mm as an example.
- the insulating ceramic substrate 2 is, for example, an A1N plate having a thickness of 0.635 mm, and the A1 plate 3 is, for example, 0.4 mm in thickness.
- the A 1 plate 3 may be joined to the entire surface of the ceramic substrate 2 or may be joined to only a part of the ceramic substrate 2. For example, as shown in FIG. 1, it may be formed only on a portion of the ceramic substrate 2 excluding the peripheral portion.
- the thickness of the brazing material 4 is not limited, but is, for example, 0.005 to 0.05 mm. A more specific example is about 0.03 mm.
- the material of the brazing material 4 is not limited, but is preferably A1-Si, A1-Ge, A1-Mn, A1-Cu, Al-Mg, or Al-S. One or more selected from i-Mg, Al-Cu-Mn, and Al-Cu-Mg-Mn brazing filler metals. All brazing materials have an A1 content of 70 to 98% by mass. Among these, A1-Si-based brazing filler metal or A1-Ge-based brazing filler metal is particularly preferred.
- A1-Si-based brazing filler metals and A1-Ge-based brazing filler metals are unlikely to produce intermetallic compounds, and when these intermetallic compounds are produced, the above-mentioned about 140 ° C to 125 ° C is considered. Cracks are likely to occur when the temperature cycle occurs. In addition, since intermetallic compounds are hardly generated, bonding can be performed under low pressure.
- a 1 Plate 3 has an average grain size of 0.5 mn!
- the standard deviation ⁇ of the crystal grain size is 2 mm or less. If the average crystal grain size is larger than 5 mm, the mechanical properties of the A1 plate 3 will be anisotropic, and the circuit board 1 may be warped when exposed to a temperature change. If the average crystal grain size is smaller than 0.5 mm, work hardening increases, deformation resistance due to temperature cycling increases, and cracks in ceramics and cracks in the Si chip soldering portion are liable to occur. If the standard deviation is 2 mm or more, the variation in crystal grain size becomes too large, and anisotropy may occur in the mechanical properties.
- the measurement of the crystal grain size of the A1 plate 3 can be performed as follows.
- the surface of the A1 plate 3 bonded to the insulating ceramic substrate 2 is etched to expose the opening of the conductive layer.
- As an etching solution a NaOH aqueous solution, HF, Ga, or the like can be used. After etching, wash with water and dry, and observe the structure of the crystal grains with an optical microscope or an electron microscope (SEM). Furthermore, as shown in Fig. 3B, image processing is performed on the microscope image to measure the average crystal grain size and the standard deviation. Similarly, the maximum grain size can be determined.
- An example of the image analysis method is as follows. First, the surface of the A1 plate 3 bonded to the ceramic substrate 2 is etched under any of the following conditions to produce a sample capable of observing the Mac mouth structure, that is, the grain boundary of A1.
- Etching conditions (1) For example, the surface of the A1 plate 3 is treated with hydrofluoric nitric acid (acid ammonium fluoride: 100 g / L, nitric acid 80 OmL / L) for 3 minutes.
- hydrofluoric nitric acid acid ammonium fluoride: 100 g / L, nitric acid 80 OmL / L
- Etching conditions (2) For example, the surface of A1 plate 3 is treated with a 4% by mass NaOH aqueous solution for 20 minutes.
- Etching conditions (3) Polish the surface of A1 plate 3, apply Ga, diffuse Ga at the grain boundary of A1 at 50 ° C for 2 hours, and then mirror-polish the surface.
- the average value and the standard deviation may be calculated from the distribution of the average particle size in the entire photograph.
- the ratio of the area of the crystal having the maximum crystal grain size to the area of the insulating ceramic substrate 2 is preferably 15% or less. In that case, the amount of warpage of the circuit board 1 can be reduced.
- the mechanical properties of the A1 plate 3 on both surfaces of the ceramic substrate 2 will be anisotropic, and the amount of warpage will increase.
- the mechanical properties of the A 1 plate 3 can be reduced in anisotropy, and the warpage of the circuit board 1 can be reduced.
- A1 plates 3 bonded to the front and back of the insulating ceramic substrate 2 have the same thickness.
- a 1 plate 3 is preferably bonded to both surfaces of insulating ceramic substrate 2. This is because if only one side is provided, the insulating ceramic substrate 2 is likely to be warped. However, only one side may be used if necessary.
- the A1 plate 3 preferably contains Cu, Fe, and Si in an amount of 20 ppm or more. In this case, excessive growth of the A1 crystal is suppressed, and variation in the crystal grain size is reduced, so that some of the crystal grains are unlikely to become coarse and cause mechanical anisotropy.
- Cu is 20 to 60 ppm
- Fe is 20 to 40 ppm
- Cu is 20 to 80 ppm.
- the sheet-shaped brazing material 4, the insulating ceramic substrate 2, the sheet-shaped brazing material 4, and the A1 plate 3 are stacked on the A1 plate 3 in this order. While applying a pressure of 50 to 300 kPa (0.5 to 3 kgf / cm 2 ) to them, at 600 ° C or higher and A1 plate in vacuum or in an inert gas (for example, in an Ar gas atmosphere) To a temperature below the melting point of As a result, the brazing material 4 is melted, and the ceramic substrate 2 and the A1 plate 3 are firmly joined. This The heating condition at the time of (1) is set so as to satisfy the crystal grain size condition described above. After brazing, it is cooled to room temperature, and the A1 plate 3 on one side is etched into a predetermined pattern to form a circuit.
- the ceramic substrate 2 is liable to crack at the time of bonding. If the heating temperature is lower than 600 ° C., the bonding tends to be insufficient. Further, when the content is out of the above range, it becomes difficult to satisfy the above-described condition of the crystal grain size.
- the circuit board 1 To measure the amount of warpage of the circuit board 1, take two points on the diagonal line of the 100 mm square circuit board 1 at intervals of 100 mm, and determine the cross-sectional curve between these two points with a three-dimensional measuring device or laser. Measure using a displacement meter. As shown in Fig. 2, the maximum displacement C of the distance between the cross-sectional curve and the plane P is measured. The larger of the values measured along each of the diagonal lines where the circuit board 1 intersects is defined as the amount of warpage.
- the crystal growth of the A1 plate 3 can be suppressed by increasing the added element, but the mechanical properties of A1 itself are significantly changed depending on the concentration of the added element, that is, the purity of A1.
- the A1 plate 3 is prepared by subjecting a plate material containing 99.8% or more of aluminum to a final heat treatment at 200 to 450 ° C, and It is preferably obtained by rolling under the above reduction. This gives A
- the stress relaxation effect can be improved, and it is possible to prevent the circuit board from cracking when a temperature cycle test of 140 ° C. to 125 ° C. is performed. Further, in the A1 plate 3, if the reduction ratio from the final heat treatment is 15% or more, the coarsening of the crystal grains does not easily progress.
- the insulating ceramics substrate 2 is formed from alumina, A 1 N, or Si 3 N 4 having a Young's modulus of about 320 GPa and requiring warpage suppression measures.
- the brazing filler metal 4 is required to be in a temperature range of 500 ° C. or higher, in which the growth of the crystal grains of the conductive layer occurs, and in particular, a heat treatment such as A 1—Si system which requires a heat treatment of 600 ° C. or higher. Even if it is used as a material, the average crystal grain size of A1 plate 3 is 0.5 mn!
- the anisotropy of the mechanical properties of the A1 plate 3 can be reduced. . Therefore, Reduces the occurrence of thermal stress due to the difference in thermal expansion between the insulating ceramic substrate 2 and the A1 plate 3, prevents the circuit board 1 from warping or cracking, and improves the long-term reliability of the circuit board It becomes possible.
- FIG. 4 is a sectional view of the power module 10.
- the power module 10 has one or two or more rectangular circuit boards 1 fixed to one main surface of a heat sink 11.
- Radiating plate 1 1 is a plate member made of A 1 alloy plate, similarly to the insulating ceramic substrate, high thermal conductivity (1 5 OWZmK least For example), a low thermal expansion coefficient (e.g. 10 X 10- 6 / (° C. or lower) is preferable, and a material composed of A 1 SiC or a three-layer structure in which A1 is bonded to both surfaces of a perforated Fe-Ni alloy plate is preferable.
- the thickness of the heat sink 11 is not limited, but a thickness of 3 to 1 Omm is used as an example.
- the circuit board 1 is the same as that of the first embodiment described above.
- the circuit board 1 includes an insulating ceramic substrate 2 made of A 1 N or the like and having a thickness of, for example, 0.3 to 1.5 mm, and both surfaces of the insulating ceramic substrate 2. It comprises first and second A1 plates 3 joined together. The first and second A1 plates 3 have a thickness of, for example, 0.25 to 0.6 mm.
- the circuit board 1 has, for example, a rectangular shape with one side of 3 Omm or less.
- the circuit board 1 is brazed to the heat sink 11 with a brazing material.
- a brazing material it is preferable to use one or more selected from brazing materials of AI-Si type, Al_Cu type, 1-] ⁇ 1 ⁇ type, A1-Mn type and AI-Ge type. .
- To braze the circuit board 1 to the heat sink 1 place a sheet of brazing material and the circuit board 1 on the heat sink 1 1 in this order, apply a pressure of 50 to 300 kPa, and apply vacuum. Heat to 580-650 ° C in medium or inert gas to melt the braze and then cool.
- the melting point is preferably lower than the melting point of the brazing material 4, more preferably 500 to 630 ° C, for example, about 575 ° C (however, the melting point is a point exceeding the liquidus line. And).
- the heat dissipating plate 11 and the first A1 plate 3 can be joined without completely melting the brazing material 4 joining the insulating ceramic substrate 2 and the A1 plate 3.
- the male screw 13 is inserted into the mounting hole 11 a formed in the corner of the heat sink 11, and the male screw 13 is formed into the female screw formed in the water-cooled heat sink 14.
- the other surface of the heat sink 11 is tightly joined to a water-cooled heat sink 14 made of, for example, an A1 alloy by being screwed into each of the heat sinks 14a.
- the power module 10 configured as described above has the same effects as the first embodiment.
- the difference in the amount of shrinkage at the edge of the circuit board 1 that occurs during a thermal cycle can be suppressed to a relatively small amount, and the thermal cycle life of the power module 10 can be extended. As a result, the reliability as a power module can be improved.
- a power module having the structure shown in Fig. 4 was created.
- A1 plate 3 was rolled at a rolling reduction of 30% after the final heat treatment at 450 ° C, and 99.9% by mass of Cu, 23 ppm of Cu and 30 ppm of Si, 33 ppm Fe was contained.
- Lowe material 4 A 1 containing S i of 8 mass 0/0 - was S i based brazing material. The melting point of this brazing material was 626 ° C.
- AI plate 3 A1—Si-based brazing material 4, insulating ceramic substrate 2, A1—Si-based brazing material 4, A1 Plate 3 stacked in this order, pressure 200 kP These were joined by heating to 60 ° C. in a vacuum while adding a, and cooling after elapse of 10 minutes.
- Example 1 a heat sink 11 made of A 1 SiC of 100 mm X 10 Omm X 3 mm and a Si chip 16 are prepared, and a circuit board 1, a heat sink 11 and a Si chip are prepared.
- the power module 10 was obtained by brazing 16 with solder. 30 power modules thus obtained were prepared and used as samples of Example 1. ⁇ Examples 2 to 12 and Comparative Examples 1 to 6>
- the aim of the present invention is to determine the Cu content in Comparative Example 1, the Si content in Comparative Example 2, the Fe content in Comparative Example 3, the final rolling reduction in Comparative Example 4, and the A1 purity in Comparative Example 5. Created out of the range.
- the A1 plate was joined to only one surface of the insulating ceramic substrate. The surface of the A1 plate 3 of each of Examples 1 to 12 and Comparative Examples 1 to 6 was etched with a 2 to 5% NaOH aqueous solution to expose a macrostructure, and the surface was observed with an electron microscope (SEM).
- the structure of the crystal having the average crystal grain size, the standard deviation, the maximum crystal grain size, and the maximum crystal grain size contained in the conductive layer occupies the area of the insulating ceramic substrate 2 by image observation by observing the structure of the crystal grains. The proportion was measured. Regarding the crystal grain size, the area (S) of the crystal grain was measured, and this was divided by the pi ( ⁇ ), and the radius was calculated from the square root of the area, which was doubled (2 X (SZT)). The results are shown in Table 1.
- Example 1 AIN AI-8wt% Si 30% 99.99% 23ppm 30ppm 33ppm 2.9 0.7 4.0
- Example 2 AIN Ai-8wt% Si 30% 99.98% 80ppm 35ppm 39ppm 1.9 0.7 3.1
- Example 3 AIN AI-8wt% Si 30% 99.98% 80ppm 35ppm 39ppm 2.0 1.0 4.0
- Example 4 Alumina AI-8wt Si 30% 99.98% 80ppm 35ppm 39ppm 1.8 0.9 3.2
- Example 6 Si A AI-4wt% Si 30% 99.98% 80ppm 35ppm 39ppm 2.3 0.9 3.7
- Example 7 AIN AI-8wt Si 15% 99.98% 20ppm 60ppm 40ppm 3.4 1.1 4.6 QQ QQ0 / N
- the power modules of Examples 1 to 12 and Comparative Examples 1 to 6 were set in a thermal shock tester, and the temperature was set at 40 ° C. for 30 minutes, room temperature for 30 minutes, 125 ° C. for 30 minutes, and The heat treatment was repeated at room temperature X 30 minutes as one cycle. At the point when the temperature cycle was repeated 100 times, the presence or absence of peeling between the circuit board 1 and the heat sink 11 and between the insulating ceramic substrate 2 and the A1 plate 3 was observed, and peeling was confirmed. If not, the temperature was repeated 100 times more. This process was repeated, and the number of temperature cycles until peeling was confirmed was measured as the temperature cycle life. The presence or absence of peeling was confirmed by checking with a magnifying glass. Table 2 shows the results.
- the amount of warpage was measured for each circuit board 1, and out of the 30 pieces, the number of defects that occurred during the manufacturing process after joining the A1 board 3 was counted.
- the number of failures is the number of power modules that have failed in the circuit board manufacturing process or in the assembly process of manufacturing a power module using this insulated circuit board.
- Defects are, specifically, the large amount of warpage, which may cause the ceramic substrate to crack on the adsorption stage for fixing the substrate during the resist printing process for forming the circuit pattern, or warp during heat sink soldering. For example, solder voids may be generated. Table 2 shows these results.
- Example 1 46 0/30 Good for 3000 cycles or more
- Example 2 32 0/30 Good for 3000 cycles or more
- Example 3 40 0/30 Good for 3000 cycles or more
- Example 4 38 0/30 Good for 3000 cycles or more
- Example 5 39 0/30 Good for 3000 cycles or more
- Example 6 48 0/30 Good for 3000 cycles or more
- Example 7 35 0/30 Good for 3000 cycles or more
- Example 8 33 0/30 Good for 3000 cycles or more
- Example 9 40 0/30 Good for 3000 cycles or more
- Example 10 45 0/30 Good for 3000 cycles or more
- Example 1 1 48 0/30 Good for 3000 cycles or more
- Example 12 48 0/30 Good for 3000 cycles or more
- Comparative Example 1 305 5/30 The solder between the insulated circuit board and the heat sink cracked in 1500 cycles.
- Comparative Example 2 213 3/30 Solder between insulated circuit board and heat sink cracked in 1500 cycles.
- Comparative Example 3 195 3/30 The solder between the insulated circuit board and the heat sink cracked in 1500 cycles.
- Comparative Example 4 50 3/30 Solder between the insulated circuit board and the heat sink cracked in 1500 cycles.
- Comparative Example 5 225 4/30 Table of insulated circuit board Peeled off at the interface between AI and ceramics in 500 cycles. Comparative Example 6 315 4/30 Solder between insulated circuit board and heat sink cracked in 1500 cycles.
- FIG. 5 shows the relationship between the average crystal grain size obtained by the experiment and the temperature cycle life. From FIG. 5, it can be seen that when the average crystal grain size is smaller than 0.5, the temperature cycle life is extremely short, 3100 times or less. In addition, when the average crystal grain size of the conductive layer is in the range of 0.8 mm or more and 1.5 mm or less, the temperature cycle life is very long at about 5000 times, which is clear.
- FIG. 6 shows the relationship between the ratio of the area of the crystal having the maximum crystal grain size contained in the conductive layer to the area of the insulating ceramic substrate and the amount of warpage. From Fig. 6, it can be seen that when the maximum grain size exceeds 15% of the entire substrate, the warpage of the substrate per 50 mm rapidly increases to 120 ⁇ m or more.
- Fig. 7 is a graph showing the relationship between the distance X from the bonded interface of A1 / A1N into the A1 plate and the Si concentration. As shown in this graph, the diffusion depth of Si was about 0.1 mm from the A1 / A1N junction interface. Therefore, by performing elemental analysis on the surface layer of the A1 sheet (for example, in the range of about 0.1 mm in thickness), the composition of the A1 sheet itself can be measured without being affected by Si diffusion from the brazing material. can do. Therefore, microanalysis such as Si: 20 to 60 ppm, Fe: 20 to 40 ppm, and Cu: 20 to 80 ppm is sufficiently possible.
- the present invention it is possible not only to reduce the warpage of the circuit board, but also to prevent the ceramic substrate from being broken or the like even when exposed to a temperature change.
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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AT03723156T ATE552717T1 (de) | 2002-04-19 | 2003-04-21 | Leiterplatte, prozess zu ihrer herstellung und stromversorgungsmodul |
JP2003586934A JP4241397B2 (ja) | 2002-04-19 | 2003-04-21 | 回路基板の製造方法 |
US10/510,199 US7128979B2 (en) | 2002-04-19 | 2003-04-21 | Circuit board, method of producing same, and power module |
EP03723156A EP1498946B1 (en) | 2002-04-19 | 2003-04-21 | Circuit board, process for producing the same and power module |
AU2003235329A AU2003235329A1 (en) | 2002-04-19 | 2003-04-21 | Circuit board, process for producing the same and power module |
Applications Claiming Priority (4)
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JP2002118359 | 2002-04-19 | ||
JP2002-118359 | 2002-04-19 | ||
JP2003088129 | 2003-03-27 | ||
JP2003-88129 | 2003-03-27 |
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WO2003090277A1 true WO2003090277A1 (en) | 2003-10-30 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/005054 WO2003090277A1 (en) | 2002-04-19 | 2003-04-21 | Circuit board, process for producing the same and power module |
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US (1) | US7128979B2 (ja) |
EP (1) | EP1498946B1 (ja) |
JP (1) | JP4241397B2 (ja) |
CN (1) | CN100364078C (ja) |
AT (1) | ATE552717T1 (ja) |
AU (1) | AU2003235329A1 (ja) |
WO (1) | WO2003090277A1 (ja) |
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JP2013243181A (ja) * | 2012-05-18 | 2013-12-05 | Showa Denko Kk | 電子素子搭載用基板 |
CN103739208B (zh) * | 2013-12-17 | 2016-05-18 | 佛山市粤峤陶瓷技术创新服务中心 | 一种具有导电玻璃层的微晶玻璃陶瓷复合板的制造方法 |
CN103739208A (zh) * | 2013-12-17 | 2014-04-23 | 佛山市粤峤陶瓷技术创新服务中心 | 一种具有导电玻璃层的微晶玻璃陶瓷复合板的制造方法 |
JP2015185647A (ja) * | 2014-03-24 | 2015-10-22 | 三菱マテリアル株式会社 | パワーモジュール用基板及びその製造方法 |
KR20170024578A (ko) | 2014-06-30 | 2017-03-07 | 미쓰비시 마테리알 가부시키가이샤 | 세라믹스/알루미늄 접합체의 제조 방법, 파워 모듈용 기판의 제조 방법, 및 세라믹스/알루미늄 접합체, 파워 모듈용 기판 |
US10573577B2 (en) | 2014-06-30 | 2020-02-25 | Mitsubishi Materials Corporation | Method for producing ceramic-aluminum bonded body, method for producing power module substrate, ceramic-aluminum bonded body, and power module substrate |
JP2016108636A (ja) * | 2014-12-10 | 2016-06-20 | 昭和電工株式会社 | モジュール基板用クラッド板及びモジュール基板 |
KR20180077170A (ko) | 2015-11-06 | 2018-07-06 | 미쓰비시 마테리알 가부시키가이샤 | 세라믹스/알루미늄 접합체, 파워 모듈용 기판, 및 파워 모듈 |
US10607907B2 (en) | 2015-11-06 | 2020-03-31 | Mitsubishi Materials Corporation | Ceramic-aluminum conjugate, power module substrate, and power module |
CN110226363A (zh) * | 2017-03-30 | 2019-09-10 | 株式会社东芝 | 陶瓷铜电路基板及使用了其的半导体装置 |
CN110226363B (zh) * | 2017-03-30 | 2022-08-02 | 株式会社东芝 | 陶瓷铜电路基板及使用了其的半导体装置 |
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Publication number | Publication date |
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EP1498946A1 (en) | 2005-01-19 |
US20050214518A1 (en) | 2005-09-29 |
EP1498946A4 (en) | 2009-06-03 |
ATE552717T1 (de) | 2012-04-15 |
AU2003235329A1 (en) | 2003-11-03 |
US7128979B2 (en) | 2006-10-31 |
JPWO2003090277A1 (ja) | 2005-09-02 |
JP4241397B2 (ja) | 2009-03-18 |
CN100364078C (zh) | 2008-01-23 |
EP1498946B1 (en) | 2012-04-04 |
CN1647267A (zh) | 2005-07-27 |
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