WO2003061004A3 - Procede pour coder et authentifier des circuits de semi-conducteurs - Google Patents

Procede pour coder et authentifier des circuits de semi-conducteurs Download PDF

Info

Publication number
WO2003061004A3
WO2003061004A3 PCT/DE2003/000080 DE0300080W WO03061004A3 WO 2003061004 A3 WO2003061004 A3 WO 2003061004A3 DE 0300080 W DE0300080 W DE 0300080W WO 03061004 A3 WO03061004 A3 WO 03061004A3
Authority
WO
WIPO (PCT)
Prior art keywords
authenticating
coding
semiconductor circuits
chip
measurement
Prior art date
Application number
PCT/DE2003/000080
Other languages
German (de)
English (en)
Other versions
WO2003061004A2 (fr
Inventor
Ralf Brederlow
Astrid Elbe
Franz Kreupl
Johannes Luyken
Robert Neuhauser
Christian Paulus
Joerg Schepers
Roland Thewes
Original Assignee
Infineon Technologies Ag
Ralf Brederlow
Astrid Elbe
Franz Kreupl
Johannes Luyken
Robert Neuhauser
Christian Paulus
Joerg Schepers
Roland Thewes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Ralf Brederlow, Astrid Elbe, Franz Kreupl, Johannes Luyken, Robert Neuhauser, Christian Paulus, Joerg Schepers, Roland Thewes filed Critical Infineon Technologies Ag
Publication of WO2003061004A2 publication Critical patent/WO2003061004A2/fr
Publication of WO2003061004A3 publication Critical patent/WO2003061004A3/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nanotechnology (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Une propriété électrique d'une couche de matériau (3) ou d'une structure de matériau stratifiée est mesurée en plusieurs emplacements dotés de contacts de raccordements (5, 6). Une valeur moyenne de mesure prise sur un ensemble de puces à circuits intégrés est soustraite d'une valeur donnée, et à partir du résultat ainsi obtenu, un mot numérique est formé pour chaque puce à circuits intégrés, afin d'identifier la puce concernée. Cette mesure peut être réalisée par corrélation croisée, selon laquelle les zones de mesure sont disposées en croix.
PCT/DE2003/000080 2002-01-17 2003-01-13 Procede pour coder et authentifier des circuits de semi-conducteurs WO2003061004A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10201645.3 2002-01-17
DE2002101645 DE10201645B4 (de) 2002-01-17 2002-01-17 Verfahren zur Codierung und Authentifizierung von Halbleiterschaltungen

Publications (2)

Publication Number Publication Date
WO2003061004A2 WO2003061004A2 (fr) 2003-07-24
WO2003061004A3 true WO2003061004A3 (fr) 2004-07-29

Family

ID=7712397

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/000080 WO2003061004A2 (fr) 2002-01-17 2003-01-13 Procede pour coder et authentifier des circuits de semi-conducteurs

Country Status (3)

Country Link
DE (1) DE10201645B4 (fr)
TW (1) TW200302353A (fr)
WO (1) WO2003061004A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023363B1 (en) * 2005-02-17 2006-04-04 Saiful Bahari Saidan Position encoding using impedance comparison
US8143705B2 (en) 2007-08-02 2012-03-27 Nxp B.V. Tamper-resistant semiconductor device and methods of manufacturing thereof
EP2665094A1 (fr) 2012-05-15 2013-11-20 Nxp B.V. CI inviolable

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6460110A (en) * 1987-08-31 1989-03-07 Toshiba Corp Code identifying circuit
EP0404985A1 (fr) * 1989-06-29 1991-01-02 Siemens Aktiengesellschaft Circuit pour l'identification de circuits intégrés à semiconducteur
EP0893705A2 (fr) * 1997-07-04 1999-01-27 Integrated Detector & Electronics AS Procédé et système pour la lecture de signal de données émis par un capteur à pixel actif
US5881155A (en) * 1996-04-01 1999-03-09 Schlumberger Industries Security device for a semiconductor chip
JP2000068833A (ja) * 1998-08-21 2000-03-03 Meidensha Corp ディジタルフィルタ方式
US6047068A (en) * 1995-09-19 2000-04-04 Schlumberger Industries Method for determining an encryption key associated with an integrated circuit
US6161213A (en) * 1999-02-17 2000-12-12 Icid, Llc System for providing an integrated circuit with a unique identification
DE10025213A1 (de) * 1999-06-24 2001-01-18 Mitsubishi Electric Corp Halbleitereinrichtung

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3736882C2 (de) * 1987-10-30 1997-04-30 Gao Ges Automation Org Verfahren zur Echtheitsprüfung eines Datenträgers mit integriertem Schaltkreis
US6459095B1 (en) * 1999-03-29 2002-10-01 Hewlett-Packard Company Chemically synthesized and assembled electronics devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6460110A (en) * 1987-08-31 1989-03-07 Toshiba Corp Code identifying circuit
EP0404985A1 (fr) * 1989-06-29 1991-01-02 Siemens Aktiengesellschaft Circuit pour l'identification de circuits intégrés à semiconducteur
US6047068A (en) * 1995-09-19 2000-04-04 Schlumberger Industries Method for determining an encryption key associated with an integrated circuit
US5881155A (en) * 1996-04-01 1999-03-09 Schlumberger Industries Security device for a semiconductor chip
EP0893705A2 (fr) * 1997-07-04 1999-01-27 Integrated Detector & Electronics AS Procédé et système pour la lecture de signal de données émis par un capteur à pixel actif
JP2000068833A (ja) * 1998-08-21 2000-03-03 Meidensha Corp ディジタルフィルタ方式
US6161213A (en) * 1999-02-17 2000-12-12 Icid, Llc System for providing an integrated circuit with a unique identification
DE10025213A1 (de) * 1999-06-24 2001-01-18 Mitsubishi Electric Corp Halbleitereinrichtung

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 270 (E - 776) 21 June 1989 (1989-06-21) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 06 22 September 2000 (2000-09-22) *
WIJARANAKULA W ET AL: "A FORMATION OF CRYSTAL DEFECTS IN CARBON-DOPED CZOCHRALSKI-GROWN SILICON AFTER A THREE-STEP INTERNAL GETTERING ANNEAL", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, VOL. 138, NR. 7, PAGE(S) 2153-2159, ISSN: 0013-4651, XP000293484 *

Also Published As

Publication number Publication date
WO2003061004A2 (fr) 2003-07-24
TW200302353A (en) 2003-08-01
DE10201645A1 (de) 2003-08-07
DE10201645B4 (de) 2007-04-26

Similar Documents

Publication Publication Date Title
SG81960A1 (en) Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument
DE60233902D1 (de) Stapelbare schichten die eingekapselte integrierte schaltungschips mit einer oder mehreren darüberliegenden verbindungsschichten beinhalten und verfahren zu deren herstellung
EP1043772A3 (fr) Procédé d'empaquetage et de montage d'un dispositif semiconducteur et dispositif ainsi obtenu
WO2004015771A3 (fr) Dispositif a semi-conducteurs et son procede de fabrication
AU2001249659A1 (en) Method of forming vias in silicon carbide and resulting devices and circuits
TW200514212A (en) Method and apparatus for packaging integrated circuit devices
EP1032041A3 (fr) Dispositif semiconducteur comprenant une configuration de conducteurs internes
WO2003041158A3 (fr) Dispositif de conditionnement pour semi-conducteurs ; fabrication et essai
TW200625587A (en) Semiconductor structure comprising a stress sensitive element and method of measuring a stress in a semiconductor structure
WO2002051217A3 (fr) Circuits integres sous boitier et procedes de production de ceux-ci
TW200605279A (en) Semiconductor device and manufacturing method thereof
WO2003041157A3 (fr) Dispositifs en carbure de silicium de grande surface et procedes de fabrication associes
TW357423B (en) Substrate for burn-in test of an IC chip and method of manufacturing a known good die utilizing the substrate the invention relates to a substrate for burn-in test of an IC chip and method of manufacturing a known good die using the substrate
WO2004012226A3 (fr) Procede de fabrication de film polymere conducteur anisotrope sur tranche de semi-conducteur
WO1999066337A3 (fr) Dispositif pour mesurer et analyser des signaux electriques d'un circuit integre
TW200625476A (en) Semiconductor device and manufacturing method thereof
MX2007003615A (es) Circuito integrado y metodo de fabricacion.
EP1458022A3 (fr) Composant semi-conducteur et son procédé de fabrication, substrat semiconducteur, carte à circuit et appareil électronique
EP1248297A3 (fr) Elément inductif et dispositif sémiconducteur
DE60231232D1 (de) Anisotrop elektroleitfaehiger klebefilm, verfahren zu seiner herstellung und halbleitervorrichtungen
EP1294017A3 (fr) Méthode de fabrication de puces pour sectionner des plots de contact de test par sectionner des puces à circuits sur la tranche
WO2003061004A3 (fr) Procede pour coder et authentifier des circuits de semi-conducteurs
WO2003073506A3 (fr) Porte-puce a circuit integre modulaire
WO2004015773A3 (fr) Plaquette a semiconducteurs comportant des surfaces de contact et de controle electriquement connectees
SG105545A1 (en) Voltage measuring method, electrical test method and apparatus, semiconductor device manufacturing method and device substrate manufacturing method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): BR CA CN IL IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP