WO2003052828A1 - Dispositif a semi-conducteur - Google Patents

Dispositif a semi-conducteur Download PDF

Info

Publication number
WO2003052828A1
WO2003052828A1 PCT/JP2001/010990 JP0110990W WO03052828A1 WO 2003052828 A1 WO2003052828 A1 WO 2003052828A1 JP 0110990 W JP0110990 W JP 0110990W WO 03052828 A1 WO03052828 A1 WO 03052828A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
data line
write
semiconductor device
transistor
Prior art date
Application number
PCT/JP2001/010990
Other languages
English (en)
Japanese (ja)
Inventor
Takeshi Sakata
Hideyuki Matsuoka
Kiyoo Itoh
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2003553626A priority Critical patent/JP4461804B2/ja
Priority to PCT/JP2001/010990 priority patent/WO2003052828A1/fr
Publication of WO2003052828A1 publication Critical patent/WO2003052828A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device including a high-speed, highly-integrated, and highly-reliable memory using a memory cell that stores information using a change in magnetoresistance.
  • MRAM magnetic resistive 'random access memory'
  • SAM statistical random access memory
  • DRAM dynamic random access memory
  • FIG. 2 shows a basic configuration of a memory cell array used in Reference 2.
  • memory cells MC00, COL, MC02, MC0, MC10, MC11, MC12, MCL, ..., C20, MC21, C22, C23, MC30, MC.'H, MC2, i ⁇ 'IC, ..., ... are provided.
  • MTJ element consists of one MTJ element and one transistor M.
  • the MTJ element MTJ has a fixed layer of ferromagnetic material whose magnetization direction is fixed in normal operation, and the magnetization direction can be reversed by a write operation The resistance between the two terminals of this MTJ element varies depending on the direction of magnetization in the two ferromagnetic layers.
  • the read operation is performed as shown in Figure 3. That is, RO, WRl, WR2, WR3,...
  • the transistor MT is turned on in the transistor, and a voltage is applied to the terminals of the MT J element MT.J.
  • D is 0, DL1, DL2, DL3,...
  • the stored information is read out by detecting the current IDL flowing through the desired data line.
  • the write operation is performed as shown in FIG.
  • the current IWW of the write mode line selected among WW0, WW1, WW2, WW3,... Is defined as the write mode current IWS, and the data lines of DL0, DLL, DL2, DL3,.
  • the current is set to a positive write current IDi or a negative ID0 according to the write data to generate a magnetic field.
  • the magnetization resistance change MR which is the ratio of the increase in resistance in the high resistance state to the low resistance state of the MTJ element, exhibits hysteresis characteristics.
  • the magnetization reversal of the MTJ element is likely to occur, and the hysteresis characteristic is narrow with respect to the data line current IDL that generates the easy axis magnetic field.
  • the memory cell selected by the write word line WW can be magnetized and the storage information can be written.
  • This disturb problem is not related to a memory cell consisting of ⁇ MTJ elements MTJ and one transistor MT, but to a memory cell using an MTJ element (spin-to-tunnelling element). It is described in reference 3. There, the MTJ element and 0. 2 / m square, if the space between 0. 2 4 mu m, it is shown that would occur magnetization reversal in the adjacent MTJ element.
  • Reference 3 as a countermeasure, a flux that confines magnetization '' closure keeper It has been proposed to provide a process, but the number of processes will increase, and the compatibility between the material and the semiconductor process will be a problem.
  • Reference 4 discloses a method of reducing disturbance to adjacent cells at the time of writing in a MAM using a memory cell using a giant's magneto-resistance (GMR) element. Since the GMR element has a smaller MR ratio than the MTJ element, the readout signal is small and high-speed stable operation is difficult. To realize a highly integrated MRAM with sufficient performance, a memory cell composed of MTJ elements and transistors, as shown in Ref. 1 or Ref. 2, is promising. Reference 4 does not describe measures against disturb in the memory cell structure.
  • GMR giant's magneto-resistance
  • an object of the present invention is to provide a highly reliable and highly integrated MRAM with a large read signal, small disturbance to adjacent cells at the time of writing. Disclosure of the invention
  • a plurality of write Wado line Thus 0 flowing representative if Shimese a configuration selected c during writing as follows current of the semiconductor device according to, ⁇ and WW2, WW3, ... and, intersects the plurality of word lines
  • a large number of memory cells, including the MTJ element MTJ and the transistor ⁇ , are arranged in a checker pattern for a plurality of data lines DL0, DL1, DL2, DL3,... that are selected at the time of writing and carry current according to the write data.
  • c is desirable to have the placed MRAM Seruarei, the MTJ element is provided question between the write word line and the data line, one end of which is connected to the data line, the other end is connected to the drain of the Bok Rungis data You.
  • the gates of the above transistors are connected to a plurality of read mode lines WR0, WR1, WR2, WR3,... Provided corresponding to the plurality of write mode lines.
  • the source of the transistor is connected to a source line arranged in substantially the same direction as the data line.
  • a dimension in a direction perpendicular to the data line is larger than a dimension in a direction perpendicular to the word line.
  • the MTJ element and the transistor are arranged for every two write lead lines of the transistor.
  • FIG. 1 is a diagram showing a configuration of a memory cell array according to the first embodiment.
  • FIG. 2 is a diagram showing a configuration example of a conventional MRAM memory cell array.
  • FIG. 3 is a diagram showing a read operation of the MRAM cell.
  • FIG. 4 is a diagram showing a write operation of the MRAM cell.
  • FIG. 5 is a diagram showing a layout of the MTJ element of the first embodiment.
  • FIG. 6 is a diagram showing a layout of the transistor of the first embodiment.
  • FIG. 7 is a diagram showing the structure of a section taken along the line AA ′ in FIGS. 5 and 6.
  • FIG. 8 is a diagram showing the structure of a section taken along the line BB ′ of FIGS. 5 and 6.
  • FIG. 9 is a diagram illustrating a configuration example of a memory.
  • FIG. 10 is a diagram showing the operation of the memory of FIG.
  • FIG. 11 is a diagram illustrating the configuration of the memory cell array according to the second embodiment.
  • FIG. 12 is a diagram showing a layout of the MTJ element of the second embodiment.
  • FIG. 13 is a diagram showing a layout of the transistor of the second embodiment.
  • FIG. 14 is a diagram showing the structure of a section taken along the line AA ′ of FIGS. 12 and 3.
  • FIG. 15 is a diagram showing a structure of a section taken along the line BB ′ of FIGS. 12 and 13.
  • FIG. 16 is a diagram showing the configuration of the memory cell array according to the third embodiment.
  • FIG. 17 is a diagram showing a layout of the MTJ element of the third embodiment.
  • FIG. 18 is a diagram showing the layout of the transistor of the third embodiment.
  • FIG. 19 is a diagram showing the structure of a section taken along the line AA ′ of FIGS. 17 and 18.
  • FIG. 20 is a diagram showing a structure of a section taken along line BB ′ of FIGS. 17 and 18.
  • FIG. 21 is a diagram showing the configuration of the memory cell array according to the fourth embodiment.
  • FIG. 22 is a diagram showing a layout of the MTJ element of the fourth embodiment.
  • FIG. 23 is a diagram showing a layout of the transistor of the fourth embodiment.
  • FIG. 24 is a diagram showing a structure of a section taken along the line AA ′ of FIGS. 22 and 23.
  • FIG. 25 is a diagram showing a structure of a cross section taken along line BB ′ of FIGS. 22 and 23.
  • FIG. 26 is a diagram showing the configuration of the memory cell array of the fifth embodiment.
  • FIG. 27 is a diagram illustrating a read operation of the MRAM cell of the fifth embodiment.
  • FIG. 28 is a diagram showing a write operation of the MRAM cell of the fifth embodiment.
  • FIG. 29 is a diagram showing a layout of the MTJ element of the fifth embodiment.
  • FIG. 30 is a diagram showing a layout of the transistor according to the fifth embodiment.
  • FIG. 31 is a diagram showing a structure of a cross section taken along line BB ′ of FIGS. 29 and 30.
  • FIG. 32 is a diagram showing the configuration of the memory cell array of the sixth embodiment.
  • FIG. 33 is a diagram showing a layout of the MTJ element of the sixth embodiment.
  • FIG. 34 is a diagram showing a layout of the transistor of the sixth embodiment.
  • FIG. 35 is a diagram showing the structure of a section taken along the line II-II of FIGS. 33 and 34.
  • FIG. 36 is a diagram showing the structure of the section taken along line BB ′ of FIGS. 33 and 34.
  • FIG. 37 is a diagram showing the configuration of the memory cell array of the seventh embodiment.
  • FIG. 38 is a diagram showing a layout of the MTJ element of the seventh embodiment.
  • FIG. 39 is a diagram showing a layout of the transistor according to the seventh embodiment.
  • FIG. 40 is a diagram showing the structure of the section taken along the line AA ′ in FIGS. 38 and 39.
  • FIG. 4 is a diagram showing the structure of the section taken along line BB ′ of FIGS. 38 and 39.
  • FIG. 42 is a diagram showing the configuration of the memory cell array according to the eighth embodiment.
  • FIG. 43 is a diagram showing a read operation of the MRAM cell of the eighth embodiment.
  • FIG. 44 is a diagram showing a write operation of the MRAM cell of the eighth embodiment.
  • FIG. 45 is a diagram showing a layout of the MTJ element according to the eighth embodiment.
  • FIG. 46 is a diagram showing a layout of the transistor according to the eighth embodiment.
  • FIG. 47 is a diagram showing a structure of a section taken along the line AA ′ of FIGS. 45 and 46.
  • FIG. 48 is a diagram showing a structure of a section taken along line BB ′ of FIGS. 45 and 46.
  • FIG. 49 is a diagram showing a layout of the MTJ element of the ninth embodiment.
  • FIG. 50 is a diagram showing the structure of the section taken along line BB ′ of FIG. 49.
  • FIGS. 51 and 52 are diagrams showing the write operation of the MRAM cell of the ninth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION
  • circuit elements constituting each functional block of the embodiment are not particularly limited, but are known in the art.
  • CMOS Complementary MOS Transistor
  • the PMOS transistor is distinguished from the NMOS transistor by attaching an arrow symbol to the body.
  • the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor is within the range ffl in which normal operation is possible. Also, unless otherwise specified, "The mouth of the f-symbol is set to '0', and the noirebenore is set to '.
  • FIG. L shows the memory cell array of the MRAM of the first embodiment.
  • memory cells MC00, C02, CU., MC13, C20, MC22, C31, MC33,... are provided in a checker pattern.
  • source lines SLOL, SL23,... are provided in the same direction as the read mode lines.
  • the read word lines WR0, WR1, WR2, WR3, ... are driven by the word line control circuit RCNL.
  • the write word lines WW0, WWL, WW2, WW3,... , And both ends of the source lines SL01, SL23,... are controlled by a word line control circuit RCN and a RCF1 including a drive circuit.
  • the source lines SL01, SL23,... May be applied with a fixed voltage such as the ground voltage VSS, or may be controlled to be floating at the time of writing as described in Reference 2.
  • Data lines DLO, DLl, DL2, DL3, ... are controlled at both ends by data line control circuits CCN1 and CCF1 including a sense circuit and a drive circuit.
  • Each memory cell includes one MTJ element MTJ and one transistor MT. One end of the MTJ element MTJ is connected to the data line, and the other end is connected to the drain of the transistor MT. The gate of the transistor MT is connected to the read mode line, and the source is connected to the source line.
  • the operation of the memory cell array is performed in the same manner as the conventional MRAM cell array shown in FIG. However, since a memory cell is arranged at half of all the intersections of the word line and the data line, the lowest address is commonly used for selecting the data line and the word line when selecting the memory cell.
  • the read operation is performed by setting the read word line WR selected among WR0, WR1, WR2, WR3,... to a high level, according to the magnetic resistance of the MTJ element MT.J. , DL1, DL2, DL3,..., By detecting the current IDL flowing through the desired data line.
  • FIG. 3 shows the read word line WR selected among WR0, WR1, WR2, WR3,...
  • the write operation is performed by setting the current IWW of the write word line selected among the jobs, W1, WW2, W3,... As the write word line current IWS, and DL0, DLL, DL2, DL3, ... Write current ID1 or according to the write data to the data line selected in: or [Generates a magnetic field by flowing DO.
  • the four memory cells adjacent to the selected memory cell MC11 are MC00, C02, MC20, and MC22. These are adjacent to both the selected write mode line WW1 and the selected data line DL1, but since both are only affected by the leakage magnetic field, the combined magnetic field is sufficiently small. it can.
  • the memory cell adjacent on the selected write word line WWl is MCL3, and receives a magnetic field due to the current of the write word line WW1, but since the data line DL2 is located far from the selected data line DLi, the distance is large.
  • the leakage magnetic field due to the current of the data line DLi is small.
  • the memory cell adjacent to the selected data line DL1 is MC31 and receives a magnetic field due to the current of the data line DL1, but there is a write mode line WW2 between the selected write mode line WW1 and the distance is large. Therefore, the leakage magnetic field due to the current of the write lead line WWi is small.
  • the leakage magnetic field is reduced in any of the unselected cells, and the possibility of being affected by the magnetization state can be avoided.
  • Fig. 5 shows the layout of the MTJ element
  • Fig. 6 shows the layout of the transistor.
  • the write cell line and the read cell line are each shifted by one line from the memory cell shown in FIG.
  • a dotted rectangle MC is an area of one memory cell.
  • FL is an active area pattern.
  • FG is a transistor gate pattern corresponding to the read word lines WR1 to WR4.
  • the area where the active area pattern FL and the gate pattern FG overlap is the channel of the power transistor.
  • it has the shape of a parallelogram.
  • Ml is the first wiring layer pattern and is used for the source lines SL01, SL23, and SL45.
  • LCT is a contact pattern from the diffusion layer to the first wiring layer.
  • PL is the lower electrode pattern of the MTJ element, and town is the MTJ element. It is an element pattern.
  • M2 is a second wiring layer pattern used for the write word lines WWl to WW4.
  • M3 is a third wiring layer pattern, corresponding to the data lines DL0 to [((3). MCNT is a memory contact pattern, and the first wiring layer and the second wiring layer are separated from the diffusion layer. This is the pattern of the connection hole to the lower electrode of the MTJ element through the well-known optical lithography.
  • FIG. 7 shows a cross section taken along the line AA ′ and FIG. 8 shows a cross section taken along the line BB ′ of the layout memory cells of FIGS. 5 and 6.
  • 100 is a p-type semiconductor substrate.
  • 101p is a p-type well formed in the memory cell array by ion implantation.
  • No. 02 is an element isolation oxide film, which is formed by, for example, etching a substrate and burying the oxide film in a region not surrounded by the pattern F.
  • Reference numeral 103 denotes an ⁇ -type diffusion layer serving as a source and a drain of the transistor.
  • the ⁇ -type diffusion layer is formed by ion implantation after forming a gate, and is formed in an active region without the element isolation oxide film 102 and the gate L04.
  • L04 is the gate of the transistor and is used as a read word line.
  • Reference numeral 105 denotes a plug of a contact between the diffusion layer and the first wiring layer, which is a contact pattern formed according to CT and MCNT.
  • 106 is a first wiring layer formed according to the pattern Ml.
  • Reference numeral 107 denotes a connection hole between the first wiring layer and the second wiring layer, which is formed according to the contact pattern MCNT.
  • L08 is no. This is the second wiring layer formed according to the turn M2, and the wiring that passes immediately below the MTJ element becomes the write data line.
  • L09 is a memory contact connecting the second wiring layer and the lower electrode of the MTJ element, and is formed according to the memory contact pattern MCNT.
  • 0 is the lower electrode of the MTJ element, which is processed according to the lower electrode pattern PL. It is desirable to use a material such as a noble metal suitable for forming a ferromagnetic material for this layer.
  • 1 L 1, 1 12, and L are the ferromagnetic fixed layer, tunnel insulating film, and ferromagnetic free layer that constitute the MTJ element, and are formed by etching with the MTJ element pattern MT after lamination.
  • LL 5 A third wiring layer formed according to the turn M3, which is in contact with the free layer L13 of the MTJ element and is used as a data line.
  • a through hole for connecting the second wiring layer 108 and the third wiring layer L15 is provided in the peripheral circuit region.
  • the write word lines, the read word lines, and the data lines are arranged in accordance with the circuit diagram of FIG.
  • the problem of disturbance to adjacent cells at the time of writing is avoided, so that the pitch of the write word line and data line can be reduced, and the memory cells can be highly integrated.
  • the shape of the MTJ element is made longer in the data line direction orthogonal to the word line and in the word line direction orthogonal to the data line.
  • the anisotropy of the ferromagnetic free layer 113 is increased, and the magnetic field due to the data line current is referred to as an easy axis, and the magnetic field due to a lead line current is referred to as a harness and a cis. Operation becomes possible.
  • the M TJ element pattern MJ has a hexagonal shape with the corners of a rectangle dropped, enabling stable magnetic pole reversal.
  • the MTJ elements having such a shape are arranged efficiently in a checker pattern.
  • the MTJ element is provided between a write word line and a data line in order to efficiently apply a magnetic field during writing. Therefore, it is necessary to provide a memory contact to the lower electrode of the MTJ element, avoiding the write source line.
  • the MTJ element has a larger area than the memory contact. Therefore, a memory contact is arranged for every two write word lines to eliminate a useless area.
  • FIG. 9 is a main block diagram of a configuration example of the synchronous memory.
  • Clock buffer CLKB, Command buffer CB, Command decoder CD, Address buffer AB, Column address counter YCT, Input buffer DIB, Output buffer A sector SCTO, SCT 1,... Including a memory array MAR is provided.
  • the configuration shown in FIG. 1 is used as the memory array MAR in FIG. However, depending on the memory capacity, a plurality of such configurations may be provided repeatedly to form the memory array MAR in FIG. Also, although sectors correspond to banks, multiple sectors per bank may be used.
  • the sector further includes a row predecoder XPD, a column predecoder YPD, a write buffer WB, and a main amplifier.
  • the clock buffer CLKB distributes the external clock CLK to the command decoder CD etc. as the internal clock CLKI.
  • the command decoder CD generates control signals for controlling the address buffer AB, the column address counter YCT, the input buffer DIB, the output buffer DOB, and the like in response to an external control signal CMD.
  • the address buffer AB takes in the external address ADR at a desired timing according to the external clock CLK and sends the low address I3X to the low address predecoder XPD.
  • the row address predecoder XPD pre-decodes the row address BX and outputs a row predecode address CX and a mat select signal MS to the memory array MAR.
  • the address buffer AB also sends the column address to the column address counter YCT.
  • the column address counter YCT uses the address as an initial value, generates a column address BY for performing a burst operation, predecodes the column address by a column address predecoder YPD, and outputs a ram predeco-address CY to the memory array MAR. Output.
  • the input buffer DI B takes in the data of the input / output data DQ with the external device at a desired timing and outputs the write data GI to the write buffer WB.
  • the write buffer WB outputs the write data GI to the main input / output line MI0.
  • the main amplifier MA amplifies the signal of the main input / output line MI0 and outputs the read data G0 to the output buffer D0B.
  • Output buffer D0B outputs read data G0 to input / output data DQ at desired timing.
  • a synchronous memory can be realized using the memory cell configuration according to the present invention.
  • Synchronous memory that fetches command addresses and inputs / outputs data in synchronization with external clock CLK enables operation at high frequencies and achieves high data rates it can.
  • MRAM by Akira Kizaki can apply various high-speed memory methods that have been questioned about SRAIV [and DRAM. It is needless to say that the present invention can be applied not only to a single MRAM but also to a general semiconductor device such as a system incorporating a MRAM and S1.
  • FIG. 10 shows an example of the timing of the read operation in the configuration example shown in FIG. The operation of the synchronous memory in FIG. 9 will be described according to the timing chart.
  • the command decoder CD determines the control signal CMD.
  • the row address and the column address are taken into the address file A1 from the end address ADR.
  • the address buffer AB outputs the address BX.
  • the row address predecoder XPD outputs the row predecode address CX, and in the memory MAR, the lead line WL shown in FIG. Selected.
  • the column address counter YCT operates every clock cycle with the column address fetched into the address buffer AB as the initial value, and the column address predecoder YPD outputs the column address BY corresponding to the burst operation.
  • the column address predecoder YPD outputs the column predecoder address CX in the sector SCT0 or SCTL, and selects the read data line DR shown in Figure] in the memory array MAR. .
  • a signal is read out to the main input / output line M I0, the main amplifier MA outputs read data GO, and the output buffer DOB outputs data at the timing according to the external clock CLK. Output.
  • the row address and the column address are simultaneously acquired by the read command R.
  • DRAM dynamic random access memory
  • MRAM can perform non-destructive readout and does not need to detect data in all memory cells on a word line, so this operation is possible. Power consumption can be reduced by detecting only the information of the selected data line.
  • FIG. 11 shows a memory cell array of the MRAM of the second embodiment.
  • the feature is that the order of the read-out read lines is changed with respect to the memory cell array of the first embodiment.
  • the write word lines are arranged in the order of WW1, WW2, W3,..., Whereas the read word lines are arranged in the order of WR0, WR2, WR1, WR3,. I have.
  • Source lines SL02, SL13,... Are arranged in the same direction as the read word lines.
  • memory cells MC00, MC02, MC11, MC13, C20, C22,..., MC31, MC33, ... Provided.
  • the read word lines WRO, WR1, WR2, WR3,. are controlled by word line control circuits RCN2 and RCF2, and both ends of data lines DL0, DL1, DL2, DL3,...
  • data line control circuits CCN2 and CCF2 including a sense circuit and a drive circuit.
  • Each memory cell consists of 1.
  • MTJ element iMTJ and: L transistor MT.
  • One end of each of the MTJ elements ⁇ and ⁇ is connected to the data line, and the other end is connected to the drain of the transistor ⁇ .
  • the gate of transistor ⁇ is connected to the read word line, and the source is connected to the source line.
  • Such a memory cell configuration s is repeated for every four write word lines and every four read word lines. Note that in FIG. 1 ⁇ ⁇ ⁇ , the memory cell MCL (), the write word line WW2 force; and the memory cell MC21, C23, the write word line WWL pass through. This is independent of the memory cell configuration, as shown in the layout below.
  • FIG. 12 shows the layout of the MTJ element
  • Fig. L3 shows the layout of the transistor.
  • the write cell line and the read cell line are shifted by L lines from the memory cell shown in FIG.
  • the dotted rectangle MC is an area of ⁇ ⁇ ⁇ memory cells.
  • FIG. 12 has the same layout as that of FIG. 5, but in FIG. 3, the shape of the active region pattern FL is different from that of FIG. 6 and is rectangular.
  • FG is the gate pattern of the transistor and is used as a read word line arranged in the order of WR2, W1U, WR3, WR4.
  • Mi is the first wiring layer pattern
  • LCT is the contact pattern from the diffusion layer to the second wiring layer.
  • M2 is a second wiring layer pattern, which is used for write word lines arranged in the order of WW, 2, WW3, WW4.
  • M3 is a third wiring layer pattern and is used as a data line.
  • MCNT is a memory contact pattern.
  • FIG. 14 shows a section taken along the line ⁇ - ⁇
  • FIG. 15 shows a section taken along the line BB ′.
  • 100 is a ⁇ -type semiconductor substrate
  • LO L p is a ⁇ -type well
  • L02 is an inter-element isolation oxide film
  • 103 is an n-type diffusion layer
  • 104 is a transistor transistor gate.
  • L05 is a plug of a contact between the diffusion layer and the first wiring layer
  • L06 is a first wiring layer
  • 107 is a connection hole between the first wiring layer and the second wiring layer
  • 108 is a second wiring layer
  • L09 is the memory contact
  • U0 is the lower electrode of the MTJ element
  • Lil, L12, and L13 constitute the MTJ element
  • 5 is the third wiring layer.
  • the memory cells connected to the same data line Every other lead wire is adjacent to the read lead line, but adjacent to the read lead line.
  • the problem of disturbing adjacent cells at the time of writing is not related to the read-out read line, and as in this embodiment, the MTJ element must be in a checker pattern for the data line and the write-out line.
  • the effect can be reduced by arranging the memory cells.
  • the memory cells connected to the adjacent read-out line are connected to the same data line, so that the channel shape of each transistor is made rectangular. As a result, the gate and the isolation oxide film do not intersect at an acute angle, and the performance improvement including the reliability of the transistor MT becomes easy.
  • FIG. 16 shows a memory cell array of the MRAM of the third embodiment.
  • the feature is that one read lead line is used for two write lead lines.
  • memory cells MC00, MC02, ..., MC11, MC13, MC20, MC22, MC31 , C33,... are provided.
  • read word lines WR0, WR1, WR2, WR3, are controlled by word line control circuits RCN3 and RCF3, and both ends of the data lines DL0, DL1, DL2, DL3,...
  • data line control circuits CCN3 and CCF3 including a sense circuit and a drive circuit.
  • Each memory cell includes one MTJ element MTJ and one transistor MT. The memory cell configuration is repeated for every two write word lines and every one read word line.
  • the address decoding method for selecting read lines differs between read and write.
  • the read mode line can be selected according to the addresses of two write word lines, so that the implementation is easy.
  • Fig. 17 shows the layout of the MTJ element
  • Fig. 18 shows the layout of the transistor.
  • the feature is that the source lines are wired by diffusion layers, and the CT used in FIG. 6 or FIG. 13 is eliminated by using the 1st-wiring layer pattern Ml and the contact pattern.
  • the area shifted from the memory cell shown in FIG. 16 by two write word lines in the data line direction, that is, by one read mode line, and by one data line in the read line direction. Is shown.
  • Dotted rectangle MC force 1. This is the area of one memory cell.
  • the force has the same layout as in Fig. 5 or Fig. 12; in Fig. 18, the shape of the active region pattern FL differs from that in Fig. 6 or Fig.
  • FG is a gate pattern of a transistor and is used as a read word line.
  • PL is the lower electrode pattern of the MTJ element
  • MI is the MTJ element pattern.
  • M2 is a second wiring layer pattern, which is used for a write lead line.
  • I is a third wiring layer pattern, which is used as a data line. .
  • MCNT for c Zu ⁇ 7 and Reiau Bok of the memory cell of FIG. 1 8 is a memory configuration Takt pattern from the diffusion layer to the MTJ element lower electrode through a second wiring layer
  • FIG. L9 shows a / ⁇ -/ ⁇ 'section
  • FIG. 20 shows a BB' section.
  • L00 is a p-type semiconductor substrate
  • l OL p is a p- type well
  • 102 is an element isolation oxide film
  • L03 is an n-type.
  • the diffusion layer, L04, is the transistor gate.
  • 105 is a contact plug between the diffusion layer and the second wiring layer because there is no first wiring layer.
  • Reference numeral 108 denotes a second wiring layer
  • L09 denotes a memory contact
  • 0 denotes a lower electrode of the MTJ element
  • 111, L12, and 3 form an MTJ element
  • L L5 denotes a third wiring layer.
  • the diffusion layer is used as a source line
  • the first wiring layer is omitted from the structures of the first and second embodiments.
  • the manufacturing process for the one-layer wiring layer can be eliminated, and the cost can be reduced.
  • the MTJ element layout for every two write lead lines, the interval between the memory contacts can be relatively large, so that the diffusion layer serving as the source line can be formed. The width can be secured to reduce the resistance. It should be noted that even in the case of the layout as in the first or second embodiment, it is possible to form a source line using a diffusion layer if the distance between gate patterns serving as read-out read lines is increased.
  • the active region since the active region has a layout orthogonal to the source lines as shown in FIG. 13, it is necessary to connect the diffusion layers in the read-out line direction to form the source lines.
  • the patterning of the active region is easy.
  • the number of read word lines is reduced to L for two write word lines, and the width of the diffusion layer serving as a source line is increased to reduce the resistance.
  • one read word line is used for two write word lines, so that the memory cells connected to the same data line are connected with respect to the read word line as in the second embodiment.
  • the MTJ element is a checker pattern for the data line and the write word line. Since the memory cells are arranged as described above, the effect can be reduced.
  • FIG. 21 shows a memory cell array of the MRAM of the fourth embodiment.
  • the memory cell is composed of two transistors MTL and MTR and MT MTJ elements MTJ.
  • Read word lines WR01 L, WR01 R, WR23 L, WR23R, ... are arranged corresponding to the write word lines WW0, Wi, WW2, WW3, ....
  • the source lines SLO, SL 12, SL34, ... are arranged.
  • the data lines DLO, DL1, DL2, DL3,... are controlled at both ends by the data line control circuits CCN4, CCF4 including the sense circuit and the drive circuit, controlled by the word line control circuits RCN4, RCF4 including the drive circuit.
  • the write mode lines WR01L and WROIR, WR23L and WR23R,... Are paired and connected to the gates of two transistors MTL and MTR in the memory cell.
  • a pair of two connected to the same memory cell performs the same control on the write line. That is, physically, there are two read word lines, but logically, there are two read word lines. Also, the transistors in the memory cell perform the same operation in parallel and are physically two transistors, but logically one transistor.
  • Each memory cell is composed of one MTJ element MTJ and one transistor MT. One end of the MTJ element MTJ is connected to the data line, and the other end is connected to the drain of the transistor MT.
  • FIG. 22 shows the layout of the MTJ element
  • Figure 23 shows the layout of the transistor.
  • FIG. 22 has a layout similar to that of FIG. 5 and the like, but in FIG. 23, the shape of the active region pattern FL is different from that of FIG. FG is a transistor gate pattern and is used as a read word line.
  • Ml is the first wiring layer pattern
  • LCT is the contact pattern from the diffusion layer to the first wiring layer.
  • PL is the lower electrode pattern of the MTJ element
  • MJ is an MTJ element pattern.
  • M2 is a second wiring layer pattern used for a write word line.
  • M3 is a third wiring layer pattern, which is used as a data line.
  • MCNT is a memory contact pattern.
  • FIG. 24 shows an AA ′ section
  • FIG. 25 shows a BB ′ section.
  • 100 is a p-type semiconductor substrate
  • LO lp is a p-type well
  • 102 is an element isolation oxide film
  • ⁇ 03 is an n-type.
  • Diffusion layer, 104 gate of transistor
  • 105 plug for contact between diffusion layer and first wiring layer
  • L06 first wiring layer
  • 107 connection hole between first and second wiring layers
  • Reference numeral 108 denotes a second wiring layer
  • 109 denotes a memory contact
  • 110 denotes an MTJ element lower electrode
  • 1, 1 12, and 13 constitute an MTJ element
  • 115 denotes a third wiring layer.
  • two transistors in the memory cell are connected in parallel to reduce the on-state resistance.
  • the resistance change rate of the MTJ element is detected.
  • the rate of change in resistance of the MTJ element is at most about several tens of percent, and for detection thereof, the on-resistance of the transistor must be sufficiently lower than the resistance of the MTJ element. Since the resistance value of the MTJ element cannot be increased so much in terms of operating speed, it is desirable to reduce the on-resistance of the transistor.
  • Reference 1 discloses that two transistors are connected in parallel and used for a memory cell.
  • this method is realized with an efficient layout by arranging the MTJ elements in a checker pattern, taking advantage of the relatively large space between the memory contacts.
  • patterning the active region pattern FL in a linear band facilitates patterning, reduces its space, increases the channel width of the transistor, and reduces the transistor resistance. It is also possible to convert.
  • FIG. 26 shows a memory cell array of the MRAM of the fifth embodiment.
  • the recell consists of two transistors MTb and MTt and two MTJ elements MT.Tb and MTJt.
  • read word lines RO, WR1, WR2, WR3,... are arranged corresponding to the write word lines WWO, W1, ⁇ 2, W3,.
  • Source lines SL01, SL23,... are arranged in the same direction as the read word lines.
  • the data lines are paired, and DLOb and DL0t, DLlb and DLU,.
  • each of the MTJ elements MTJh and MTJt in each memory cell is connected to the data line pair, and the other end is connected to the drains of the transistors MTb and MTt.
  • the gates of the transistors MTh and MTt are connected to the read mode line, and the sources are connected to the source line.
  • the write word line, the read mode line, and the source line are controlled by the read line control circuits RCN5 and RCF5 including the drive circuit, and the data line pair is connected to the sense circuit and the drive circuit. Both ends are controlled by the data line control circuits CCN5 and CCF5 including the circuit.
  • the operation of the memory cell array is performed as follows, with complementary information stored in the MTJ element in the memory cell.
  • the read operation as shown in FIG. 27, by setting the read word line WR selected among WRO, WR1, WR2, WR3,... To a high level, the transistors in the memory cells connected to the word line are changed. Turn on MTb and MTt and apply voltage to the terminals of MTJ element MT.Tb and TJb. Current flowing through a desired data line pair in DLOb and DL0t, DLib and DLlt,... According to the magnetoresistance of MTJ elements MTJb and MTJb: [Read stored information by comparing DLb and IDLt. . On the other hand, as shown in FIG.
  • the write operation is performed by setting the current TWW of the write source line selected among WWO, WW1, WW2, WW3,... As the write source line current IWS, and the DLOb, DL0t, DLlb DLit,... Write to the selected data line pair according to the write data This is performed by generating a magnetic field by passing a current.
  • the currents IDLb and IDLt of the selected data line pair at this time are complementarily positive ID1 and negative: [DO.
  • This embodiment uses a memory cell composed of two transistors and two MTJ elements as in Reference 1.
  • This memory cell is called a twin cell because it uses two complementary memory cells consisting of one transistor and one MTJ element.
  • the cell area is larger than that of the memory cell of the first embodiment, stable operation is easy.
  • the read operation it is sufficient to compare the currents of the data line pairs, and it is not necessary to generate a reference signal.
  • control is easy because the current flows so that the current reciprocates in the data line pair.
  • disturb at the time of writing is reduced by arranging the memory cells in a checker pattern.
  • the leakage magnetic field due to the current in the data line is reduced by arranging the data line paired with the adjacent data line next to the data line and flowing the current in the opposite direction.
  • adjacent memory cells on the selected write word line have a data line pair between the selected data line pair and the distance is sufficiently large, so that the leakage magnetic field due to the current of the data line pair is small.
  • FIG. 29 shows the layout of the MTJ element
  • FIG. 30 shows the layout of the transistor.
  • FL is an active region pattern
  • FG is a gate pattern of a transistor, which is used as a read-out line.
  • Ml is the first wiring layer pattern
  • LCT is the contact pattern from the diffusion layer to the first wiring layer.
  • PL is the lower electrode pattern of the MTJ element
  • Machi is the MTJ element pattern.
  • M2 is a second wiring layer pattern, which is used for a write lead line.
  • M3 is the third wiring layer pattern, Used as data line.
  • the layout is changed in width depending on the presence or absence of the corresponding MTJ element.
  • MCNT is a memory contact pattern.
  • FIG. 31 shows a BB ′ cross section.
  • 100 is a p-type semiconductor substrate
  • 101p is a p-type well
  • 02 is an element isolation oxide film
  • L04 is a transistor gate
  • L08 is a second wiring layer
  • 109 is a memory contact
  • 110 is a MTJ element lower electrode.
  • L11, 112 and 1L3 constitute the MTJ element
  • L15 is the third wiring layer.
  • the ⁇ -type diffusion layer, the plug of the contact between the diffusion layer and the first wiring layer, the connection hole between the first wiring layer, and the first and second wiring layers are not provided.
  • the shape of the MTJ element is longer in the word line direction orthogonal to the data lines than in the data line direction orthogonal to the word lines.
  • FIG. 32 shows a memory cell array of the MRAM of the sixth embodiment.
  • the feature is that an adjacent write mode line is used as a source line.
  • Read word lines WR0, WR1, WR2, WR3, ... are arranged corresponding to the write word lines WW0, WW1, WW2, WW3, ....
  • Each memory cell is connected to an adjacent write word line, for example, the memory cells MC00 and MC02 are also connected to a write word line WW1, and the memory cells MC11 and MC13 are also connected to a write word line WW0.
  • the write word lines WW0, WW1, WW2, 3,... and the read word lines WRO, WR1, WR2, WR3,... are controlled by the word line control circuits RCN6 and RCF6 including the drive circuit and the data lines.
  • DLO, DL1, DL2, DL3, ... are controlled at both ends by the data line control circuits CCN6 and CCF6 including the sense circuit and the drive circuit.
  • Each memory cell includes an MTJ element MTJ and a transistor MT.
  • One end of the MTJ element MT.T is connected to the data line, and the other end is connected to the drain of the transistor MT.
  • the gate of the transistor MT is connected to a read mode line, and the source is connected to an adjacent write mode line. That is, instead of being connected to the source line as in the first embodiment, it is connected to the adjacent write code line.
  • FIG. 33 shows the layout of the MTJ element
  • Figure 34 shows the layout of the transistor.
  • the first wiring layer pattern Ml used in the first embodiment and the like is deleted.
  • an area shifted from the memory cell shown in FIG. 16 by two write and read read lines in the data line direction and one data line in the pad line direction is shown.
  • FIGS. 33 and 34 Dotted rectangular MC force; area of one memory cell.
  • MCNT is a memory contact pattern from the diffusion layer to the lower electrode of the MTJ element via the second wiring layer
  • WCT is a contact pattern from the diffusion layer to the second wiring layer. is there.
  • FIG. 33 has the same layout as in FIG. 17 etc., but in FIG. 34, the active area pattern FL is extended and sewn due to the layout of the contact to the second wiring layer. Thus, the gate pattern FG of the transistor that is the read word line is arranged.
  • PL is the lower electrode pattern of the MTJ element
  • MT is the MTJ element pattern.
  • M2 is The second wiring layer pattern is used for a write word line.
  • M3 is a third wiring layer pattern and is used as a data line.
  • FIG. 35 shows an AA ′ section
  • FIG. 36 shows a BB ′ section
  • L00 is a p-type semiconductor substrate
  • LO lp is a p-type well
  • L02 is an element isolation oxide film
  • L03 is an n-type diffusion layer
  • L04 is The gate of the transistor
  • K) 5 is the plug of the contact between the diffusion layer and the second wiring layer
  • L08 is the second wiring layer
  • L09 is the memory contact
  • 110 is the lower electrode of the MTJ element
  • UL, 112, ⁇ L: 3 constitute the MTJ element
  • U5 is the third wiring layer.
  • the contact plug 105 is formed according to the contact patterns MCNT and WCT.
  • the first wiring layer is omitted from the structure of the first or second embodiment by using the adjacent write word line as the source line.
  • the manufacturing process for one wiring layer can be eliminated, and the cost can be reduced.
  • the diffusion layer can be used as the source line as in the third embodiment, the influence of the wiring resistance can be reduced by using the write word line as the source line as in the present embodiment.
  • the write word line is connected to two adjacent memory cells, but one of them replaces the source line, and the influence of disturbance on the adjacent cells during writing can be reduced.
  • the transistor ON resistance may be added due to the drive circuit in the read line control circuits RCN6 and RCF6 for controlling the write word line. Is done. However, as shown in Fig. 4, it is only necessary to supply a current to the write line in one direction, so one of the write line control circuits RCN6 and RCF6 connects the write line to a fixed voltage. It is also possible to prevent the resistance from being added.
  • FIG. 37 shows a memory cell array of the MRAM of the seventh embodiment. ⁇
  • the feature is that the read line is alternately used as a write line and a read line in memory cells adjacent to each other in the line direction.
  • the memory cells MC00 for every two lines , MC02, MCll, MCI 3,..., C20, MC22, MC31, MC33, ⁇ .., MC40, MC42, .., C51, MC53,..., C60, MC62,...,
  • MC71, MC73, ..., ... are provided.
  • source lines SLO, SL12, SL34, SL56, SL78 ... are arranged for every two word lines.
  • Each memory cell includes an MTJ element MTJ and a transistor MT.
  • One end of the TJ element MT.J is connected to the data line, and the other end is connected to the drain of the transistor MT.
  • the gate of the transistor MT is connected to the gate line.
  • the source is connected to the source line.
  • the role of the word line is alternated for each data line between a write word line that applies a magnetic field to the MTJ element and a read word line connected to the gate of the transistor.
  • the lead lines W0, W2, W4, and W6 work as write lead lines
  • the lead lines Wl, W3, W5 , W7 are connected as read word lines.
  • the read lines Wt, W, 5, W7 function as write word lines, and the word lines WO, W2, W4, W6 read out. It is connected as a lead line.
  • Fig. 38 shows the layout of the MTJ element
  • Fig. 39 shows the layout of the transistor.
  • M2 is a second wiring layer pattern
  • FG is a transistor gate pattern, both of which are used for word lines.
  • the FCT is a contact pattern from the gate to the second wiring layer via the wiring layer.
  • FL is the active region pattern
  • Ml is the first wiring layer pattern
  • LCT is the contact pattern from the diffusion layer to the first wiring layer
  • PL is the lower electrode pattern of the MTJ element
  • MJ is the MTJ element pattern.
  • M3 is a third wiring layer pattern used as a data line.
  • MCNT is a memory contact pattern. If necessary, the contact pattern FCT from the gate via the first wiring layer to the second wiring layer can be thinned out.
  • FIG. 40 shows an AA ′ section
  • FIG. 41 shows a BB ′ section
  • 105f is a contact plug of the gate and the first wiring layer, and is formed according to the contact pattern FCT in FIG.
  • Other symbols are the same as those in FIGS. 7 and 8, such as 100 is a p-type semiconductor substrate, lOLp is a p-type transistor, 102 is an element isolation oxide film, 103 is an n-type diffusion layer, and 104 is a transistor.
  • connection hole 107 is formed in accordance with the contact pattern FCT in addition to the memory contact pattern MCNT shown in FIGS. 38 and 39. As described above, by connecting the gate 104 serving as a read lead line to the second wiring layer 108 serving as a write lead line, the read operation can be sped up.
  • the gate 104 is generally formed of polysilicon, polysilicon, or some metal, such as polymetal in which polysilicon and metal are laminated, and has a higher sheet resistance than a metal wiring layer. By connecting this to the second wiring layer, the influence of the sheet resistance of the gate 104 is reduced, and this is used for reading. -The rise and fall times of the gate line can be shortened.
  • Literature 2 discloses a configuration in which a read line and a write line are connected by the edge of a memory cell array.In this embodiment, however, the connection is made by a large number of connection holes in the memory array. The effect of shunting the gate with the metal wiring layer is great.
  • the read line is connected to two adjacent memory cells.On the other hand, the read line is a gate and the other is a second wiring layer which is a write word line. In addition, the influence of disturbance on adjacent cells during writing can be reduced.
  • FIG. 42 shows a memory cell array of the MRAM of the eighth embodiment.
  • the feature is that data lines are paired, and memory cells are connected so that read current flows between pairs of data lines.
  • the read word lines WR0, WR1, R2, WR3,... Are arranged corresponding to the write word lines WWO, WW, WW2, W3,.
  • memory cells MC00, C01, C02, MC03, MC10, MC11, MCL2, MC13 , MC20, MC21, C22, MC23, C30, MC31, C32, MC33, ..., ... are provided.
  • Each memory cell includes an MTJ element MTJ and a transistor MT.
  • One end of the MTJ element MTJ is connected to one of the data line pairs, and the other end is connected to the drain of the transistor MT.
  • the gate of the transistor MT is connected to the read mode line, and the source is connected to the other of the data line pair.
  • MTJ element MT.J is connected to data line DLOu
  • transistor MT is connected to data line DL01
  • MTJ element iMTJ is connected to data line DL01.
  • the transistor MT is connected to the data line DLOu.
  • the operation of the memory cell array is performed as follows.
  • the read line selected in Book 0, WR1, WR2, WR3, ... is set to the high level, so that the memory cells connected to the read line can be read.
  • the transistor MT is turned on, and a voltage is applied between the terminals of the MTJ element MT.T. Detects the current IDLu and IDL1 flowing through the desired data line pair among the DLOu and DL01, DLlu and DL11, DL2u and DL21, DL3u and DL31,... in accordance with the magnetic resistance of the MTJ element MT.I. By doing so, the stored information is read.
  • the read line selected in Book WR1, WR2, WR3, ... is set to the high level, so that the memory cells connected to the read line can be read.
  • the transistor MT is turned on, and a voltage is applied between the terminals of the MTJ element MT.T. Detects the current IDLu and IDL1 flowing through
  • the write operation is performed for WW0, WW1, WW2, WW3, ...
  • the current I of the selected write line is selected as the write line current IWS, and D and Ob and DL0t, DLlb and DLlt, are connected to the MTJ element MTJ on one of the data line pairs selected in....
  • a magnetic field is generated by applying a write current ID1 or ID0 according to the write data to the data line.
  • FIG. 44 shows a case where a memory cell to which the MTJ element MTJ is connected is selected and written to the data lines DL0u, DLlu, DL2u, DL3u,..., And the data line selected among them is shown. Is the write current IDt or ID0.
  • the current IDL1 is set as the write current ID1 or ID0.
  • Figure 45 shows the layout of the MTJ element
  • Figure 46 shows the layout of the transistor.
  • the first wiring layer pattern Ml used in the first embodiment and the like is deleted. Dotted rectangular MC is the area of L memory cells.
  • MCNT is the memory contact pattern from the diffusion layer to the lower electrode of the MTJ element via the second wiring layer
  • DLCT is the third contact pattern from the diffusion layer via the second wiring layer. This is a contact pattern to the wiring layer.
  • PL is the lower electrode pattern of the MTJ element, and is the MTJ element pattern.
  • M2 is a second wiring layer pattern used for a write word line.
  • M3 is a third wiring layer pattern and is used as a data line.
  • the active region pattern FL is greatly inclined with respect to the data line due to the layout of the contact from the diffusion layer to the third wiring layer.
  • FG is a gate pattern and is used as a read mode line.
  • FIG. 47 shows a section taken along the line-′
  • FIG. 48 shows a section taken along the line BB ′.
  • 100 is a ⁇ -type semiconductor substrate
  • ⁇ 0Lp is a ⁇ -type semiconductor
  • L02 is an element isolation oxide film
  • L03 is n.
  • L04 is transistor
  • L05 is a plug of a contact between the diffusion layer and the second wiring layer
  • 108 is a second wiring layer
  • 109 is a memory contact
  • L10 is a lower electrode of the MTJ element
  • 111, 112, and 3 are An MTJ element is formed
  • LL5 is a third wiring layer.
  • the contact plug 105 is formed according to the contact patterns MCNT and DLCT.
  • U4 is a connection hole from the second wiring layer to the third wiring layer, and is formed according to the data line contact pattern DLCT.
  • the first wiring layer used as the source line in the first embodiment and the like is deleted by using the data lines as the pair lines.
  • the manufacturing process for one wiring layer can be eliminated, and the cost can be reduced.
  • the diffusion layer can be used as the source line as in the third embodiment, the effect of the wiring resistance can be reduced in the present embodiment using the metal wiring layer.
  • the signal current is read out to both data line pairs, the read current can be effectively doubled by taking the difference between the currents in the data line pairs. This makes it possible to increase the S / N and speed up the reading operation.
  • the data line is connected to two adjacent memory cells. However, since tV [every TJ element MT.J is connected to the adjacent memory cell, the data line is connected to the adjacent cell at the time of writing. The effect of the disturbance can be reduced.
  • FIG. 49 shows the layout of the MTJ element.
  • the layout of the transistor should be as shown in Figure 6. Similar to FIG. 5, the write and read read lines are shifted by i each from the memory cell shown in FIG. 1, and the rectangular MC indicated by the dotted line represents the area of ⁇ ⁇ ⁇ memory cells. is there.
  • PL is the lower electrode pattern of the MTJ element, is the pattern of the MTJ element —
  • M2 is a second wiring layer pattern used for the write word lines WW1 to WW4.
  • M3 is a third wiring layer pattern, and corresponds to the data lines DL0 to DL3.
  • MCNT is a memory contact pattern, and the layout shown in Fig. 5, which is a pattern of connection holes from the diffusion layer to the lower electrode of the MTJ element via the first and second wiring layers,
  • the longitudinal direction is alternately inclined for each writing lead line, whereas the hexagon is a hexagon and the lead line direction is the longitudinal direction.
  • FIG. 50 shows a B- ⁇ 'cross section.
  • 100 is a ⁇ -type semiconductor substrate
  • ⁇ is a p-type well
  • 102 is an isolation oxide film
  • 104 is a transistor gate
  • 108 is a second wiring layer
  • 109 is a memory contact
  • 0 is an MTJ element lower electrode
  • 111, 112, and L13 constitute an MTJ element
  • 115 is a third wiring layer.
  • the n-type diffusion layer, the plug of the contact between the diffusion layer and the first wiring layer, the connection hole between the first wiring layer and the first and second wiring layers are not visible.
  • FIG. 51 and FIG. 52 show the write operation.
  • the feature is that the current of the write word line is controlled by the write operation, and the polarity is switched for each write word line.
  • the current flowing through the word line control circuit RCN1 from the word line control circuit RCF1 is assumed to be positive.
  • the current flowing from the data line control circuit CCNL to CCF1 is assumed to be positive.
  • the current IWWe of the selected write word line is The positive write word line current IWp is used, and when writing '0', the negative write word line current IWn is used.
  • the book to select If the write word line is one of the odd-numbered WW and WW3,..., as shown in Figure 52, the current IWWo of the selected write word line and the negative write ⁇ Assuming that the lead line current is IWn, when writing '0', a positive write word line! ; Flow IWp.
  • the current of the data line selected among DL0, DL1, DL2, DL3, ... is set to positive write current ID1 or negative ID0 according to the write data.
  • the combined magnetic field to the MTJ element of the selected memory cell due to the currents of the write select line and the data line changes according to the write data in a direction close to the longitudinal direction of the M: TJ element.
  • the writing can be easily performed by reversing the magnetization of the free layer.
  • Reference 5 A method of alternately arranging the magnetoresistive elements with respect to the lead wire in this manner is disclosed in Reference 5.
  • the magnetoresistive elements are arranged at all the intersections of the data line and the data line to which the magnetic field is applied by the electric current.
  • the intersection of the write code line and the data line has a checker pattern. Since the MTJ element is located in the area, the effect of reducing disturb is even greater. Further, since the corners in the longitudinal direction of adjacent MTJ elements do not approach each other, the layout is easy.
  • the fixed layer of the MTJ element desirably has the same direction in order to determine the direction at the time of manufacture.
  • the magnetization of the free layer is It is desirable that the direction is the write code line direction, and the angle at which the longitudinal direction of the MTJ element is inclined with respect to the write code line direction is in the range of -45 degrees to 45 degrees.
  • the present invention is suitable for a semiconductor device having a memory cell array that stores information by using a change in magnetoresistance.
  • a single MR AM or a system containing MR AM can be applied to SI.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne une mémoire MRAM hautement fiable et hautement intégrée, qui présente un grand signal de lecture et une faible perturbation de cellule adjacente lors de l'écriture. La mémoire MRAM selon l'invention comprend une pluralité de lignes de mots d'écriture (WW0 à WW3) qui peuvent être sélectionnés lors de l'écriture et sont conçus pour l'application d'un courant électrique, une pluralité de lignes de données (DL0 à DL3), qui sont perpendiculaires aux lignes de mots, peuvent être sélectionnés pour l'écriture et sont conçues pour l'application d'un courant électrique correspondant aux données d'écriture, ainsi qu'une pluralité de cellules de mémoire comprenant un élément MTJ (MTJ) et un transistor (MT) et agencées en forme d'échiquier. L'élément MTJ est connecté, à une extrémité, aux lignes de données, et, à l'autre extrémité, au drain du transistor. La grille du transistor est reliée à une pluralité de lignes de mots de lecture (WR0 à WR3) correspondants aux lignes de mots d'écriture. Lors de l'écriture, par conséquent, le champ magnétique fuyant vers des cellules de mémoire adjacente à la cellule sélectionnée est réduit, ce qui réduit donc l'influence sur l'état magnétisé.
PCT/JP2001/010990 2001-12-14 2001-12-14 Dispositif a semi-conducteur WO2003052828A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003553626A JP4461804B2 (ja) 2001-12-14 2001-12-14 半導体装置
PCT/JP2001/010990 WO2003052828A1 (fr) 2001-12-14 2001-12-14 Dispositif a semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2001/010990 WO2003052828A1 (fr) 2001-12-14 2001-12-14 Dispositif a semi-conducteur

Publications (1)

Publication Number Publication Date
WO2003052828A1 true WO2003052828A1 (fr) 2003-06-26

Family

ID=11738040

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2001/010990 WO2003052828A1 (fr) 2001-12-14 2001-12-14 Dispositif a semi-conducteur

Country Status (2)

Country Link
JP (1) JP4461804B2 (fr)
WO (1) WO2003052828A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1826772A1 (fr) * 2006-02-22 2007-08-29 Samsung Electronics Co., Ltd. Dispositif de mémoire magnétique et procédé d'écriture de données dans un dispositif de mémoire magnétique
JP2008192990A (ja) * 2007-02-07 2008-08-21 Toshiba Corp 半導体記憶装置
DE102004030174B4 (de) * 2003-12-24 2012-03-01 Hynix Semiconductor Inc. Magnetischer Direktzugriffsspeicher

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101325188B1 (ko) 2012-04-09 2013-11-20 이화여자대학교 산학협력단 자기 저항 메모리
KR102098244B1 (ko) * 2014-02-04 2020-04-07 삼성전자 주식회사 자기 메모리 소자

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894447A (en) * 1996-09-26 1999-04-13 Kabushiki Kaisha Toshiba Semiconductor memory device including a particular memory cell block structure
US6005800A (en) * 1998-11-23 1999-12-21 International Business Machines Corporation Magnetic memory array with paired asymmetric memory cells for improved write margin
US6055178A (en) * 1998-12-18 2000-04-25 Motorola, Inc. Magnetic random access memory with a reference memory array
US6111781A (en) * 1998-08-03 2000-08-29 Motorola, Inc. Magnetic random access memory array divided into a plurality of memory banks
EP1109170A2 (fr) * 1999-12-16 2001-06-20 Kabushiki Kaisha Toshiba Dispositif de mémoire magnétique
JP2001217398A (ja) * 2000-02-03 2001-08-10 Rohm Co Ltd 強磁性トンネル接合素子を用いた記憶装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894447A (en) * 1996-09-26 1999-04-13 Kabushiki Kaisha Toshiba Semiconductor memory device including a particular memory cell block structure
US6111781A (en) * 1998-08-03 2000-08-29 Motorola, Inc. Magnetic random access memory array divided into a plurality of memory banks
US6005800A (en) * 1998-11-23 1999-12-21 International Business Machines Corporation Magnetic memory array with paired asymmetric memory cells for improved write margin
US6055178A (en) * 1998-12-18 2000-04-25 Motorola, Inc. Magnetic random access memory with a reference memory array
EP1109170A2 (fr) * 1999-12-16 2001-06-20 Kabushiki Kaisha Toshiba Dispositif de mémoire magnétique
JP2001217398A (ja) * 2000-02-03 2001-08-10 Rohm Co Ltd 強磁性トンネル接合素子を用いた記憶装置

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
DURLAM M. ET AL.: "Nonvolatile RAM based on magnetic tunnel junction elements", IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 2000, pages 130 - 131, XP002909386 *
NAJI P.K. ET AL.: "A 256kb 3.OV 1T1MTJ nonvolatile magnetoresisitive RAM", IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 2001, pages 122 - 123, XP002909384 *
SCHEUERLEIN R. ET AL.: "A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell", IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 2000, pages 128 - 129, XP002909385 *
WANG Z.G. ET AL.: "Feasibility of ultra-dense spin-tunneling random access memory", IEEE TRANSACTIONS ON MAGNETICS, vol. 33, no. 6, 1997, pages 4498 - 4512, XP000831059 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004030174B4 (de) * 2003-12-24 2012-03-01 Hynix Semiconductor Inc. Magnetischer Direktzugriffsspeicher
EP1826772A1 (fr) * 2006-02-22 2007-08-29 Samsung Electronics Co., Ltd. Dispositif de mémoire magnétique et procédé d'écriture de données dans un dispositif de mémoire magnétique
US7548449B2 (en) 2006-02-22 2009-06-16 Samsung Electronics Co., Ltd. Magnetic memory device and methods thereof
JP2008192990A (ja) * 2007-02-07 2008-08-21 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
JPWO2003052828A1 (ja) 2005-04-28
JP4461804B2 (ja) 2010-05-12

Similar Documents

Publication Publication Date Title
TW508827B (en) Magnetic random access memory
JP4290494B2 (ja) 半導体記憶装置
KR100288823B1 (ko) 반도체기억장치
TW565840B (en) Thin film magnetic memory device
US20030117837A1 (en) Magnetic random access memory and method of operating the same
JP2003060165A (ja) 半導体記憶装置
JP2006294179A (ja) 不揮発性記憶装置
US6724651B2 (en) Nonvolatile solid-state memory and method of driving the same
TW200304144A (en) Magnetic random access memory
KR20140023806A (ko) 자기 저항 메모리 장치의 배치 구조
TW200301561A (en) Magnetic random access memory and the manufacturing method thereof
KR20060059209A (ko) 메모리
JP2010218678A (ja) 情報保存装置及びその動作方法
JP2007294762A (ja) 磁気メモリセル及びランダムアクセスメモリ
US6714442B1 (en) MRAM architecture with a grounded write bit line and electrically isolated read bit line
US20130265821A1 (en) Shared bit line smt mram array with shunting transistors between bit lines
KR100943112B1 (ko) 토글 메모리를 기록하는 회로 및 방법
JP3392657B2 (ja) 半導体記憶装置
JP3788964B2 (ja) 磁気ランダムアクセスメモリ
JP4834403B2 (ja) 磁気書き込み線を利用したｍｒａｍメモリ
US8144503B2 (en) Information storage device and method of operating the same
US20080007991A1 (en) Reversed Magnetic Tunneling Junction for Power Efficient Byte Writing of Mram
JP2006073956A (ja) メモリ
WO2003052828A1 (fr) Dispositif a semi-conducteur
JP2005251336A (ja) 磁気抵抗ランダムアクセスメモリおよびその駆動方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003553626

Country of ref document: JP

122 Ep: pct application non-entry in european phase