WO2003052828A1 - Semiconductor device - Google Patents

Abstract

There is provided a highly-reliable, highly-integrated MRAM which has a large read signal and a low disturbance of an adjoining cell in writing. An MRAM comprises a plurality of write word lines (WW0 to WW3) selected in writing and adapted for applying an electric current, a plurality of data lines (DL0 to DL3) perpendicular to the word lines, selected in writing, and adapted for applying an electric current corresponding to the write data, and a multiplicity of memory cells including an MTJ element (MTJ) and a transistor (MT) and arranged in a checker pattern. The MTJ element is connected at its one end with the data lines and at the other end with the drain of the transistor. The gate of the transistor is connected with a plurality of read word lines (WR0 to WR3) corresponding to the write word lines. In writing, therefore, the leakage magnetic field leaking to memory cells adjacent to the selected cell is reduced thereby to reduce the influence on the magnetized state.

Description

 Description Semiconductor device technical field

 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a high-speed, highly-integrated, and highly-reliable memory using a memory cell that stores information using a change in magnetoresistance. Background art

 The documents referred to in this specification are as follows, and the documents are referred to by their document numbers. [Literature: 1.]: R. Scheuerlein, et al., "A 10ns Read and Wri'te Non-Voia'tile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each cell, 2000 IEEE International Sol id-State L: Lrcuits Conference Digest of Technical Papers, pp. 128-129, Feb. 2000. [Reference 2]: PK Naji, et al., "A 256kb 3.0V LTIMTJ Nonvolatile Magne'toresis.tive RAM," -2001 IEEE ΐη terna tional Sol id-State Circuits Conference Digest of Technical Papers, pp. L22-L23, Feb. 2001. [Reference 3]: ZG Wang, et al., "Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory," IEEE Transaction on Magnetics, vol. 33, no. 6, pp. 4498-45L2, Nov. L997. [Reference 4]: Japanese Patent Laid-Open No. 10-106255 [Reference 5]: USP6, 005, 800.

A magnetic resistive 'random access memory' (MRAM) has been developed as a non-volatile memory that does not limit the number of reads and writes. MRAM stores information using the magnetoresistive effect in which the resistance of the element differs depending on the direction of magnetization of the ferromagnetic material in the memory cell. In recent years, magnetic resistance called magnetic resistance (MR) has been Magnetic tunnel with large resistance change rate ■ Junction TJ) The development of elements and their application to MRAM are underway. It is possible to perform high-speed read / write operations at the same level as statistic “random access memory” (SAM) and achieve high integration at the same level as dynamic random access memory (DRAM). : L and Ref.

FIG. 2 shows a basic configuration of a memory cell array used in Reference 2. At the intersection of the write word lines WW0, WW1, WW2, WW3,… and the read word lines WR0, WRl, WR2, WR3,… and the data lines DLO, DL1, DL2, DL,…, memory cells MC00, COL, MC02, MC0, MC10, MC11, MC12, MCL, ..., C20, MC21, C22, C23, MC30, MC.'H, MC2, i \ 'IC, ..., ... are provided. The write word lines WW0, WW1, WW2, WW3, ... and the read word lines WR0, WRL, WR2, WR3, ... are controlled by read line control circuits RCN0, RCF0 including a drive circuit. The data lines D, 0, DLL, D, 2, D3, ... are controlled at both ends by a data line control circuit (ΧΝ, CCF0) including a sense circuit and a drive circuit. MTJ element consists of one MTJ element and one transistor M. The MTJ element MTJ has a fixed layer of ferromagnetic material whose magnetization direction is fixed in normal operation, and the magnetization direction can be reversed by a write operation The resistance between the two terminals of this MTJ element varies depending on the direction of magnetization in the two ferromagnetic layers. However, when they are in the same direction, they are in a low-resistance state, and when they are in opposite directions, they are in a high-resistance state.The read operation is performed as shown in Figure 3. That is, RO, WRl, WR2, WR3,… By setting the read word line WR to high level, the memory connected to the read line The transistor MT is turned on in the transistor, and a voltage is applied to the terminals of the MT J element MT.J. According to the magnetic resistance of the M element J element MTJ, D is 0, DL1, DL2, DL3,… The stored information is read out by detecting the current IDL flowing through the desired data line. On the other hand, the write operation is performed as shown in FIG. That is, the current IWW of the write mode line selected among WW0, WW1, WW2, WW3,... Is defined as the write mode current IWS, and the data lines of DL0, DLL, DL2, DL3,. The current is set to a positive write current IDi or a negative ID0 according to the write data to generate a magnetic field. At this time, the magnetization resistance change MR, which is the ratio of the increase in resistance in the high resistance state to the low resistance state of the MTJ element, exhibits hysteresis characteristics. Due to the hard axis magnetic field generated by the write line current IWS, the magnetization reversal of the MTJ element is likely to occur, and the hysteresis characteristic is narrow with respect to the data line current IDL that generates the easy axis magnetic field. As a result, only the memory cell selected by the write word line WW can be magnetized and the storage information can be written.

As MRAM becomes more highly integrated, disturbing adjacent cells in this write operation becomes a problem. For example, consider a case in which a current flows through the write mode line VWL and the data line DL1 in order to write to the memory cell MC11 in FIG. The adjacent memory cells MC10 and MC12 are in the selected state of the write word line 'l, receive the magnetic field generated by the current, and are memory cells adjacent to the selected data line DLL. However, a leakage magnetic field due to the current is also received. Therefore, it may be affected by the magnetization state. Also, the adjacent memory cells MC01 and MC21 may be affected by the magnetization state because the data line DL1 is in the selected state and further adjacent to the selected write mode line WW1. This disturb problem is not related to a memory cell consisting of 丄 MTJ elements MTJ and one transistor MT, but to a memory cell using an MTJ element (spin-to-tunnelling element). It is described in reference 3. There, the MTJ element and 0. 2 / m square, if the space between 0. 2 ⁴ mu m, it is shown that would occur magnetization reversal in the adjacent MTJ element. In Reference 3, as a countermeasure, a flux that confines magnetization '' closure keeper It has been proposed to provide a process, but the number of processes will increase, and the compatibility between the material and the semiconductor process will be a problem. Reference 4 discloses a method of reducing disturbance to adjacent cells at the time of writing in a MAM using a memory cell using a giant's magneto-resistance (GMR) element. Since the GMR element has a smaller MR ratio than the MTJ element, the readout signal is small and high-speed stable operation is difficult. To realize a highly integrated MRAM with sufficient performance, a memory cell composed of MTJ elements and transistors, as shown in Ref. 1 or Ref. 2, is promising. Reference 4 does not describe measures against disturb in the memory cell structure.

 Therefore, an object of the present invention is to provide a highly reliable and highly integrated MRAM with a large read signal, small disturbance to adjacent cells at the time of writing. Disclosure of the invention

Present invention a plurality of write Wado line Thus 0 flowing representative if Shimese a configuration selected _c during writing as follows current of the semiconductor device according to,丽and WW2, WW3, ... and, intersects the plurality of word lines A large number of memory cells, including the MTJ element MTJ and the transistor ιΜΤ, are arranged in a checker pattern for a plurality of data lines DL0, DL1, DL2, DL3,… that are selected at the time of writing and carry current according to the write data. _c is desirable to have the placed MRAM Seruarei, the MTJ element is provided question between the write word line and the data line, one end of which is connected to the data line, the other end is connected to the drain of the Bok Rungis data You. The gates of the above transistors are connected to a plurality of read mode lines WR0, WR1, WR2, WR3,... Provided corresponding to the plurality of write mode lines. The source of the transistor is connected to a source line arranged in substantially the same direction as the data line. Furthermore, desired Alternatively, in the MTJ element, a dimension in a direction perpendicular to the data line is larger than a dimension in a direction perpendicular to the word line. The MTJ element and the transistor are arranged for every two write lead lines of the transistor. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a diagram showing a configuration of a memory cell array according to the first embodiment. FIG. 2 is a diagram showing a configuration example of a conventional MRAM memory cell array. FIG. 3 is a diagram showing a read operation of the MRAM cell.

 FIG. 4 is a diagram showing a write operation of the MRAM cell.

 FIG. 5 is a diagram showing a layout of the MTJ element of the first embodiment. FIG. 6 is a diagram showing a layout of the transistor of the first embodiment. FIG. 7 is a diagram showing the structure of a section taken along the line AA ′ in FIGS. 5 and 6.

 FIG. 8 is a diagram showing the structure of a section taken along the line BB ′ of FIGS. 5 and 6.

 FIG. 9 is a diagram illustrating a configuration example of a memory.

 FIG. 10 is a diagram showing the operation of the memory of FIG.

 FIG. 11 is a diagram illustrating the configuration of the memory cell array according to the second embodiment. FIG. 12 is a diagram showing a layout of the MTJ element of the second embodiment. FIG. 13 is a diagram showing a layout of the transistor of the second embodiment. FIG. 14 is a diagram showing the structure of a section taken along the line AA ′ of FIGS. 12 and 3.

 FIG. 15 is a diagram showing a structure of a section taken along the line BB ′ of FIGS. 12 and 13.

 FIG. 16 is a diagram showing the configuration of the memory cell array according to the third embodiment. FIG. 17 is a diagram showing a layout of the MTJ element of the third embodiment. FIG. 18 is a diagram showing the layout of the transistor of the third embodiment. FIG. 19 is a diagram showing the structure of a section taken along the line AA ′ of FIGS. 17 and 18.

 FIG. 20 is a diagram showing a structure of a section taken along line BB ′ of FIGS. 17 and 18.

FIG. 21 is a diagram showing the configuration of the memory cell array according to the fourth embodiment. FIG. 22 is a diagram showing a layout of the MTJ element of the fourth embodiment. FIG. 23 is a diagram showing a layout of the transistor of the fourth embodiment. FIG. 24 is a diagram showing a structure of a section taken along the line AA ′ of FIGS. 22 and 23.

 FIG. 25 is a diagram showing a structure of a cross section taken along line BB ′ of FIGS. 22 and 23.

 FIG. 26 is a diagram showing the configuration of the memory cell array of the fifth embodiment. FIG. 27 is a diagram illustrating a read operation of the MRAM cell of the fifth embodiment.

 FIG. 28 is a diagram showing a write operation of the MRAM cell of the fifth embodiment.

 FIG. 29 is a diagram showing a layout of the MTJ element of the fifth embodiment. FIG. 30 is a diagram showing a layout of the transistor according to the fifth embodiment. FIG. 31 is a diagram showing a structure of a cross section taken along line BB ′ of FIGS. 29 and 30.

 FIG. 32 is a diagram showing the configuration of the memory cell array of the sixth embodiment. FIG. 33 is a diagram showing a layout of the MTJ element of the sixth embodiment. FIG. 34 is a diagram showing a layout of the transistor of the sixth embodiment. FIG. 35 is a diagram showing the structure of a section taken along the line II-II of FIGS. 33 and 34.

 FIG. 36 is a diagram showing the structure of the section taken along line BB ′ of FIGS. 33 and 34.

 FIG. 37 is a diagram showing the configuration of the memory cell array of the seventh embodiment. FIG. 38 is a diagram showing a layout of the MTJ element of the seventh embodiment. FIG. 39 is a diagram showing a layout of the transistor according to the seventh embodiment. FIG. 40 is a diagram showing the structure of the section taken along the line AA ′ in FIGS. 38 and 39.

 The upper part of FIG. 4 is a diagram showing the structure of the section taken along line BB ′ of FIGS. 38 and 39.

 FIG. 42 is a diagram showing the configuration of the memory cell array according to the eighth embodiment. FIG. 43 is a diagram showing a read operation of the MRAM cell of the eighth embodiment.

 FIG. 44 is a diagram showing a write operation of the MRAM cell of the eighth embodiment.

FIG. 45 is a diagram showing a layout of the MTJ element according to the eighth embodiment. FIG. 46 is a diagram showing a layout of the transistor according to the eighth embodiment. FIG. 47 is a diagram showing a structure of a section taken along the line AA ′ of FIGS. 45 and 46.

 FIG. 48 is a diagram showing a structure of a section taken along line BB ′ of FIGS. 45 and 46.

 FIG. 49 is a diagram showing a layout of the MTJ element of the ninth embodiment. FIG. 50 is a diagram showing the structure of the section taken along line BB ′ of FIG. 49.

 FIGS. 51 and 52 are diagrams showing the write operation of the MRAM cell of the ninth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are known in the art.

It is formed on a semiconductor substrate such as single crystal silicon by integrated circuit technology such as CMOS (Complementary MOS Transistor). In the drawings, the PMOS transistor is distinguished from the NMOS transistor by attaching an arrow symbol to the body. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor is within the range ffl in which normal operation is possible. Also, unless otherwise specified, "The mouth of the f-symbol is set to '0', and the noirebenore is set to '.

 (No. 1: Embodiment 1)

Figure: L shows the memory cell array of the MRAM of the first embodiment. At the intersection of the write lead lines WW0, WW1, WW2, WW3,… and the read lead lines WR0, WRL, WR2, WR3,… and the data lines DLO, DLL, DL2, DL3,…, In a checker pattern, memory cells MC00, C02, CU., MC13, C20, MC22, C31, MC33,... Are provided in a checker pattern. Further, source lines SLOL, SL23,... Are provided in the same direction as the read mode lines. The read word lines WR0, WR1, WR2, WR3, ... are driven by the word line control circuit RCNL. The write word lines WW0, WWL, WW2, WW3,… , And both ends of the source lines SL01, SL23,... Are controlled by a word line control circuit RCN and a RCF1 including a drive circuit. The source lines SL01, SL23,... May be applied with a fixed voltage such as the ground voltage VSS, or may be controlled to be floating at the time of writing as described in Reference 2. Data lines DLO, DLl, DL2, DL3, ... are controlled at both ends by data line control circuits CCN1 and CCF1 including a sense circuit and a drive circuit. Each memory cell includes one MTJ element MTJ and one transistor MT. One end of the MTJ element MTJ is connected to the data line, and the other end is connected to the drain of the transistor MT. The gate of the transistor MT is connected to the read mode line, and the source is connected to the source line.

 The operation of the memory cell array is performed in the same manner as the conventional MRAM cell array shown in FIG. However, since a memory cell is arranged at half of all the intersections of the word line and the data line, the lowest address is commonly used for selecting the data line and the word line when selecting the memory cell. As shown in Fig. 3, the read operation is performed by setting the read word line WR selected among WR0, WR1, WR2, WR3,… to a high level, according to the magnetic resistance of the MTJ element MT.J. , DL1, DL2, DL3,..., By detecting the current IDL flowing through the desired data line. On the other hand, as shown in FIG. 4, the write operation is performed by setting the current IWW of the write word line selected among the jobs, W1, WW2, W3,... As the write word line current IWS, and DL0, DLL, DL2, DL3, ... Write current ID1 or according to the write data to the data line selected in: or [Generates a magnetic field by flowing DO.

For example, let us consider a case in which a current flows through the write line WW1 and the data line DL1 in order to write to the memory cell MC11 in FIG. The four memory cells adjacent to the selected memory cell MC11 are MC00, C02, MC20, and MC22. These are adjacent to both the selected write mode line WW1 and the selected data line DL1, but since both are only affected by the leakage magnetic field, the combined magnetic field is sufficiently small. it can. The memory cell adjacent on the selected write word line WWl is MCL3, and receives a magnetic field due to the current of the write word line WW1, but since the data line DL2 is located far from the selected data line DLi, the distance is large. The leakage magnetic field due to the current of the data line DLi is small. The memory cell adjacent to the selected data line DL1 is MC31 and receives a magnetic field due to the current of the data line DL1, but there is a write mode line WW2 between the selected write mode line WW1 and the distance is large. Therefore, the leakage magnetic field due to the current of the write lead line WWi is small. As described above, by arranging the memory cells in a checker pattern, the leakage magnetic field is reduced in any of the unselected cells, and the possibility of being affected by the magnetization state can be avoided.

 In addition, if the influence of the leakage magnetic field of the write word line can be reduced by a structure or the like, a configuration may be adopted in which adjacent memory cells on the same data line are connected to adjacent write word lines. Conversely, if the influence of the leakage magnetic field of the data line can be reduced, an adjacent memory cell on the same write mode line may be connected to the adjacent data line.

Next, a specific layout and structure of the memory cell array shown in FIG. 1 will be described. Fig. 5 shows the layout of the MTJ element, and Fig. 6 shows the layout of the transistor. Here, in order to make the repetition unit easier to understand, the write cell line and the read cell line are each shifted by one line from the memory cell shown in FIG. A dotted rectangle MC is an area of one memory cell. In FIG. 6, FL is an active area pattern. FG is a transistor gate pattern corresponding to the read word lines WR1 to WR4. The area where the active area pattern FL and the gate pattern FG overlap is the channel of the power transistor. Here, it has the shape of a parallelogram. Ml is the first wiring layer pattern and is used for the source lines SL01, SL23, and SL45. LCT is a contact pattern from the diffusion layer to the first wiring layer. In Fig. 5, PL is the lower electrode pattern of the MTJ element, and town is the MTJ element. It is an element pattern. M2 is a second wiring layer pattern used for the write word lines WWl to WW4. M3 is a third wiring layer pattern, corresponding to the data lines DL0 to [((3). MCNT is a memory contact pattern, and the first wiring layer and the second wiring layer are separated from the diffusion layer. This is the pattern of the connection hole to the lower electrode of the MTJ element through the well-known optical lithography.

FIG. 7 shows a cross section taken along the line AA ′ and FIG. 8 shows a cross section taken along the line BB ′ of the layout memory cells of FIGS. 5 and 6. In these figures, 100 is a p-type semiconductor substrate. 101p is a p-type well formed in the memory cell array by ion implantation. No. 02 is an element isolation oxide film, which is formed by, for example, etching a substrate and burying the oxide film in a region not surrounded by the pattern F. Reference numeral 103 denotes an η-type diffusion layer serving as a source and a drain of the transistor. The η-type diffusion layer is formed by ion implantation after forming a gate, and is formed in an active region without the element isolation oxide film 102 and the gate L04. L04 is the gate of the transistor and is used as a read word line. Reference numeral 105 denotes a plug of a contact between the diffusion layer and the first wiring layer, which is a contact pattern formed according to CT and MCNT. 106 is a first wiring layer formed according to the pattern Ml. Reference numeral 107 denotes a connection hole between the first wiring layer and the second wiring layer, which is formed according to the contact pattern MCNT. L08 is no. This is the second wiring layer formed according to the turn M2, and the wiring that passes immediately below the MTJ element becomes the write data line. L09 is a memory contact connecting the second wiring layer and the lower electrode of the MTJ element, and is formed according to the memory contact pattern MCNT. 0 is the lower electrode of the MTJ element, which is processed according to the lower electrode pattern PL. It is desirable to use a material such as a noble metal suitable for forming a ferromagnetic material for this layer. 1 L 1, 1 12, and L are the ferromagnetic fixed layer, tunnel insulating film, and ferromagnetic free layer that constitute the MTJ element, and are formed by etching with the MTJ element pattern MT after lamination. LL 5 A third wiring layer formed according to the turn M3, which is in contact with the free layer L13 of the MTJ element and is used as a data line. Although not provided in the memory cell array, a through hole for connecting the second wiring layer 108 and the third wiring layer L15 is provided in the peripheral circuit region.

 Thus, the write word lines, the read word lines, and the data lines are arranged in accordance with the circuit diagram of FIG. As described above, in the present embodiment, the problem of disturbance to adjacent cells at the time of writing is avoided, so that the pitch of the write word line and data line can be reduced, and the memory cells can be highly integrated.

 Here, the shape of the MTJ element is made longer in the data line direction orthogonal to the word line and in the word line direction orthogonal to the data line. By adopting such a shape, the anisotropy of the ferromagnetic free layer 113 is increased, and the magnetic field due to the data line current is referred to as an easy axis, and the magnetic field due to a lead line current is referred to as a harness and a cis. Operation becomes possible. Furthermore, the M TJ element pattern MJ has a hexagonal shape with the corners of a rectangle dropped, enabling stable magnetic pole reversal. In the present embodiment, the MTJ elements having such a shape are arranged efficiently in a checker pattern.

 The MTJ element is provided between a write word line and a data line in order to efficiently apply a magnetic field during writing. Therefore, it is necessary to provide a memory contact to the lower electrode of the MTJ element, avoiding the write source line. With the above-mentioned shape, the MTJ element has a larger area than the memory contact. Therefore, a memory contact is arranged for every two write word lines to eliminate a useless area.

Next, the overall configuration of a memory using this memory cell array will be described. FIG. 9 is a main block diagram of a configuration example of the synchronous memory. Clock buffer CLKB, Command buffer CB, Command decoder CD, Address buffer AB, Column address counter YCT, Input buffer DIB, Output buffer A sector SCTO, SCT 1,... Including a memory array MAR is provided. The configuration shown in FIG. 1 is used as the memory array MAR in FIG. However, depending on the memory capacity, a plurality of such configurations may be provided repeatedly to form the memory array MAR in FIG. Also, although sectors correspond to banks, multiple sectors per bank may be used. The sector further includes a row predecoder XPD, a column predecoder YPD, a write buffer WB, and a main amplifier.

Each circuit block plays the following role. The clock buffer CLKB distributes the external clock CLK to the command decoder CD etc. as the internal clock CLKI. The command decoder CD generates control signals for controlling the address buffer AB, the column address counter YCT, the input buffer DIB, the output buffer DOB, and the like in response to an external control signal CMD. The address buffer AB takes in the external address ADR at a desired timing according to the external clock CLK and sends the low address I3X to the low address predecoder XPD. The row address predecoder XPD pre-decodes the row address BX and outputs a row predecode address CX and a mat select signal MS to the memory array MAR. The address buffer AB also sends the column address to the column address counter YCT. The column address counter YCT uses the address as an initial value, generates a column address BY for performing a burst operation, predecodes the column address by a column address predecoder YPD, and outputs a ram predeco-address CY to the memory array MAR. Output. The input buffer DI B takes in the data of the input / output data DQ with the external device at a desired timing and outputs the write data GI to the write buffer WB. The write buffer WB outputs the write data GI to the main input / output line MI0. On the other hand, the main amplifier MA amplifies the signal of the main input / output line MI0 and outputs the read data G0 to the output buffer D0B. Output buffer D0B outputs read data G0 to input / output data DQ at desired timing. You.

 Thus, a synchronous memory can be realized using the memory cell configuration according to the present invention. Synchronous memory that fetches command addresses and inputs / outputs data in synchronization with external clock CLK enables operation at high frequencies and achieves high data rates it can. MRAM by Akira Kizaki can apply various high-speed memory methods that have been questioned about SRAIV [and DRAM. It is needless to say that the present invention can be applied not only to a single MRAM but also to a general semiconductor device such as a system incorporating a MRAM and S1.

FIG. 10 shows an example of the timing of the read operation in the configuration example shown in FIG. The operation of the synchronous memory in FIG. 9 will be described according to the timing chart. Each time the external clock CLK rises, the command decoder CD determines the control signal CMD. When the read command R is given, the row address and the column address are taken into the address file A1 from the end address ADR. The address buffer AB outputs the address BX. In response to this, in the sector SCT0 or SCn, the row address predecoder XPD outputs the row predecode address CX, and in the memory MAR, the lead line WL shown in FIG. Selected. The column address counter YCT operates every clock cycle with the column address fetched into the address buffer AB as the initial value, and the column address predecoder YPD outputs the column address BY corresponding to the burst operation. In response, the column address predecoder YPD outputs the column predecoder address CX in the sector SCT0 or SCTL, and selects the read data line DR shown in Figure] in the memory array MAR. . As a result, a signal is read out to the main input / output line M I0, the main amplifier MA outputs read data GO, and the output buffer DOB outputs data at the timing according to the external clock CLK. Output. Here, the row address and the column address are simultaneously acquired by the read command R. As a result, in the DRAM, there is no delay time generally required between the capture of the row address and the capture of the column address, and only the information of the selected data line can be detected. Unlike DRAM, MRAM can perform non-destructive readout and does not need to detect data in all memory cells on a word line, so this operation is possible. Power consumption can be reduced by detecting only the information of the selected data line.

 (Second embodiment)

FIG. 11 shows a memory cell array of the MRAM of the second embodiment. The feature is that the order of the read-out read lines is changed with respect to the memory cell array of the first embodiment. As in the first embodiment, the write word lines are arranged in the order of WW1, WW2, W3,..., Whereas the read word lines are arranged in the order of WR0, WR2, WR1, WR3,. I have. Source lines SL02, SL13,... Are arranged in the same direction as the read word lines. At the intersections between the write word lines and the data lines DL0, DL1, DL2, DL3,…, in the form of a checker pattern, memory cells MC00, MC02, MC11, MC13, C20, C22,…, MC31, MC33, ... Provided. Like the first embodiment, the write word lines 0, WW1, WW2, WW3,... And the read word lines WRO, WR1, WR2, WR3,. Are controlled by word line control circuits RCN2 and RCF2, and both ends of data lines DL0, DL1, DL2, DL3,... Are controlled by data line control circuits CCN2 and CCF2 including a sense circuit and a drive circuit. Each memory cell consists of 1. MTJ element iMTJ and: L transistor MT. One end of each of the MTJ elements ΜΤ and Ι is connected to the data line, and the other end is connected to the drain of the transistor ΜΤ. The gate of transistor ΜΤ is connected to the read word line, and the source is connected to the source line. Such a memory cell configuration ^s is repeated for every four write word lines and every four read word lines. Note that in FIG. 1 メ モ リ, the memory cell MCL (), the write word line WW2 force; and the memory cell MC21, C23, the write word line WWL pass through. This is independent of the memory cell configuration, as shown in the layout below.

 Fig. 12 shows the layout of the MTJ element, and Fig. L3 shows the layout of the transistor. Again, in order to make the repetition unit easier to understand, the write cell line and the read cell line are shifted by L lines from the memory cell shown in FIG. The dotted rectangle MC is an area of メ モ リ memory cells. FIG. 12 has the same layout as that of FIG. 5, but in FIG. 3, the shape of the active region pattern FL is different from that of FIG. 6 and is rectangular. FG is the gate pattern of the transistor and is used as a read word line arranged in the order of WR2, W1U, WR3, WR4. Mi is the first wiring layer pattern, and LCT is the contact pattern from the diffusion layer to the second wiring layer. In FIG. 12, P denotes the lower electrode pattern of the MTJ element, and M.T denotes the MTJ element pattern. M2 is a second wiring layer pattern, which is used for write word lines arranged in the order of WW, 2, WW3, WW4. M3 is a third wiring layer pattern and is used as a data line. In FIGS. 12 and 3, MCNT is a memory contact pattern.

 With regard to the memory cells of the layouts of FIGS. 12 and 13, FIG. 14 shows a section taken along the line Λ-Λ, and FIG. 15 shows a section taken along the line BB ′. Similar to FIGS. 7 and 8, in these figures, 100 is a ρ-type semiconductor substrate, LO L p is a ρ-type well, L02 is an inter-element isolation oxide film, 103 is an n-type diffusion layer, and 104 is a transistor transistor gate. L05 is a plug of a contact between the diffusion layer and the first wiring layer, L06 is a first wiring layer, 107 is a connection hole between the first wiring layer and the second wiring layer, 108 is a second wiring layer, L09 is the memory contact, U0 is the lower electrode of the MTJ element, Lil, L12, and L13 constitute the MTJ element, and 5 is the third wiring layer.

In this embodiment, the memory cells connected to the same data line Every other lead wire is adjacent to the read lead line, but adjacent to the read lead line. The problem of disturbing adjacent cells at the time of writing is not related to the read-out read line, and as in this embodiment, the MTJ element must be in a checker pattern for the data line and the write-out line. The effect can be reduced by arranging the memory cells. In this embodiment, the memory cells connected to the adjacent read-out line are connected to the same data line, so that the channel shape of each transistor is made rectangular. As a result, the gate and the isolation oxide film do not intersect at an acute angle, and the performance improvement including the reliability of the transistor MT becomes easy.

 (Third embodiment)

 FIG. 16 shows a memory cell array of the MRAM of the third embodiment. The feature is that one read lead line is used for two write lead lines. Write word line, read word line WR01 and source line SL01 corresponding to WW1 There are two write word lines, read word line WR23 and source line SL23 corresponding to WW3. At the intersection of the write word line, read word line and source line and the data lines D and 0, DL1, D and 2, DL3, ..., memory cells MC00, MC02, ..., MC11, MC13, MC20, MC22, MC31 , C33,… are provided. As in the first or second embodiment, the write word lines WW0, WW, WW2, WW3,... And the read word lines WR0, WR1, WR2, WR3,. Are controlled by word line control circuits RCN3 and RCF3, and both ends of the data lines DL0, DL1, DL2, DL3,... Are controlled by data line control circuits CCN3 and CCF3 including a sense circuit and a drive circuit. Each memory cell includes one MTJ element MTJ and one transistor MT. The memory cell configuration is repeated for every two write word lines and every one read word line.

Since the number of write read lines and the number of read read lines are different, the address decoding method for selecting read lines differs between read and write. However, the read mode line can be selected according to the addresses of two write word lines, so that the implementation is easy.

Fig. 17 shows the layout of the MTJ element, and Fig. 18 shows the layout of the transistor. The feature is that the source lines are wired by diffusion layers, and the CT used in FIG. 6 or FIG. 13 is eliminated by using the 1st-wiring layer pattern Ml and the contact pattern. Here, the area shifted from the memory cell shown in FIG. 16 by two write word lines in the data line direction, that is, by one read mode line, and by one data line in the read line direction. Is shown. Dotted rectangle MC force 1. This is the area of one memory cell. In Fig. 1_7, the force has the same layout as in Fig. 5 or Fig. 12; in Fig. 18, the shape of the active region pattern FL differs from that in Fig. 6 or Fig. I have. FG is a gate pattern of a transistor and is used as a read word line. In FIG. 17, PL is the lower electrode pattern of the MTJ element, and MI is the MTJ element pattern. M2 is a second wiring layer pattern, which is used for a write lead line. Is a third wiring layer pattern, which is used as a data line. . In Figure 1 7 and 1 8, MCNT, for _c Zu丄7 and Reiau Bok of the memory cell of FIG. 1 8 is a memory configuration Takt pattern from the diffusion layer to the MTJ element lower electrode through a second wiring layer , FIG. L9 shows a / \-/ \ 'section, and FIG. 20 shows a BB' section. As in FIGS. 7 and 8 or FIGS. 4 and 15, in these figures, L00 is a p-type semiconductor substrate, l OL p is a _p- type well, 102 is an element isolation oxide film, and L03 is an n-type. The diffusion layer, L04, is the transistor gate. 105 is a contact plug between the diffusion layer and the second wiring layer because there is no first wiring layer. Reference numeral 108 denotes a second wiring layer, L09 denotes a memory contact, 0 denotes a lower electrode of the MTJ element, 111, L12, and 3 form an MTJ element, and L L5 denotes a third wiring layer. Unlike FIG. 8 or FIG. 15, FIG. 20 shows a cross section in which diffusion layers serving as source lines are continuously formed. In this embodiment, the diffusion layer is used as a source line, and the first wiring layer is omitted from the structures of the first and second embodiments. As a result, the manufacturing process for the one-layer wiring layer can be eliminated, and the cost can be reduced. Here, by arranging the MTJ element layout for every two write lead lines, the interval between the memory contacts can be relatively large, so that the diffusion layer serving as the source line can be formed. The width can be secured to reduce the resistance. It should be noted that even in the case of the layout as in the first or second embodiment, it is possible to form a source line using a diffusion layer if the distance between gate patterns serving as read-out read lines is increased. In particular, in the second embodiment, since the active region has a layout orthogonal to the source lines as shown in FIG. 13, it is necessary to connect the diffusion layers in the read-out line direction to form the source lines. The patterning of the active region is easy. Further, in the present embodiment, the number of read word lines is reduced to L for two write word lines, and the width of the diffusion layer serving as a source line is increased to reduce the resistance.

 In this embodiment, one read word line is used for two write word lines, so that the memory cells connected to the same data line are connected with respect to the read word line as in the second embodiment. Are adjacent. As described above, the problem of disturbing adjacent cells at the time of writing is unrelated to the read line, and in this embodiment, the MTJ element is a checker pattern for the data line and the write word line. Since the memory cells are arranged as described above, the effect can be reduced.

 (Fourth embodiment)

FIG. 21 shows a memory cell array of the MRAM of the fourth embodiment. The feature is that the memory cell is composed of two transistors MTL and MTR and MT MTJ elements MTJ. Read word lines WR01 L, WR01 R, WR23 L, WR23R, ... are arranged corresponding to the write word lines WW0, Wi, WW2, WW3, .... In the same direction as the read word line, the source lines SLO, SL 12, SL34, ... are arranged. At the intersection of the write word line and the data line DL0, DL1, 1) and 2, DL3, ..., a memory pattern MCOO, MC02, MC11, MC13, ..., MC20, C22, MC31, MC33,. ..,… are provided. As in the first embodiment, the write word lines WWO, WW1, WW2, WW3,… and the read word lines WR01L, WROIR, WR23, WR23R,… and the source lines SL0, SL12, SL34,… The data lines DLO, DL1, DL2, DL3,… are controlled at both ends by the data line control circuits CCN4, CCF4 including the sense circuit and the drive circuit, controlled by the word line control circuits RCN4, RCF4 including the drive circuit. You. Here, the write mode lines WR01L and WROIR, WR23L and WR23R,... Are paired and connected to the gates of two transistors MTL and MTR in the memory cell. A pair of two connected to the same memory cell performs the same control on the write line. That is, physically, there are two read word lines, but logically, there are two read word lines. Also, the transistors in the memory cell perform the same operation in parallel and are physically two transistors, but logically one transistor. Each memory cell is composed of one MTJ element MTJ and one transistor MT. One end of the MTJ element MTJ is connected to the data line, and the other end is connected to the drain of the transistor MT.

Figure 22 shows the layout of the MTJ element, and Figure 23 shows the layout of the transistor. Here, an area shifted from the memory cell shown in FIG. 21 by two write code lines in the data line direction, that is, one pair of read read lines, and shifted by t data lines in the read line direction is shown. ing. FIG. 22 has a layout similar to that of FIG. 5 and the like, but in FIG. 23, the shape of the active region pattern FL is different from that of FIG. FG is a transistor gate pattern and is used as a read word line. Ml is the first wiring layer pattern, and LCT is the contact pattern from the diffusion layer to the first wiring layer. In Figure 22, PL is the lower electrode pattern of the MTJ element, MJ is an MTJ element pattern. M2 is a second wiring layer pattern used for a write word line. M3 is a third wiring layer pattern, which is used as a data line. MCNT is a memory contact pattern.

 Regarding the memory cells of the layouts of FIGS. 22 and 23, FIG. 24 shows an AA ′ section, and FIG. 25 shows a BB ′ section. As in FIGS. 7 and 8 or FIGS. 14 and 15, in these figures, 100 is a p-type semiconductor substrate, LO lp is a p-type well, 102 is an element isolation oxide film, and 丄 03 is an n-type. Diffusion layer, 104: gate of transistor, 105: plug for contact between diffusion layer and first wiring layer, L06: first wiring layer, 107: connection hole between first and second wiring layers Reference numeral 108 denotes a second wiring layer, 109 denotes a memory contact, 110 denotes an MTJ element lower electrode, 1, 1 12, and 13 constitute an MTJ element, and 115 denotes a third wiring layer.

 In this embodiment, two transistors in the memory cell are connected in parallel to reduce the on-state resistance. As described above, in the read operation, the resistance change rate of the MTJ element is detected. The rate of change in resistance of the MTJ element is at most about several tens of percent, and for detection thereof, the on-resistance of the transistor must be sufficiently lower than the resistance of the MTJ element. Since the resistance value of the MTJ element cannot be increased so much in terms of operating speed, it is desirable to reduce the on-resistance of the transistor. Reference 1 discloses that two transistors are connected in parallel and used for a memory cell. In the present embodiment, this method is realized with an efficient layout by arranging the MTJ elements in a checker pattern, taking advantage of the relatively large space between the memory contacts. In some cases, patterning the active region pattern FL in a linear band facilitates patterning, reduces its space, increases the channel width of the transistor, and reduces the transistor resistance. It is also possible to convert.

 (Fifth embodiment)

FIG. 26 shows a memory cell array of the MRAM of the fifth embodiment. Note The feature is that the recell consists of two transistors MTb and MTt and two MTJ elements MT.Tb and MTJt. Similarly to the first embodiment shown in FIG. 5, read word lines RO, WR1, WR2, WR3,... Are arranged corresponding to the write word lines WWO, W1, 丽 2, W3,. , Source lines SL01, SL23,... Are arranged in the same direction as the read word lines. On the other hand, the data lines are paired, and DLOb and DL0t, DLlb and DLU,. Memory cells MC00, MCL1,..., MC20, MC31,...,... Are provided at checkpoint patterns at intersections of the write / read line and the data line pair. One end of each of the MTJ elements MTJh and MTJt in each memory cell is connected to the data line pair, and the other end is connected to the drains of the transistors MTb and MTt. The gates of the transistors MTh and MTt are connected to the read mode line, and the sources are connected to the source line. As in the first embodiment, the write word line, the read mode line, and the source line are controlled by the read line control circuits RCN5 and RCF5 including the drive circuit, and the data line pair is connected to the sense circuit and the drive circuit. Both ends are controlled by the data line control circuits CCN5 and CCF5 including the circuit.

The operation of the memory cell array is performed as follows, with complementary information stored in the MTJ element in the memory cell. In the read operation, as shown in FIG. 27, by setting the read word line WR selected among WRO, WR1, WR2, WR3,... To a high level, the transistors in the memory cells connected to the word line are changed. Turn on MTb and MTt and apply voltage to the terminals of MTJ element MT.Tb and TJb. Current flowing through a desired data line pair in DLOb and DL0t, DLib and DLlt,... According to the magnetoresistance of MTJ elements MTJb and MTJb: [Read stored information by comparing DLb and IDLt. . On the other hand, as shown in FIG. 4, the write operation is performed by setting the current TWW of the write source line selected among WWO, WW1, WW2, WW3,... As the write source line current IWS, and the DLOb, DL0t, DLlb DLit,… Write to the selected data line pair according to the write data This is performed by generating a magnetic field by passing a current. The currents IDLb and IDLt of the selected data line pair at this time are complementarily positive ID1 and negative: [DO.

 This embodiment uses a memory cell composed of two transistors and two MTJ elements as in Reference 1. This memory cell is called a twin cell because it uses two complementary memory cells consisting of one transistor and one MTJ element. Although the cell area is larger than that of the memory cell of the first embodiment, stable operation is easy. In the read operation, it is sufficient to compare the currents of the data line pairs, and it is not necessary to generate a reference signal. In the write operation, control is easy because the current flows so that the current reciprocates in the data line pair.

 In this embodiment, disturb at the time of writing is reduced by arranging the memory cells in a checker pattern. In particular, the leakage magnetic field due to the current in the data line is reduced by arranging the data line paired with the adjacent data line next to the data line and flowing the current in the opposite direction. Also, adjacent memory cells on the selected write word line have a data line pair between the selected data line pair and the distance is sufficiently large, so that the leakage magnetic field due to the current of the data line pair is small.

FIG. 29 shows the layout of the MTJ element, and FIG. 30 shows the layout of the transistor. Here, an area shifted from the memory cell shown in FIG. 26 by i write and read read lines in the data line direction and by one data line in the read line direction is shown. The layout is line-symmetric between the data line pairs. In FIG. 30, FL is an active region pattern, and FG is a gate pattern of a transistor, which is used as a read-out line. Ml is the first wiring layer pattern, and LCT is the contact pattern from the diffusion layer to the first wiring layer. In Fig. 29, PL is the lower electrode pattern of the MTJ element, and Machi is the MTJ element pattern. M2 is a second wiring layer pattern, which is used for a write lead line. M3 is the third wiring layer pattern, Used as data line. Unlike the layout shown in FIG. 5, the layout is changed in width depending on the presence or absence of the corresponding MTJ element. In FIGS. 29 and 30, MCNT is a memory contact pattern.

 In the memory cells having the layouts of FIGS. 29 and 30, the cross section taken along the line AA ′ is as shown in FIG. 7 as in the first embodiment. FIG. 31 shows a BB ′ cross section. 100 is a p-type semiconductor substrate, 101p is a p-type well, 02 is an element isolation oxide film, L04 is a transistor gate, L08 is a second wiring layer, 109 is a memory contact, and 110 is a MTJ element lower electrode. Yes, L11, 112 and 1L3 constitute the MTJ element, and L15 is the third wiring layer. In this cross section, the η-type diffusion layer, the plug of the contact between the diffusion layer and the first wiring layer, the connection hole between the first wiring layer, and the first and second wiring layers are not provided.

 Also in this embodiment, the shape of the MTJ element is longer in the word line direction orthogonal to the data lines than in the data line direction orthogonal to the word lines. By changing the line width of the data line depending on the presence or absence of the MTJ element, the MTJ element is efficiently arranged in this shape.

 (Sixth embodiment)

FIG. 32 shows a memory cell array of the MRAM of the sixth embodiment. The feature is that an adjacent write mode line is used as a source line. Read word lines WR0, WR1, WR2, WR3, ... are arranged corresponding to the write word lines WW0, WW1, WW2, WW3, .... At the intersection of the write word line and read word line with the data line D, 0, DLL, DL2, DL3,…, in a checker pattern, memory cells MC00, MC02,…, MCLL, MCL3,…, MC20, MC22 ,…, MC: U, MC33,. Each memory cell is connected to an adjacent write word line, for example, the memory cells MC00 and MC02 are also connected to a write word line WW1, and the memory cells MC11 and MC13 are also connected to a write word line WW0. The write word lines WW0, WW1, WW2, 3,… and the read word lines WRO, WR1, WR2, WR3,… are controlled by the word line control circuits RCN6 and RCF6 including the drive circuit and the data lines. DLO, DL1, DL2, DL3, ... are controlled at both ends by the data line control circuits CCN6 and CCF6 including the sense circuit and the drive circuit. Each memory cell includes an MTJ element MTJ and a transistor MT. One end of the MTJ element MT.T is connected to the data line, and the other end is connected to the drain of the transistor MT. The gate of the transistor MT is connected to a read mode line, and the source is connected to an adjacent write mode line. That is, instead of being connected to the source line as in the first embodiment, it is connected to the adjacent write code line.

As described with reference to FIG. 4, at the time of the read operation of the memory cell, it is not necessary to supply a current to the write line, and a desired voltage can be maintained. In addition, during the write operation, the transistor MT in the memory cell is off, so that even if a current flows through the write word line, there is no danger that the current will flow through the transistor MT. Therefore, as in this embodiment, an adjacent write line can be used as a source line. Figure 33 shows the layout of the MTJ element, and Figure 34 shows the layout of the transistor. The first wiring layer pattern Ml used in the first embodiment and the like is deleted. Here, an area shifted from the memory cell shown in FIG. 16 by two write and read read lines in the data line direction and one data line in the pad line direction is shown. . Dotted rectangular MC force; area of one memory cell. In FIGS. 33 and 34, MCNT is a memory contact pattern from the diffusion layer to the lower electrode of the MTJ element via the second wiring layer, and WCT is a contact pattern from the diffusion layer to the second wiring layer. is there. FIG. 33 has the same layout as in FIG. 17 etc., but in FIG. 34, the active area pattern FL is extended and sewn due to the layout of the contact to the second wiring layer. Thus, the gate pattern FG of the transistor that is the read word line is arranged. In FIG. 33, PL is the lower electrode pattern of the MTJ element, and MT is the MTJ element pattern. M2 is The second wiring layer pattern is used for a write word line. M3 is a third wiring layer pattern and is used as a data line.

 Regarding the memory cells having the layouts shown in FIGS. 33 and 34, FIG. 35 shows an AA ′ section, and FIG. 36 shows a BB ′ section. As in FIGS. 19 and 20, in these figures, L00 is a p-type semiconductor substrate, LO lp is a p-type well, L02 is an element isolation oxide film, L03 is an n-type diffusion layer, and L04 is The gate of the transistor, K) 5 is the plug of the contact between the diffusion layer and the second wiring layer, L08 is the second wiring layer, L09 is the memory contact, and 110 is the lower electrode of the MTJ element. , UL, 112, 〖L: 3 constitute the MTJ element, and U5 is the third wiring layer. The contact plug 105 is formed according to the contact patterns MCNT and WCT.

 In this embodiment, the first wiring layer is omitted from the structure of the first or second embodiment by using the adjacent write word line as the source line. As a result, the manufacturing process for one wiring layer can be eliminated, and the cost can be reduced. Although the diffusion layer can be used as the source line as in the third embodiment, the influence of the wiring resistance can be reduced by using the write word line as the source line as in the present embodiment. In this embodiment, the write word line is connected to two adjacent memory cells, but one of them replaces the source line, and the influence of disturbance on the adjacent cells during writing can be reduced.

 When used as the write word line and source line, there is a concern that the transistor ON resistance may be added due to the drive circuit in the read line control circuits RCN6 and RCF6 for controlling the write word line. Is done. However, as shown in Fig. 4, it is only necessary to supply a current to the write line in one direction, so one of the write line control circuits RCN6 and RCF6 connects the write line to a fixed voltage. It is also possible to prevent the resistance from being added.

 (Seventh embodiment)

FIG. 37 shows a memory cell array of the MRAM of the seventh embodiment.ヮ The feature is that the read line is alternately used as a write line and a read line in memory cells adjacent to each other in the line direction. At the intersection of the code lines WO, Wl, W2, W3, W4, W5, W6, W7, ... and the data lines DL0, DLL, 0 to 2, D to 3, ..., the memory cells MC00 for every two lines , MC02, MCll, MCI 3,…, C20, MC22, MC31, MC33, ■ .., MC40, MC42, .., C51, MC53,…, C60, MC62,…,

MC71, MC73, ..., ... are provided. In addition, source lines SLO, SL12, SL34, SL56, SL78 ... are arranged for every two word lines. The word lines W0, Wl, W2, W3, W4, W5, W6, W7, ... are controlled at both ends by word line control circuits RCN7, RCF7 including the drive circuit, and the data lines DLO, DL1, DL2, D ,... Are controlled at both ends by data line control circuits CCN7 and CCF7 including a sense circuit and a drive circuit. Each memory cell includes an MTJ element MTJ and a transistor MT. One end of the TJ element MT.J is connected to the data line, and the other end is connected to the drain of the transistor MT. The gate of the transistor MT is connected to the gate line. The source is connected to the source line. However, the role of the word line is alternated for each data line between a write word line that applies a magnetic field to the MTJ element and a read word line connected to the gate of the transistor. For example, in the memory cells MCOO, MC20, MC40, and MC60 connected to the data line DL0, the lead lines W0, W2, W4, and W6 work as write lead lines, and the lead lines Wl, W3, W5 , W7 are connected as read word lines. On the other hand, in the memory cells MCll, MC1, MC5L, connected to the data line DL1, the read lines Wt, W, 5, W7 function as write word lines, and the word lines WO, W2, W4, W6 read out. It is connected as a lead line.

As described with reference to FIG. 4, during the read operation of the memory cell, it is not necessary to apply any of the current and the voltage to the write word line, and during the write operation, the read word line is not applied. There is no need to apply both current and voltage. Therefore, normal operation is possible even if the word line is used as a write word line or a read word line, as described above. Fig. 38 shows the layout of the MTJ element, and Fig. 39 shows the layout of the transistor. M2 is a second wiring layer pattern, and FG is a transistor gate pattern, both of which are used for word lines. The FCT is a contact pattern from the gate to the second wiring layer via the wiring layer. FL is the active region pattern, Ml is the first wiring layer pattern, LCT is the contact pattern from the diffusion layer to the first wiring layer, PL is the lower electrode pattern of the MTJ element, and MJ is the MTJ element pattern. M3 is a third wiring layer pattern used as a data line. MCNT is a memory contact pattern. If necessary, the contact pattern FCT from the gate via the first wiring layer to the second wiring layer can be thinned out.

Regarding the memory cells of the layouts of FIGS. 38 and 39, FIG. 40 shows an AA ′ section, and FIG. 41 shows a BB ′ section. 105f is a contact plug of the gate and the first wiring layer, and is formed according to the contact pattern FCT in FIG. Other symbols are the same as those in FIGS. 7 and 8, such as 100 is a p-type semiconductor substrate, lOLp is a p-type transistor, 102 is an element isolation oxide film, 103 is an n-type diffusion layer, and 104 is a transistor. , 05 is a plug for the contact between the diffusion layer and the first wiring layer, 106 is the first wiring layer, 107 is the connection hole between the first wiring layer and the second wiring layer, and 108 is the second wiring Layer 109 is a memory contact, L10 is a lower electrode of the MTJ element, 111, 112, and L13 constitute the MTJ element, and 115 is a third wiring layer. However, the connection hole 107 is formed in accordance with the contact pattern FCT in addition to the memory contact pattern MCNT shown in FIGS. 38 and 39. As described above, by connecting the gate 104 serving as a read lead line to the second wiring layer 108 serving as a write lead line, the read operation can be sped up. The gate 104 is generally formed of polysilicon, polysilicon, or some metal, such as polymetal in which polysilicon and metal are laminated, and has a higher sheet resistance than a metal wiring layer. By connecting this to the second wiring layer, the influence of the sheet resistance of the gate 104 is reduced, and this is used for reading. -The rise and fall times of the gate line can be shortened. Literature 2 discloses a configuration in which a read line and a write line are connected by the edge of a memory cell array.In this embodiment, however, the connection is made by a large number of connection holes in the memory array. The effect of shunting the gate with the metal wiring layer is great. In Reference 2, since the read and write read lines connected to the same memory cell are connected, the write word line and the data line, which carry current respectively at the time of writing, Current may flow. This is because, when a current flows through the write word line, the voltage of the read word line changes, and the transistor in the memory cell may be turned on. In this embodiment, this problem does not occur because the read word line and the write word line of each memory cell are provided separately. Even if the gate voltage rises to allow the current to flow through the second wiring layer, the transistor of the selected memory cell remains off, and does not interfere with the selected data line through which the current flows for writing. Even if a transistor may be turned on in a non-selected memory cell where the data line is not selected, unnecessary current does not flow if the non-selected data line is left floating at that time. In this embodiment, such a configuration is efficiently laid out by arranging the MTJ elements in a checker pattern. In this embodiment, the read line is connected to two adjacent memory cells.On the other hand, the read line is a gate and the other is a second wiring layer which is a write word line. In addition, the influence of disturbance on adjacent cells during writing can be reduced.

 (Eighth embodiment)

FIG. 42 shows a memory cell array of the MRAM of the eighth embodiment. The feature is that data lines are paired, and memory cells are connected so that read current flows between pairs of data lines. The read word lines WR0, WR1, R2, WR3,... Are arranged corresponding to the write word lines WWO, WW, WW2, W3,. At the intersection of the write and read line and data line pair DLOu and DL01, DLlu and DL11, DL2u and DL21, DL3u and DL31, ..., memory cells MC00, C01, C02, MC03, MC10, MC11, MCL2, MC13 , MC20, MC21, C22, MC23, C30, MC31, C32, MC33, ..., ... are provided. The read word lines WW0, WW1, WW2, WW3, ... and the read word lines WR0, R1, WR2, WR3, ... are controlled by read line control circuits RCN8, RCF8 including a drive circuit, and the data line pair DLOu , DL01, DLlu, DLll, DL2u, DL21, DL3u, DL31, ... are controlled at both ends by data line control circuits CCN8, CCF8 including sense circuits and drive circuits. Each memory cell includes an MTJ element MTJ and a transistor MT. One end of the MTJ element MTJ is connected to one of the data line pairs, and the other end is connected to the drain of the transistor MT. The gate of the transistor MT is connected to the read mode line, and the source is connected to the other of the data line pair. That is, as in the first embodiment, instead of being connected to the source line, it is connected to the other of the data line pair. Here, adjacent memory cells connected to the same data line pair have opposite connections to the data line pair. For example, in memory cell MC00, MTJ element MT.J is connected to data line DLOu, and transistor MT is connected to data line DL01, whereas in memory cell MC10, MTJ element iMTJ is connected to data line DL01. And the transistor MT is connected to the data line DLOu.

The operation of the memory cell array is performed as follows. In the read operation, as shown in Fig. 43, the read line selected in Book 0, WR1, WR2, WR3, ... is set to the high level, so that the memory cells connected to the read line can be read. Then, the transistor MT is turned on, and a voltage is applied between the terminals of the MTJ element MT.T. Detects the current IDLu and IDL1 flowing through the desired data line pair among the DLOu and DL01, DLlu and DL11, DL2u and DL21, DL3u and DL31,… in accordance with the magnetic resistance of the MTJ element MT.I. By doing so, the stored information is read. On the other hand, as shown in Fig. 44, the write operation is performed for WW0, WW1, WW2, WW3, … The current I of the selected write line is selected as the write line current IWS, and D and Ob and DL0t, DLlb and DLlt, are connected to the MTJ element MTJ on one of the data line pairs selected in…. A magnetic field is generated by applying a write current ID1 or ID0 according to the write data to the data line. FIG. 44 shows a case where a memory cell to which the MTJ element MTJ is connected is selected and written to the data lines DL0u, DLlu, DL2u, DL3u,..., And the data line selected among them is shown. Is the write current IDt or ID0. When selecting and writing to the memory cells connected to the MTJ element MTJ on the data lines DL01, DLU, DL21, DL31,…, contrary to FIG. The current IDL1 is set as the write current ID1 or ID0.

 Figure 45 shows the layout of the MTJ element, and Figure 46 shows the layout of the transistor. The first wiring layer pattern Ml used in the first embodiment and the like is deleted. Dotted rectangular MC is the area of L memory cells. In FIGS. 45 and 46, MCNT is the memory contact pattern from the diffusion layer to the lower electrode of the MTJ element via the second wiring layer, and DLCT is the third contact pattern from the diffusion layer via the second wiring layer. This is a contact pattern to the wiring layer. In FIG. 45, PL is the lower electrode pattern of the MTJ element, and is the MTJ element pattern. M2 is a second wiring layer pattern used for a write word line. M3 is a third wiring layer pattern and is used as a data line. In FIG. 46, the active region pattern FL is greatly inclined with respect to the data line due to the layout of the contact from the diffusion layer to the third wiring layer. FG is a gate pattern and is used as a read mode line.

With respect to the memory cells of the layouts of FIGS. 45 and 46, FIG. 47 shows a section taken along the line-′, and FIG. 48 shows a section taken along the line BB ′. As in FIGS. 19 and 20 and FIGS. 33 and 34, in these figures, 100 is a ρ-type semiconductor substrate, 〖0Lp is a ρ-type semiconductor, L02 is an element isolation oxide film, and L03 is n. Type diffusion layer, L04 is transistor L05 is a plug of a contact between the diffusion layer and the second wiring layer, 108 is a second wiring layer, 109 is a memory contact, L10 is a lower electrode of the MTJ element, and 111, 112, and 3 are An MTJ element is formed, and LL5 is a third wiring layer. The contact plug 105 is formed according to the contact patterns MCNT and DLCT. U4 is a connection hole from the second wiring layer to the third wiring layer, and is formed according to the data line contact pattern DLCT.

 In this embodiment, the first wiring layer used as the source line in the first embodiment and the like is deleted by using the data lines as the pair lines. As a result, the manufacturing process for one wiring layer can be eliminated, and the cost can be reduced. Although the diffusion layer can be used as the source line as in the third embodiment, the effect of the wiring resistance can be reduced in the present embodiment using the metal wiring layer. In addition, when reading data from a plurality of memory cells at the same time, the current does not concentrate on the source line, so that the effect of wiring resistance is small. Also, since the signal current is read out to both data line pairs, the read current can be effectively doubled by taking the difference between the currents in the data line pairs. This makes it possible to increase the S / N and speed up the reading operation. In this embodiment, the data line is connected to two adjacent memory cells. However, since tV [every TJ element MT.J is connected to the adjacent memory cell, the data line is connected to the adjacent cell at the time of writing. The effect of the disturbance can be reduced.

 (Ninth embodiment)

Next, a ninth embodiment in which the shape of the MTJ element is devised will be described. The memory cell array is configured as shown in FIG. 1, as in the first embodiment. Figure 49 shows the layout of the MTJ element. The layout of the transistor should be as shown in Figure 6. Similar to FIG. 5, the write and read read lines are shifted by i each from the memory cell shown in FIG. 1, and the rectangular MC indicated by the dotted line represents the area of メ モ リ memory cells. is there. PL is the lower electrode pattern of the MTJ element, is the pattern of the MTJ element — M2 is a second wiring layer pattern used for the write word lines WW1 to WW4. M3 is a third wiring layer pattern, and corresponds to the data lines DL0 to DL3. Furthermore, MCNT is a memory contact pattern, and the layout shown in Fig. 5, which is a pattern of connection holes from the diffusion layer to the lower electrode of the MTJ element via the first and second wiring layers, In this layout, the longitudinal direction is alternately inclined for each writing lead line, whereas the hexagon is a hexagon and the lead line direction is the longitudinal direction.

 Even in the memory cell having the layout shown in FIG. 50, the cross section taken along the line AA ′ is as shown in FIG. FIG. 50 shows a B-β 'cross section. As in FIG. 7, 100 is a ρ-type semiconductor substrate, Ιρ is a p-type well, 102 is an isolation oxide film, 104 is a transistor gate, 108 is a second wiring layer, 109 is a memory contact, 0 is an MTJ element lower electrode, 111, 112, and L13 constitute an MTJ element, and 115 is a third wiring layer. In this section, the n-type diffusion layer, the plug of the contact between the diffusion layer and the first wiring layer, the connection hole between the first wiring layer and the first and second wiring layers are not visible.

The read operation of this memory cell array is performed as shown in FIG. 3, as in the first embodiment. FIG. 51 and FIG. 52 show the write operation. The feature is that the current of the write word line is controlled by the write operation, and the polarity is switched for each write word line. In the memory cell array configuration of FIG. 1, the current flowing through the word line control circuit RCN1 from the word line control circuit RCF1 is assumed to be positive. Regarding the current of the data line, the current flowing from the data line control circuit CCNL to CCF1 is assumed to be positive. If the selected write word line is any of the even-numbered WW0, W2,…, as shown in Figure 51, the current IWWe of the selected write word line is The positive write word line current IWp is used, and when writing '0', the negative write word line current IWn is used. On the other hand, the book to select If the write word line is one of the odd-numbered WW and WW3,…, as shown in Figure 52, the current IWWo of the selected write word line and the negative writeヮ Assuming that the lead line current is IWn, when writing '0', a positive write word line! ; Flow IWp. In either case, the current of the data line selected among DL0, DL1, DL2, DL3, ... is set to positive write current ID1 or negative ID0 according to the write data.

 In this way, by driving, the combined magnetic field to the MTJ element of the selected memory cell due to the currents of the write select line and the data line changes according to the write data in a direction close to the longitudinal direction of the M: TJ element. The writing can be easily performed by reversing the magnetization of the free layer. On the other hand, the MTJ element of the memory cell MC22 when writing to the memory cell MC22, which is adjacent to the selected write line and the selected data line, for example, the memory cell MC22 in FIG. Is applied. In this direction, the magnetization reversal of the free layer hardly occurs due to shape anisotropy. Therefore, the influence of the disturbance is smaller than in the first embodiment using the layout of FIG.

 A method of alternately arranging the magnetoresistive elements with respect to the lead wire in this manner is disclosed in Reference 5. In Reference 5, the magnetoresistive elements are arranged at all the intersections of the data line and the data line to which the magnetic field is applied by the electric current. In contrast, in this embodiment, the intersection of the write code line and the data line has a checker pattern. Since the MTJ element is located in the area, the effect of reducing disturb is even greater. Further, since the corners in the longitudinal direction of adjacent MTJ elements do not approach each other, the layout is easy.

Note that the fixed layer of the MTJ element desirably has the same direction in order to determine the direction at the time of manufacture. In the layout shown in FIG. 49, it is desirable to align the data lines in a direction perpendicular to the data lines, that is, in a write line direction. For such a pinned layer, the magnetization of the free layer is It is desirable that the direction is the write code line direction, and the angle at which the longitudinal direction of the MTJ element is inclined with respect to the write code line direction is in the range of -45 degrees to 45 degrees.

 Here, an example in which the configuration of the first embodiment is modified is shown. However, in the configurations of the second embodiment to the eighth embodiment, the longitudinal direction of the MTJ element is similarly written for each lead line. Can be used.

 The main effects obtained by the present invention are as follows.

 In a semiconductor device with an MR AM cell array composed of an MTJ element and a transistor with a transistor, the leakage magnetic field to the memory cell adjacent to the selected cell during writing is reduced to avoid the possibility of being affected by the magnetization state. Can be As a result, a highly integrated, highly reliable, high-speed MRAM cell array can be realized. Industrial applicability

 INDUSTRIAL APPLICABILITY The present invention is suitable for a semiconductor device having a memory cell array that stores information by using a change in magnetoresistance. For example, a single MR AM or a system containing MR AM can be applied to SI.

Claims

The scope of the claims

 1. The i-th writing line and

 A second write mode line adjacent to the first write mode line, a third write mode line further adjacent to the second write mode line,

 A first data line intersecting the first to third write code lines, a first memory cell disposed at an intersection of the first write code line and the first data line,

 A second memory cell disposed at an intersection of the third write code line and the first data line;

 The first memory cell includes a first magnetoresistive element connected to the first data line, and a first transistor connected to the first magnetoresistive element,

 The second memory cell includes a second magnetoresistive element connected to the first data line, and a second transistor connected to the second magnetoresistive element,

 The second magnetic resistance element is disposed closest to the first magnetic resistance element among the magnetic resistance elements connected to the first data line,

 A semiconductor device in which the second write code line passes between the first magnetoresistive element and the second magnetoresistive element.

 2. The semiconductor device according to claim].

 A second data line adjacent to the first data line;

 A third memory cell disposed at an intersection of the second write code line and the second data line;

The semiconductor device, wherein the third memory cell includes a third magnetoresistive element connected to the second data line, and a third transistor connected to the third magnetoresistive element.

3. The semiconductor device according to claim 2, further comprising a fourth write code line further adjacent to the third write word line,

 The first memory cell has a first connection hole that connects the first magnetoresistive element and the first transistor,

Γ) the second memory cell has a second connection hole connecting the second magnetoresistive element and the second transistor,

 The third memory cell has a third connection hole that connects the third magneto-resistance element and the third transistor,

 The first connection hole and the third connection hole are disposed between the first write code line and the second write code line,

 The semiconductor device, wherein the second connection hole is arranged between the third write word line and the fourth write word line.

 4. The semiconductor device according to claim 2,

 A source of the second transistor is connected to the second write code line,

 The semiconductor device, wherein a source of the third transistor is connected to the third write line.

 5. The semiconductor device according to claim].

 A second data line adjacent to the first data line;

0 a third data line further adjacent to the second data line;

 A fourth memory cell disposed at an intersection of the first write line and the third data line;

 The fourth memory cell includes a fourth magnetoresistive element connected to the third data line, and a fourth transistor 5 connected to the fourth magnetoresistive element,

The fourth magnetoresistive element is the most magnetoresistive element among the magnetoresistive elements selected at the time of writing by the first write code line. Is located close to

 A semiconductor device in which the second data line passes between the first and fourth magnetoresistive elements.

6. Multiple write word lines,

 A plurality of data lines intersecting with the plurality of write code lines, and a plurality of memory cells arranged in a checker pattern at desired intersections of the plurality of write code lines and the plurality of data lines,

 Each of the plurality of memory cells includes a magnetoresistive element connected to the data line, and a transistor having a drain connected to the magnetoresistive element.

 7. The semiconductor device according to claim 6,

 Each of the plurality of memory cells is a semiconductor device including:] magnetoresistive elements and one transistor.

 8. The semiconductor device according to claim 6,

 A semiconductor device in which an active region of the transistor is arranged such that a line connecting a source and a drain of the transistor is oblique to a direction of the plurality of data lines.

 9. The semiconductor device according to claim 6, further comprising: a plurality of read word lines arranged in the same direction as the plurality of write word lines;

 A semiconductor device, wherein a gate of the transistor is connected to the read word line.

 10. The semiconductor device according to claim 9,

 A semiconductor device in which the order of address assignment is different between the plurality of write source lines and the plurality of read source lines.

 11. The semiconductor device according to claim 9,

The number of the plurality of read code lines is half of the number of the plurality of write code lines; A semiconductor device in which the plurality of memory cells are arranged at all intersections of the read mode line and the data line.

 12. The semiconductor device according to claim 6,

 The semiconductor device, wherein the magnetoresistive element has a dimension in a direction perpendicular to the write code line smaller than a dimension in a direction perpendicular to the data.

 13. The semiconductor device according to claim 6,

 A semiconductor device in which the magnetoresistive elements are arranged alternately in a checker pattern, with the longitudinal direction being inclined with respect to the direction of the write lead line.

14. The semiconductor device according to claim 3,

 The longitudinal direction of the magnetoresistive element is different from the direction of the write lead line.

Semiconductor device at an angle between -45 and 45 degrees.

 1.5. The semiconductor device according to claim 6,

 The semiconductor device, wherein the magnetoresistive element is formed in a layer above the write code line, and the data line is formed on the magnetoresistive element.

 1.6. Multiple write word lines,

 A plurality of data line pairs intersecting the plurality of write word lines; a desired intersection of the plurality of write word lines and the plurality of data line pairs; a plurality of memory cells arranged in a checker pattern; And

 Each of the plurality of memory cells includes a magnetoresistive element connected to the data line, and a transistor having a drain connected to the magnetoresistive element.

 17. The semiconductor device according to claim 16,

 Each of the plurality of memory cells includes two magnetoresistive elements connected to the data line pair, and two transistors each having a drain connected to the two magnetoresistive elements. Semiconductor device.

18. The semiconductor device according to claim 16,

Each of the plurality of memory cells is connected to one of the data line pairs. A semiconductor device comprising: a plurality of the magneto-resistive elements; and one transistor having a drain connected to the magneto-resistive element and a source connected to the other of the data line pair.

 19. First, second, third, and fourth ground lines provided adjacent to each other around I

 A first data line intersecting the first to fourth code lines; and a second data line intersecting the first to fourth code lines and adjacent to the first data line. When,

 A first memory cell disposed at an intersection of the first and second pad lines and the first data line;

 A second memory cell disposed at an intersection of the second and second code lines and the second data line;

 A third memory cell disposed at an intersection of the third and fourth code lines and the third data line;

 A fourth memory cell disposed at an intersection of the third and fourth word lines and the second data line,

 The first memory cell includes a first magnetoresistive element connected to the first data line, to which a magnetic field is applied by a current of the first read line, and a drain connected to the first magnetoresistive element. A first transistor having a gate connected to the second wire and a gate connected to the second wire.

 The second memory cell includes a second magnetoresistive element connected to the second data line and applied with a magnetic field by a current of the second read line, and a drain connected to the second magnetoresistive element. A second transistor connected to the first: L lead wire,

The third memory cell includes a third magnetoresistive element connected to the first data line, to which a magnetic field is applied by a current of the third read line, and a drain connected to the third magnetoresistive element. Connected and the gate is connected to the fourth lead. A third transistor to be connected,

 The fourth memory cell includes a fourth magnetoresistive element connected to the second data line, to which a magnetic field is applied by a current of the fourth read line, and a drain connected to the fourth magnetoresistive element. A semiconductor device having a fourth transistor connected and a gate connected to the third lead line;

 20. The semiconductor device according to any one of claims 1 to 19, wherein the magnetoresistive element includes a magnetic layer including a ferromagnetic fixed layer, a tunnel insulating film, and a ferromagnetic free layer. A semiconductor device that is a tunnel junction element.