US20130265821A1 - Shared bit line smt mram array with shunting transistors between bit lines - Google Patents
Shared bit line smt mram array with shunting transistors between bit lines Download PDFInfo
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- US20130265821A1 US20130265821A1 US13/887,289 US201313887289A US2013265821A1 US 20130265821 A1 US20130265821 A1 US 20130265821A1 US 201313887289 A US201313887289 A US 201313887289A US 2013265821 A1 US2013265821 A1 US 2013265821A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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Abstract
Description
- The present disclosure is a divisional application that claims priority under 35 U.S.C. §120 from U.S. patent application Ser. No. 12/803,523, filing date Jun. 29, 2010, now U.S. Pat. No. ______, issued ______, assigned to a common assignee and herein incorporated by reference in its entirety.
- This disclosure relates generally to memory cells and array structures for memory cells. More particularly, this disclosure relates to magnetic random access memory (MRAM) cells and array structures for spin moment transfer (SMT) MRAM cells.
- The term spin moment transfer MRAM refers to a magnetic tunnel junction (MTJ) random access memory (RAM). In this context, the term “spin” refers to the angular momentum of electrons passing through an MTJ that will alter the magnetic moment of a free layer of an MTJ device. Electrons possess both electric charge and angular momentum (or spin). It is known in the art that a current of spin-polarized electrons can change the magnetic orientation of a free ferromagnetic layer of an MTJ via an exchange of spin angular momentum.
- “A Novel Nonvolatile Memory with Spin-torque Transfer Magnetization Switching: Spin-Ram”, Hosomi, et al., IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. December 2005, pp.: 459-462, provides a nonvolatile memory utilizing spin-torque transfer magnetization switching (STS), abbreviated Spin-RAM. The Spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM.
- A spin-torque MTJ element has two ferromagnetic layers and a spacer layer between the ferromagnetic layers. One ferromagnetic layer is a pinned magnetic layer and the other ferromagnetic layer is a free magnetic layer. The spacer layer is a tunnel barrier layer. When a spin polarized electron flows through the ferromagnetic layers, the spin direction rotates according to the directions of magnetic moment. The rotation of spin direction of the electrons in the ferromagnetic layers is the origin of a spin-torque to the magnetic moment. If the given torque is large enough, magnetization of ferromagnetic layer and thus the magnetic moment is reversed. The magnetization of the ferromagnetic layers transforms from parallel to anti-parallel alignment. This changes the MTJ element from a low resistance state to a high resistance state thus changing the logic state of the MTJ element from a first logic state (0) to a second logic state (1). A voltage source provides the programming voltage that generates the programming current that is reversed appropriately change the programming state of the MTJ element. Reading an SMT MRAM cell involves applying a voltage across the SMT MRAM cell and detecting the resistance (or current) difference.
- As illustrated in
FIG. 1 , a spin moment transfer (SMT)MRAM cell 100 consists of anMTJ element 105 and a Metal Oxide Semiconductor (MOS)gating transistor 110. TheMTJ element 105 is composed of a pinnedferromagnetic layer 102 and a freeferromagnetic layer 104, and atunnel barrier layer 103. The drain of thegating transistor 110 is connected through a nonmagnetic layer to the pinnedferromagnetic layer 102. The freeferromagnetic layer 104 is connected to abit line 115 and the source of thegating transistor 110 is connected thesource line 120. Thebit line 115 and sourceselect line 120 are connected to the bipolar write pulse/readbias generator 125. The bipolar write pulse/read bias generator 125 provides the necessary programming current to theMTJ element 105 through thebit line 115 and the source selectline 120. The direction being determined by logic state being programmed to theMTJ element 105. - The gate of the
gating transistor 110 is connected to aword line 130. Theword line 130 transfers a word line select voltage to the gate of thegating transistor 110 to activate thegating transistor 110 for reading or writing the logic state of theMTJ element 105. Asense amplifier 135 has one input terminal connected to the bit line and a second input terminal connected to a voltage reference circuit. When theword line 130 has the word line select voltage activated to turn on thegating transistor 110, the bipolar write pulse/read bias generator 125 generates a bias current that passes throughMTJ element 105. A voltage is developed across theMTJ element 105 that is sensed by thesense amplifier 135 and compared with the reference voltage generator to determine the logic state written to theMTJ element 105. This logic state is transferred to the output terminal of thesense amplifier 135 as to thedata output signal 145. - Arrays of spin moment transfer (SMT)
MRAM cell 100 are arranged in rows and columns. Each row of the spin-transfer based magneto tunnel junction memory devices may have theirsource line 120 commonly connected to a source line selection circuit or tied to a ground reference point. In other arrangements of an array ofSMT MRAM cells 100, as shown in U. S.Patent Application 200/60018057 (Huai), theSMT MRAM cells 100 are organized into an array having two bit lines. The two bit lines are structures such that the current flowing perpendicularly through theMTJ 105 is controlled by the difference of the bias voltages of the two bit lines for each spin moment transfer (SMT)MRAM cell 100. Two reading/writing column selection circuits are provided to control the voltages on the bit lines. - An object of this disclosure is to provide an array of SMT MRAM cells with paired columns of the SMT MRAM cells having shared bit lines with means for lowering the resistance of the shared bit lines.
- Another object of this disclosure is inhibiting program disturbance of a non-selected column of a pair of columns of the SMT MRAM cells.
- To accomplish at least one of these objects, an array of SMT MRAM cells is arranged in rows and columns. An array of SMT MRAM cells is arranged in rows and columns. Each of the columns of SMT MRAM cells is associated with one of its adjacent columns of SMT MRAM cells. Each column is connected to a true data bit line and each associated pair of columns of SMT MRAM cells is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. An activation terminal of each of the shunting switch device is connected to a column address decoder such that the shunting switch device is activated to connect the true data bit line associated with the non-selected column in parallel with the complement data bit line. The shared complement data bit line may be wider than the true data bit line to further lower the resistance of the shared complement data bit line. In some embodiments the shared complement data bit line may be twice the dimension of the true data bit line.
- In other embodiments, a bit line structure for connecting columns of SMT MRAM cells within an array of SMT MRAM cells has a true data bit line connected to an MTJ device of each SMT MRAM cell of each column of the SMT MRAM cells. A complement data bit line is connected to a source of a gating transistor of each SMT MRAM cell of the each column of the SMT MRAM cells. The bit line structure has a shunting switch transistor connected between the true data bit line and the complement data bit line of the associated pairs of columns of the SMT MRAM cells. The shunting switch transistors have an activation terminal that, when activated, connects the true data bit line of an unselected column of the SMT MRAM cells in parallel with the shared complement data bit line to effectively reduce program disturb effects in the unselected column of SMT MRAM cells. The shared complement data bit line may be wider than the true data bit line to further lower the resistance of the shared complement data bit line. The shared complement data bit line may be twice the dimension of the true data bit line.
- In other embodiments, a method for reducing resistance of a shared bit line and reducing program disturb effects of unselected columns of SMT MRAM cells in an array of SMT MRAM cells begins by providing an array of SMT MRAM cells where columns of the SMT MRAM cells are mutually connected to a shared complement data bit line through the source of a gating transistor of each of the. SMT MRAM cells of the pair of columns of SMT MRAM cells. The shared complement data bit line may be wider than the true data bit line to further lower the resistance of the shared complement data bit line. In some embodiments the shared complement data bit line may be twice the dimension of the true data bit line.
- Each of the SMT MRAM cells of each column of the SMT MRAM cells is connected to a true data bit line through an MTJ device within the SMT MRAM cells. A source of a gating transistor of the pair of adjacent columns of SMT MRAM cells is connected to a complement data bit line. A shunting switch transistor is connected between the true data bit line and the complement data bit line of the associated pairs of columns of the SMT MRAM cells. During a program operation, an address is decoded to select a row and columns of the array of SMT MRAM cells. An activation terminal of each of the shunting switch transistor of each unselected column of the array of SMT MRAM cells is initiated to turn on the shunting switch transistors to connect the true data bit line of the unselected column of the SMT MRAM cells in parallel with the shared complement data bit line to effectively reduce program disturb effects in the unselected column of SMT MRAM cells. The programming drive current is then activated to program the selected SMT MRAM cells of the selected rows and columns.
- Further, in other embodiments, an array of SMT MRAM cells is arranged in rows and columns. Each of the columns of SMT MRAM cells is associated with one of its adjacent columns of SMT MRAM cells. Each column is connected to a true data bit line and to a complement data bit line.
- A shunting switch device is connected between the true data bit line and the complement data bit line of the connected columns of SMT MRAM cells for selectively connecting one of the true data bit lines to the complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. The complement data bit lines are connected such that they are shared during a program operation to further reduce the resistance of the complement data bit lines. An activation terminal of each of the shunting switch devices is connected to a column address decoder such that the shunting switch device is activated to connect the true data bit line associated with the non-selected column in parallel with the complement data bit line.
- Still further, in other embodiments, an array of SMT MRAM cells is arranged in rows and columns. Each of the columns of SMT MRAM cells is associated with one of its adjacent columns of SMT MRAM cells. Each column is connected to a true data bit line and to a complement data bit line. At least one true data bit line shunting switch device is connected between the true data bit line and the complement data bit line of the connected columns of SMT MRAM cells for selectively connecting one of the true data bit lines to the complement data bit line. The complement data bit lines of the associated adjacent columns have at least one complement data bit line shunting switch device connected between the adjacent complement data bit lines such that they are shared during a program operation to further reduce the resistance of the complement data bit lines. An activation terminal of each of the shunting switch devices is connected to a column address decoder such that the shunting switch device is activated to connect the two complement data bit lines and the true data bit line associated with the non-selected column in parallel to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
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FIG. 1 is a functional diagram of a SMT MRAM memory cell and its peripheral circuitry of the related art. -
FIG. 2 is a functional diagram of a SMT MRAM memory cell and its peripheral circuitry. -
FIG. 3 is a schematic diagram of an embodiment of an array of SMT MRAM memory cells. -
FIG. 4 is block diagram of an embodiment of an SMT MRAM memory device. -
FIG. 5 is a flow diagram for a method to effectively reduce program disturb effects in the unselected column of SMT MRAM cells. -
FIG. 6 is a schematic diagram of another embodiment of an array of SMT MRAM memory cells having shunting switch transistors. -
FIG. 7 is a schematic diagram of still another embodiment of an array of SMT MRAM memory cells having shunting switch transistors. - The embodiments of SMT MRAM cell arrays have columns of SMT MRAM memory cells with pairs of bit lines, for the sake of convention, have one of the bit line referred to as a true data bit line and the other bit line referred to as the complement data bit line. In the related art, as described in Huai,
FIG. 9 , each column of cells has a pair of bit lines. Such architecture has too many bit lines and the bit line connecting to the source sides ofgating transistor 110 ofFIG. 2 is highly resistive. High bit line resistance puts constraint on how many cells that may be grouped in a basic array with decoders and drivers. In embodiments of this disclosure, adjacent pairs of columns are connected to share a bit the complement data bit lines. The complement data bit lines are effectively merged to form the complement data bit lines. Therefore, in some embodiments, the complement data bit lines are formed to be much wider and therefore less resistive. This permits a larger and more efficient array in terms of area. However, in the shared complement data bit line structure, the adjacent SMT MRAM memory cell of an SMT MRAM memory cell being programmed will be disturbed during programming. To effectively reduce program disturb effects in the unselected column of SMT MRAM cells, shunting switch transistors are added between each of the true data bit lines and the shared complement data bit lines. - Referring to
FIG. 2 , the structure of the SMT MRAM memory cell is essentially identical to that ofFIG. 1 , except the source of thegating transistor 110 of the SMTMRAM memory cell 100 is connected to the shared complement data bitline 155. In the embodiments, the complement data bitline 155 is structured to be in parallel with the true data bitline 150. The true data bitline 150 is connected to the freeferromagnetic layer 104 of theMTJ element 105. The true data bitline 150 and the complement data bitline 155 are connected to THE bipolar write pulse/readbias generator 125. The complement data bitline 155 is shared with an identical SMTMRAM memory cell 100 in an adjacent column of SMTMRAM memory cells 100. - The complement data bit
line 155 that is connected to the source of thegating transistor 110, is the first metal layer line in the physical construction of the SMTMRAM memory cell 100. The true data bitline 150 is the last, or the top most metal line in the physical cell stack. The first metal bit line of the complement data bitline 155 has to share the space with vias connecting the drain side of thegating transistor 110 to thebottom plate 102 ofMTJ element 105 thus forcing the first metal bit line of the complement data bitline 155 usually to be thinner. The first metal bit line of the complement data bitline 155 being narrower and thinner are therefore much more resistive than the top true data bitline 150. By sharing two adjacent complement data bitlines 155, the width of shared line is effectively wider by three times—two lines plus the spacing between the two adjacent complement data bitlines 155. The disadvantage of doing so is that the SMTMRAM memory cell 100 adjacent to the cell being programmed will see a disturb condition because they share the same selectedWord line 130. The shunting transistor (or transistors if we put more than one between the bit lines true and complement) will help to reduce this disturb condition. The further reduction in resistance of the two adjacent complement data bitlines 155 comes from the neighboringtrue bit line 150 is also in parallel with thecomplement bit line 155. But this requires more than one shunting transistor between the true and complement bit lines. -
FIG. 3 illustrates an embodiment of anarray 200 of the SMTMRAM memory cells 100. The SMTMRAM memory cells 100 are arranged into rows and columns to form thearray 200. The MTJ element of each SMTMRAM memory cells 100 is connected to one of the true data bitlines 250 a, 259 b, . . . 250 n. - Adjacent columns of SMT
MRAM memory cells 100 are associated with each other. A shuntingswitch transistor 205 a, . . . , 205 n and 206 a, . . . , 206 n connects each true data bitline line 255 a, . . . , 255 n. A first source/drain of each of the shuntingswitch transistor 205 a, . . . , 205 n and 206 a, . . . , 206 n is connected to the true data bitline switch transistor 205 a, . . . , 205 n and 206 a, . . . , 206 n is connected to one shared complement data bitline 255 a, . . . , 255 n. The gate of each of the shuntingswitch transistors 205 a, . . . , 205 n is connected to the in-phase column address select bit Ay 210 and the gate of each of the shuntingswitch transistor 206 a, . . . , 206 n is connected to the out-of-phase column addressselect bit Ay Ay 212 originate from a column or bit line decoder selector that decodes an address to select the columns of thearray 200 for programming, reading, and erasing. - Each of the true data bit
lines line switch transistor 215 a, 215 b, . . . , 215 n-1, 215 n. The second source/drain of each of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n is connected to a true program datavoltage distribution line 247. Each shared complement data bitline 255 a, . . . , 255 n is connected to a first source/drain of each of the complement data bit line switch transistors 220 a, . . . , 220 n. The second source/drain of each of the complement data bit line switch transistors 220 a, . . . , 220 n is connected to a complement data programvoltage distribution line 245. The gates of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n are connected to the bit line decodeselect circuit 227. The decodeselect circuit 225 receives an address, decodes the address and activates the appropriate gate of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n to activate the selected column or columns for programming, erasing, and reading the selected SMTMRAM memory cells 100. - Each of the complement data bit
lines 255 a, 255 b, . . . , 255 n-1, 255 n is connected to a first source/drain of a complement data bit line switch transistor 220 a, 220 b, . . . , 220 n-1, 220 n. The second source/drain of each of the complement data bit line switch transistors 220 a, 220 b, . . . , 220 n-1, 220 n is connected to a programvoltage distribution line 245. Each shared complement data bitline 255 a, . . . , 255 n is connected to a first source/drain of each of the complement data bit line switch transistors 220 a, . . . , 220 n. The second source/drain of each of the complement data bit line switch transistors 220 a, . . . , 220 n is connected to a programvoltage distribution line 245. The gates of the complement data bit line switch transistors 220 a, 220 b, . . . , 220 n-1, 220 n are connected to the bit line decodeselect circuit 225. As above, the decodeselect circuit 225 receives an address, decodes the address and activates the appropriate gate of the complement data bit line switch transistors 220 a, 220 b, . . . , 220 n-1, 220 n to activate the selected column or columns for programming, erasing, and reading the selected SMTMRAM memory cells 100. - During programming of selected SMT
MRAM memory cells 100, the shuntingswitch transistors 205 a, . . . , 205 n are activated to effectively place unselected true data bitline line 255 a, . . . , 255 n for each paired columns of the SMTMRAM memory cells 100. By placing the true data bitline line 255 a, . . . , 255 n, the resistance of the shared complement data bitline 255 a, . . . , 255 n is effectively decreased and prevents disturb program currents from passing through the unselectedSMT MRAM cells 100. -
FIG. 4 is block diagram of an embodiment of an SMT MRAM memory device showing a shared bit line structure with shunting switch transistors between the true data bit lines and the shared complement data bit lines. The SMT MRAM memory device has an array of SMTMRAM memory cells 100 that is formed ofmultiple sub-arrays 200 of SMTMRAM memory cells 100. The SMTMRAM memory cells 100 are formed in rows and columns with the structure as described inFIG. 2 . With each row of the SMTMRAM memory cells 100 are connected to one of the word lines 315 a, . . . , 315 m, 316 a, . . . , 316 m. Each column of the SMTMRAM memory cells 100 is connected to one of the true data bitlines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n. Adjacent columns are paired and connected to one of the shared complement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m. The true data bitlines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n are connected to their associated shared complement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m through their respectiveshunting switch transistors 205 and 206 to selectively connected the true data bitlines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n of the unselected column of SMTMRAM memory cells 100 to the associated shared complement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m as described above. - The true data bit
lines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n are connected to the bit line decode selector circuit 305 a. The shared complement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m are connected to the bit line decode selector circuit 305 b The bit line decode selector circuits 305 a and 305 b are connected to the bitline decode circuit 355 The bit line decode circuit receives theexternal address lines 365 and theexternal control lines 360 and decodes the decodedaddress 370 and transmits the decodedaddress 370 to the bit line decode selector circuits 305 a and 305 b to select the desired columns of selected sub-arrays 200 of the SMTMRAM memory cells 100. - The write/
read generator 335 receives theclock timing signal 345 and thedata input signal 350 and conditions and amplifies thedata input signal 350 to form the trueprogram data D W 375 and the complement data program 376. The trueprogram data D W 375 and the complement data programDW 376 are transferred respectively through the bit line decode selector circuits 305 a and 305 b to the appropriate true data bitlines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n and the shared complement data bit lines 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m. - During a programming operation, the shunting
switch transistors 205 and 206 of the unselected columns are activated to shunt the true data bitlines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n of the unselected columns to shared complement data bit lines 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m to prevent disturb program currents from passing through the unselectedSMT MRAM cells 100 and to further decrease the effective resistance of the complement data bit lines 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m. - During a read operation, a read current is passed from the bit line decode selector 305 a through the selected true data bit
lines 320 a, 320 b, . . . , 320 n-1, 320 n, 321 a, 321 b, . . . , 321 n-1, 321 n, and 322 a, 322 b, . . . , 322 n-1, 322 n to the MTJ of the SMTMRAM memory cells 100 to the shared complement data bit line 325 a, . . . , 325 m, 326 a, . . . , 326 m, and 327 a, . . . , 327 m to the bit line decode selector 305 b. The sense amplifiers are connected to the through the bit line decode selector 305 a to sense the voltage developed across the MTJ of the selected SMTMRAM memory cells 100 to detect the data stored in the selectedSMT MRAM 100. Thedata driver 385 receives the captured data conditions and amplifies the data to generate theoutput data 390 that is transferred to external circuitry. - Refer now to
FIG. 5 for a discussion of an embodiment of a method to reduce the resistance of a complement data bit line during a programming operation and to effectively reduce program disturb effects in unselected columns of SMT MRAM memory cells. A provided array of SMT MRAM memory cells is structured and operates as described inFIG. 3 where columns of the SMT MRAM cells are mutually connected to a shared complement data bit line through the source of a gating transistor of each of the SMT MRAM cells of the pair of columns of SMT MRAM cells. Each of the SMT MRAM cells of each column of the SMT MRAM cells is connected to a true data bit line. Each of the true data bit lines is connected to an MTJ device within the SMT MRAM cells. A source of a gating transistor of the pair of adjacent columns of SMT MRAM cells is connected to a complement data bit line. A shunting switch transistor is connected between the true data bit line and the complement data bit line of the associated pairs of columns of the SMT MRAM cells. During a program operation, an address is decoded (Box 400) to select a row (Box 405) and columns (Box 410) of the array of SMT MRAM cells. A gating terminal of each of the shunting switch transistor of each unselected column of the array of SMT MRAM cells is activated (Box 415) to turn on the shunting switch transistors to connect the true data bit line of the unselected columns of the SMT MRAM cells in parallel with the shared complement data bit line to effectively reduce program disturb effects in the unselected column of SMT MRAM cells. The programming drive current is then activated (Box 420) to program the selected SMT MRAM cells of the selected rows and columns. -
FIG. 6 illustrates an alternate embodiment of anarray 200 of the SMTMRAM memory cells 100. The SMTMRAM memory cells 100 are arranged into rows and columns to form thearray 200 as described above inFIG. 3 . The MTJ element of each SMTMRAM memory cells 100 is connected to one of the true data bitlines 250 a, 259 b, . . . , 250 n and to one of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n. - Adjacent columns of SMT
MRAM memory cells 100 are associated with each other. A shuntingswitch transistor 505 a, . . . , 505 n and 506 a, . . . , 506 n connects each true data bitline line 500 a, . . . , 500 n and 501 a, . . . , 501 n. A first source/drain of each of the shuntingswitch transistors 505 a, . . . , 505 n and 506 a, . . . , 506 n is connected to the true data bitline switch transistors 505 a, . . . , 505 n and 506 a, . . . , 506 n is connected to one associated complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n. The gate of each of the shuntingswitch transistors 505 a, . . . , 505 n is connected to the in-phase column address select bit Ay 210 and the gate of each of the shuntingswitch transistor 506 a, . . . , 506 n is connected to the out-of-phase column addressselect bit Ay Ay 212 originate from a column or bit line decoder selector that decodes an address to select the columns of thearray 200 for programming, reading, and erasing. - Each of the true data bit
lines line switch transistor 215 a, 215 b, . . . , 215 n-1, 215 n. The second source/drain of each of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n is connected to a true program datavoltage distribution line 247. Each shared complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n is connected to a first source/drain of each of the complement data bit line switch transistors 220 a, . . . , 215 n. The second source/drain of each of the complement data bit line switch transistors 220 a, . . . , 215 n is connected to a complement data programvoltage distribution line 245. The gates of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n are connected to the bit line decodeselect circuit 225. The decodeselect circuit 225 receives an address, decodes the address and activates the appropriate gate of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n to activate the selected column or columns for programming, erasing, and reading the selected SMTMRAM memory cells 100. - Each of the complement data bit
lines 500 a, . . . , 500 n is connected to a first source/drain of a complement data bitline switch transistor 520 a, . . . , 520 n and each of the complement data bitlines 501 a, . . . , 501 n is connected to the first source/drain of a complement data bitline switch transistors 521 a, . . . , 521 n. The second source/drain of each of the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n is connected to a programvoltage distribution line 245. The gates of the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n are connected to the bit line decodeselect circuit 225. As above, the decodeselect circuit 225 receives an address, decodes the address and activates the appropriate gate of the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n to activate the selected column or columns for programming, erasing, and reading the selected SMTMRAM memory cells 100. - During programming of selected SMT
MRAM memory cells 100, the shuntingswitch transistors 505 a, . . . , 505 n and 506 a, . . . , 506 n are selectively activated to effectively place unselected true data bitlines line 500 a, . . . , 500 n and 501 a, . . . , 501 n for each of the columns of the SMTMRAM memory cells 100. By placing the true data bitline line 500 a, . . . , 500 n and 501 a, . . . , 501 n, the resistance of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n is effectively decreased and prevents disturb program currents from passing through the unselectedSMT MRAM cells 100. Further during programming. the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n of the unselected columns are activated to effectively place the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n of the selected column in parallel with the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n of the associated adjacent unselected column of the SMTMRAM memory cells 100. The placing the complement data bitlines 500 a, . . . , 500 n and 501 a, . . . , 501 n of the associated adjacent selected and unselected bit lines in parallel effectively reduces the resistance.otthe complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n of the selected columns of SMTMRAM memory cells 100 and any magnetic field resulting in'a program disturb of the unselected SMTMRAM memory cells 100 is mitigated. - The bit line
decode selector circuit 225 must be structured to activate,the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n appropriately for the unselected complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n to connected selected and unselected complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n in parallel. The bit linedecode selector circuit 225 must further deactivate the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n for the unselected true data bitlines voltage distribution line 247 from being applied to the unselected true data bitlines lines 500 a, . . . , 500 n and 501 a, . . . , 501 n. -
FIG. 7 illustrates a generalized embodiment of anarray 200 of the SMTMRAM memory cells 100. The SMTMRAM memory cells 100 are arranged into rows and columns to form thearray 200 as described above inFIGS. 3 and 6 . The MTJ element of each SMTMRAM memory cells 100 is connected to one of the true data bitlines 250 a, 259 b, . . . , 250 n and to one of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n. - Adjacent columns of SMT
MRAM memory cells 100 are associated with each other. A shunting switch transistor 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n connects each true data bitline line 500 a, . . . , 500 n and 501 a, . . . , 501 n. A first source/drain of each of the shunting switch transistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n is connected to one of the true data bitlines line 500 a, . . . , 500 n and 501 a, . . . , 501 n. The gate of each of the shunting switch transistors 600 a, . . . , 600 n, and 605 a, . . . , 605 n is connected to the in-phase column address select bit Ay 620 a and 620 b and the pate of each of the shunting switch transistor 601 a, . . . , 601 n and 606 a, . . . , 606 n is connected to the out-of-phase column address select bitAy 621 a and 621 b. The in-phase column address select bit Ay 620 a and 620 b and the out-of-phase column address select bitAy 621 a and 621 b originate from a column or bit line decoder selector that decodes an address to select the columns of thearray 200 for programming, reading, and erasing. In the generalized embodiment there may be an number of the shunting switch transistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n placed in parallel between the true data bitlines lines 500 a, . . . , 500 n and 501 a, . . . , 501 n with two of the shunting switch transistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n connected between each of the true data bitline line 500 a, . . . , 500 n and 501 a, . . . , 501 n. - Each of the complement data bit
lines 500 a, . . . , 500 n and 501 a, . . . , 501 n of the associated columns of SMT MRAM's 100 has a pair of complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n. Again as described above, in the generalized embodiment, the number of complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n may be any number to assist in reducing the resistance of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n, with the two of this illustration being exemplary. A first source/drain of the complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n is connected to a first of the complement data bitlines 500 a, . . . , 500 n and 501 a, . . . , 501 n and a second source/drain of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n being connected to a second of the associated complement data bitlines 500 a, . . . , 500 n and 501 a, . . . , 501 n. The gates of the complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n are connected to a program command signal to activate the connection of the associated complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n through the complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n during a program operation and to disconnect the complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n during read and erase operations. - As shown in
FIG. 6 , each of the true data bitlines line switch transistor 215 a, 215 b, . . . , 215 n-1, 215 n. The second source/drain of each of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n is connected to a true program datavoltage distribution line 247. Each shared complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n is connected to a first source/drain of each of the complement data bit line switch transistors 220 a, . . . , 215 n. The second source/drain of each of the complement data bit line switch transistors 220 a, . . . , 215 n is connected to a complement data programvoltage distribution line 245. The gates of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n are connected to the bit line decodeselect circuit 225. The decodeselect circuit 225 receives an address, decodes the address and activates the appropriate gate of the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n to activate the selected column or columns for programming, erasing, and reading the selected SMTMRAM memory cells 100. - Further, as shown in
FIG. 6 , each of the complement data bitlines 500 a, . . . , 500 n is connected to a first source/drain of a complement data bitline switch transistor 520 a, . . . , 520 n and each of the complement data bitlines 501 a, . . . , 501 n is connected to the first source/drain of a complement data bitline switch transistors 521 a, . . . , 521 n. The second source/drain of each of the complement data bitline switch transistors 520 a, . . . , 520 n and 521 a, . . . , 521 n is connected to a programvoltage distribution line 245. The gates of the complement data bit line switch transistors 220 a, 220 b, . . . , 220 n-1, 220 n are connected to the bit line decodeselect circuit 225. As above, the decodeselect circuit 225 receives an address, decodes the address and activates the appropriate gate of the complement data bit line switch transistors 2 520 a, . . . , 520 n and 521 a, . . . , 521 n to activate the selected column or columns for programming, erasing, and reading the selected SMTMRAM memory cells 100. - During programming of selected SMT
MRAM memory cells 100, the in-phase column address select bit Ay 620 a and 620 b and the out-of-phase column address select bitAy 621 a and 621 b are selectively activated to turn on the selected shunting switch transistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n to effectively place unselected true data bitlines line 500 a, . . . , 500 n and 504 a, . . . , 501 n for each of the columns of the SMTMRAM memory cells 100. The Program command signals 625 a and 625 b are activated to turn on the selected complement bitline shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n place the complement data bitlines 500 a, . . . , 500 n and 501 a, . . . , 501 n of the associated column pairs of the SMTMRAM memory cells 100 in parallel to further reduce the resistance of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n. - By placing the true data bit
line line 500 a, . . . , 500 n and 501 a, . . . , 501 n, the resistance of the complement data bitline 500 a, . . . , 500 n and 501 a, . . . , 501 n is effectively decreased and any magnetic field resulting in a program disturb of the unselected SMTMRAM memory cells 100 is mitigated. - The bit line
decode selector circuit 225 must deactivate the true data bitline switch transistors 215 a, 215 b, . . . , 215 n-1, 215 n for the unselected true data bitlines voltage distribution line 247 from being applied to the unselected true data bitlines lines 500 a, . . . , 500 n and 501 a, . . . , 501 n. - The placing of the shunting switch transistors 600 a, . . . , 600 n, 601 a, . . . , 601 n, 605 a, . . . , 605 n and 606 a, . . . , 606 n and the complement bit
line shunting transistors 615 a, . . . , 615 n and 616 a, . . . , 616 n in the various locations through out thearray 200 of SMTMRAM memory cells 100 ofFIGS. 3 , 4, 6, and 7 as stated above decreases the resistance of the complement data bitlines 500 a, . . . , 500 n and 501 a, . . . , 501 n, therefore a larger and more efficient array in terms of area is now formed. - While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.
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US20140177319A1 (en) * | 2012-12-21 | 2014-06-26 | SK Hynix Inc. | Nonvolatile memory apparatus |
KR102098244B1 (en) | 2014-02-04 | 2020-04-07 | 삼성전자 주식회사 | Magnetic memory device |
TWI559450B (en) | 2014-04-18 | 2016-11-21 | 力晶科技股份有限公司 | Memory structrue and operation method thereof |
US9805816B2 (en) * | 2015-04-03 | 2017-10-31 | Headway Technologies, Inc. | Implementation of a one time programmable memory using a MRAM stack design |
US10008537B2 (en) | 2015-06-19 | 2018-06-26 | Qualcomm Incorporated | Complementary magnetic tunnel junction (MTJ) bit cell with shared bit line |
US9548096B1 (en) * | 2015-08-26 | 2017-01-17 | Qualcomm Incorporated | Reverse complement magnetic tunnel junction (MTJ) bit cells employing shared source lines, and related methods |
US9721662B1 (en) | 2016-01-13 | 2017-08-01 | Sandisk Technologies Llc | Non-volatile memory with efficient programming |
US11437083B2 (en) | 2021-02-05 | 2022-09-06 | International Business Machines Corporation | Two-bit magnetoresistive random-access memory device architecture |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6055178A (en) | 1998-12-18 | 2000-04-25 | Motorola, Inc. | Magnetic random access memory with a reference memory array |
DE10053965A1 (en) | 2000-10-31 | 2002-06-20 | Infineon Technologies Ag | Method for preventing unwanted programming in an MRAM arrangement |
WO2004049345A2 (en) | 2002-11-28 | 2004-06-10 | Koninklijke Philips Electronics N.V. | Magnetic memory architecture with shared current line |
US6920062B2 (en) * | 2003-10-14 | 2005-07-19 | International Business Machines Corporation | System and method for reading data stored on a magnetic shift register |
US7576956B2 (en) | 2004-07-26 | 2009-08-18 | Grandis Inc. | Magnetic tunnel junction having diffusion stop layer |
US7376006B2 (en) | 2005-05-13 | 2008-05-20 | International Business Machines Corporation | Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element |
US7646627B2 (en) | 2006-05-18 | 2010-01-12 | Renesas Technology Corp. | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
JP4935183B2 (en) | 2006-05-18 | 2012-05-23 | 株式会社日立製作所 | Semiconductor device |
JP4157571B2 (en) * | 2006-05-24 | 2008-10-01 | 株式会社東芝 | Spin injection magnetic random access memory |
US8693238B2 (en) * | 2006-08-07 | 2014-04-08 | Nec Corporation | MRAM having variable word line drive potential |
JP4987386B2 (en) | 2006-08-16 | 2012-07-25 | 株式会社東芝 | Semiconductor memory having variable resistance element |
JP5091495B2 (en) * | 2007-01-31 | 2012-12-05 | 株式会社東芝 | Magnetic random access memory |
JP5159116B2 (en) | 2007-02-07 | 2013-03-06 | 株式会社東芝 | Semiconductor memory device |
JP4864760B2 (en) * | 2007-02-15 | 2012-02-01 | 株式会社東芝 | Semiconductor memory device and data writing / reading method thereof |
WO2010038565A1 (en) * | 2008-09-30 | 2010-04-08 | 日本電気株式会社 | Magnetic random access memory and method for operating magnetic random access memory |
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US11075247B2 (en) | 2019-11-22 | 2021-07-27 | Globalfoundries U.S. Inc. | Circuit structure and method for resistive RAM with self aligned contacts in zero-via layer |
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US8570793B1 (en) | 2013-10-29 |
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US20130301347A1 (en) | 2013-11-14 |
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