WO2010038565A1

WO2010038565A1 - Magnetic random access memory and method for operating magnetic random access memory

Info

Publication number: WO2010038565A1
Application number: PCT/JP2009/064839
Authority: WO
Inventors: 昇崎村; 直彦杉林; 竜介根橋
Original assignee: 日本電気株式会社
Priority date: 2008-09-30
Filing date: 2009-08-26
Publication date: 2010-04-08
Also published as: JP5354391B2; JPWO2010038565A1

Abstract

An MRAM comprises a memory array (3), word lines (WL), bit lines (WBL, /WBL), a word line unit (5) and a bit line unit (7). The memory array (3) includes memory cells (C), each of which includes a transistor (M1) and a magnetoresistive element (11). The word lines (WL) extend in an X-direction, while the bit lines (WBL, /WBL) extend in a Y-direction. The word line unit (5) selects a word line (WL), while the bit line unit (7) selects bit lines (WBL, /WBL). The transistor (M1) has its gate connected to a word line (WL), one of its terminals connected to a bit line (WBL) and the other of its terminals connected to the magnetoresistive element (11). During a standby state, the word line unit (5) grounds the word line (WL), while the bit line unit (7) applies a first voltage to the bit lines (WBL, /WBL). During a write operation, the word line unit (5) applies a second voltage to the selected word line (WL), while the bit line unit (7) causes a potential difference to occur between the selected bit lines (WBL, /WBL).

Description

Magnetic random access memory and method of operating magnetic random access memory

The present invention relates to a magnetic random access memory using a magnetoresistive element and an operation method of the magnetic random access memory.

Magnetic random access memory (hereinafter referred to as MRAM (Magnetic Random Access Memory)) is a non-volatile memory that can be read and written unlimitedly, and can operate at low voltage and high speed. The memory cell of the MRAM includes a magnetoresistive element (example: MTJ (Magnetic Tunneling Junction) element) as an element for storing data.

The biaxial writing method has been used as a writing method for the memory cell. In the two-axis write method, a write current is supplied to each of two orthogonal wires (eg, word line and bit line), and a memory cell selected by a synthesized magnetic field generated by the current (hereinafter referred to as a selected cell). ) Of the magnetoresistive element is reversed. In the case of this biaxial writing method, the memory cell has a 1T1MTJ cell configuration. That is, the memory cell is composed of one MTJ element (1MTJ) as a magnetoresistive element and one cell transistor (1T) for selecting a memory cell during a read operation. The area of this memory cell may be able to realize a cell size comparable to DRAM (Dynamic Random Access Memory). However, in this two-axis writing method, there is a state (hereinafter referred to as a half-selected state) in which a magnetic field is applied also to non-selected memory cells (hereinafter referred to as non-selected cells). For this reason, there is a drawback that the operation margin for writing is narrow. In addition, since the write current is typically as large as about 5 mA, it is difficult to increase the cell occupation rate and increase the capacity.

Several techniques have been proposed to solve this problem. For example, Japanese Patent No. 3888463 discloses an MRAM. 1A to 1C are circuit diagrams showing a configuration of a memory cell described in Japanese Patent No. 3888463. As shown in FIG. 1A, this memory cell has a 2T1MTJ cell configuration. That is, this memory cell is composed of one MTJ element (1MTJ) as a magnetoresistive element and two cell transistors M1 and M2 (2T) for selecting a memory cell at the time of write operation and read operation. Yes. As shown in FIG. 1B, the MRAM first sets the word line WL to the high level during the write operation. Thereby, the two cell transistors M1 and M2 are turned on. At the same time, the write bit line WBL is set to the high level, and the write bit line / WBL is set to the low level. Thereby, the write current Iw is conducted between the cell transistors M1 and M2. As a result, it is possible to apply a reversal magnetic field only to the MTJ element of the selected cell. Thereby, it is possible to improve the selectivity of the memory cell during the write operation. As shown in FIG. 1C, this MRAM can conduct the read current Is only to the selected cell via the two cell transistors M1 and M2 during the read operation. Thereby, it is possible to improve the selectivity of the memory cell even during the read operation.

There is a spin injection writing method as another technique. When the spin injection writing method is applied to a memory cell having a 1T1MTJ cell configuration, writing is performed by flowing a write current directly through the cell transistor to the MTJ element of the selected cell. Therefore, this method is also an excellent method for selecting memory cells during a write operation.

A problem common to these MRAM memory cells is that the write current that can be supplied is limited by the size of the cell transistor, that is, the gate width. Therefore, when the write current is large, the size of the memory cell (cell size) depends on the size of the cell transistor. Here, in order to realize the MRAM as a semiconductor memory, it is necessary to make the cell size as small as an SRAM (Static Random Access Memory) or a DRAM. Therefore, a reduction in write current is inevitable in the MRAM. For example, in order to realize a bit cost comparable to that of an SRAM, it is necessary to reduce the write current value to 500 μA or less. In order to realize a bit cost comparable to that of a DRAM, it is necessary to reduce the write current value to 200 μA or less. Advances in magnetic thin film technology for reducing the magnetization reversal current of MTJ elements to the level of these write current values are eagerly desired.

Japanese Patent No. 3888463

As an approach for reducing the cell size of an MRAM memory cell, the inventor examined the following technique separately from the method of reducing the write current. The technique is a technique of applying a voltage higher than the power supply voltage to the word line in the MRAM (hereinafter referred to as a word boost technique). According to the inventor's study, this technique can substantially increase the on-current of the cell transistor and drive a larger write current to the memory cell.

2A to 2C are circuit diagrams showing an example in which word boost technology is applied to a memory cell having a 2T1MTJ cell configuration. As shown in FIG. 2A, in the standby state, all word lines WL and write bit lines WBL, / WBL are grounded (Gnd). As shown in FIG. 2B, in the write operation, a voltage Vdh (> Vdd) higher than the power supply voltage Vdd is applied to the word line WL. At the same time, the power supply voltage Vdd is applied to one write bit line WBL, and the other write bit line / WBL is grounded (Gnd). Thereby, the write current Iw is supplied. Further, as shown in FIG. 2C, in the read operation, a voltage Vdh (> Vdd) is applied to the word line WL. At the same time, both write bit lines WBL and / WBL are grounded (Gnd), and the read bit line RBL is clamped to a voltage Vc (eg, about 0.3 V) lower than the power supply voltage Vdd. Thereby, the tunnel current Is penetrating the MTJ element of the selected cell is detected.

According to the inventor's investigation, this word boost technology can substantially increase the on-current of the cell transistor. Thereby, the gate width of the cell transistor can be reduced with respect to the design parameter called the current value of the write current. FIG. 3 is a graph showing the effect of this word boost technique. The vertical axis represents the area (cell size) of the memory cell, and the horizontal axis represents the current value of the write current. As shown in the figure, this word boost technique makes it possible to reduce the gate width of the cell transistor, that is, to reduce the cell size of the cell transistor, for the same write current value. That is, it is possible to reduce the cell size of an MRAM cell of a type in which a write current is conducted to the memory cell via the cell transistor.

However, when this word boost technique is used, the inventors have made it clear that there are the following problems in the write operation and the read operation. 2A to 2C, the write bit lines WBL, / WBL of the non-selected cells on the selected word line (hereinafter, selected word line) WL are grounded (Gnd). is there. However, the gate-source voltage of Vdh is applied to all the cell transistors M1, M2 (including the cell transistors M1, M2 of the non-selected cells) on the selected word line WL. Therefore, an excessive electric field is applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cells. This may impair the reliability of the cell transistors M1 and M2, and may be a factor that limits the number of times of writing and reading.

In view of the above problems, an object of the present invention is to provide a magnetic random access memory and a method for operating the magnetic random access memory that can reduce the bit cost more efficiently while maintaining the number of times of writing and reading. It is to provide.

The magnetic random access memory of the present invention includes a memory array, a plurality of word lines, a plurality of first bit lines and a plurality of second bit lines, a word line driving circuit, and a bit line driving circuit. In the memory array, a plurality of memory cells are arranged in a matrix. The plurality of word lines extend in the first direction. The plurality of first bit lines and the plurality of second bit lines extend in a second direction different from the first direction. The word line driving circuit selects a selected word line from a plurality of word lines. The bit line driving circuit selects a selected first bit line and a selected second bit line from the plurality of first bit lines and the plurality of second bit lines. Each of the plurality of memory cells includes a first selection transistor and a magnetoresistive element. The first selection transistor has a gate connected to a corresponding one of the plurality of word lines, and one source / drain connected to a corresponding one of the plurality of first bit lines. The magnetoresistive element has one end connected to the other source / drain of the first selection transistor. In the standby state, the word line driving circuit grounds the plurality of word lines. The bit line driving circuit applies a first voltage to the plurality of first bit lines and the plurality of second bit lines. In the write operation, the word line driving circuit applies a second voltage higher than the first voltage to the selected word line. The bit line driving circuit controls the voltages of the selected first bit line and the selected second bit line so that a potential difference is generated between the selected first bit line and the selected second bit line.

The operating method of the magnetic random access memory according to the present invention relates to a magnetic random access memory having the following configuration. That is, the magnetic random access memory includes a memory array in which a plurality of memory cells are arranged in a matrix, a plurality of word lines extending in a first direction, and a second direction different from the first direction. A plurality of first bit lines and a plurality of second bit lines are provided. Each of the plurality of memory cells includes a first selection transistor having a gate connected to a corresponding one of the plurality of word lines and one source / drain connected to a corresponding one of the plurality of first bit lines; And a magnetoresistive element having one end connected to the other source / drain of the first select transistor. The operating method of the magnetic random access memory includes a step of grounding the plurality of word lines and a step of applying a first voltage to the plurality of first bit lines and the plurality of second bit lines in the standby state. . In the write operation, a step of applying a second voltage higher than the first voltage to a selected word line selected from the plurality of word lines, a selected first bit line selected from the plurality of first bit lines, and a plurality Applying a first voltage to a plurality of first bit lines and a plurality of second bit lines excluding a selected second bit line selected from the second bit lines, a selected first bit line and a selected second bit line And controlling the voltage of the selected first bit line and the selected second bit line so that a potential difference is generated between the first bit line and the selected second bit line.

According to the present invention, it is possible to more efficiently reduce the bit cost while maintaining the number of times of writing and reading.

FIG. 1A is a circuit diagram showing a configuration of a memory cell described in Japanese Patent No. 3888463. FIG. 1B is a circuit diagram showing a configuration of a memory cell described in Japanese Patent No. 3888463. FIG. 1C is a circuit diagram showing a configuration of a memory cell described in Japanese Patent No. 3888463. FIG. 2A is a circuit diagram showing an example in which the word boost technique is applied to a memory cell having a 2T1MTJ cell configuration. FIG. 2B is a circuit diagram showing an example in which the word boost technique is applied to a memory cell having a 2T1MTJ cell configuration. FIG. 2C is a circuit diagram showing an example in which word boost technology is applied to a memory cell having a 2T1MTJ cell configuration. FIG. 3 is a graph showing the effect of the word boost technique. FIG. 4A is a block diagram showing the configuration of the magnetic random access memory according to the first embodiment of the present invention. FIG. 4B is a block diagram showing the configuration of the magnetic random access memory according to the first embodiment of the present invention. FIG. 4C is a block diagram showing a configuration of the magnetic random access memory according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing an example of the configuration of the word line driving circuit according to the first embodiment of the present invention. FIG. 6 is a timing chart showing input signals and output signals of the word line driving circuit according to the first embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the configuration of the bit line driving circuit according to the first embodiment of the present invention. FIG. 8 is a timing chart showing input signals and output signals of the bit line driving circuit according to the first embodiment of the present invention. FIG. 9 is a timing chart showing input signals and output signals of the bit line driving circuit according to the first embodiment of the present invention. FIG. 10 is a circuit diagram showing another example of the configuration of the bit line driving circuit according to the first embodiment of the present invention. FIG. 11A is a block diagram showing a configuration of a magnetic random access memory according to the second embodiment of the present invention. FIG. 11B is a block diagram showing the configuration of the magnetic random access memory according to the second embodiment of the present invention. FIG. 11C is a block diagram showing the configuration of the magnetic random access memory according to the second embodiment of the present invention. FIG. 12 is a circuit diagram showing an example of the configuration of the bit line driving circuit according to the second embodiment of the present invention.

Hereinafter, a magnetic random access memory and an operation method of the magnetic random access memory according to the embodiment of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
A configuration of the magnetic random access memory according to the first embodiment of the present invention will be described. 4A to 4C are block diagrams showing the configuration of the magnetic random access memory according to the first embodiment of the present invention. The magnetic random access memory 1 includes a memory array 3, a plurality of word lines WL, a plurality of write bit lines WBL and a plurality of write bit lines / WBL, a plurality of read bit lines RBL, a word line drive circuit 5, And a bit line driving circuit 7.

The memory array 3 includes a plurality of memory cells C (C00, C01,..., C10, C11,...) Arranged in a matrix. However, in this drawing, for convenience of explanation, only the memo cells C in 2 rows and 2 columns are shown. The plurality of word lines WL (WL0, WL1,...) Extend in parallel to each other in the X direction (first direction). Moreover, it arrange | positions along with the Y direction (2nd direction). The plurality of write bit lines WBL (WBL0, WBL1,...) And the plurality of write bit lines / WBL (/ WBL0, / WBL1,...) Extend in parallel to each other in the Y direction. Moreover, it arrange | positions along with the X direction. Adjacent write bit line WBL (example: WBL0) and write bit line / WBL (example: / WBL0) form a pair. The plurality of read bit lines RBL (RBL0, RBL1,...) Extend in parallel to each other in the Y direction. Moreover, it arrange | positions along with the X direction.

The word line driving circuit 5 selects a selected word line WL from a plurality of word lines WL. For example, the selected word line WL is set to a predetermined voltage level. The word line driving circuit 5 has at least functions of a row decoder and a word driver. The bit line driving circuit 7 selects the selected write bit line WBL and the selected write bit line / WBL from the plurality of write bit lines WBL and the plurality of write bit lines / WBL. For example, each of the selected write bit line WBL and the selected write bit line / WBL is set to a predetermined voltage level. Further, the selected read bit line RBL is selected from the plurality of read bit lines RBL. For example, the selected read bit line is set to a predetermined voltage level. The bit line driving circuit 7 has at least functions as a column decoder and a write / read driver.

The memory cell C includes a first selection transistor M1, a second selection transistor M2, and a magnetoresistive element 11. That is, the memory cell C has a 2T1MTJ cell configuration. The first selection transistor M1 has a gate connected to a corresponding one of the plurality of word lines WL, and one source / drain connected to a corresponding one of the plurality of write bit lines WBL. The second select transistor M2 has a gate corresponding to one of the plurality of word lines WL, one source / drain corresponding to one of the plurality of write bit lines / WBL, and the other source / drain connected to the second one. The other source / drain of one select transistor M1 is connected to each other. The magnetoresistive element 11 is exemplified as an MTJ element, and one end is connected to the other source / drain of the first selection transistor M1, and the other end is connected to a corresponding one of the plurality of read bit lines RBL.

Next, an operation method of the magnetic random access memory according to the first embodiment of the present invention will be described.
FIG. 4A shows a standby state of the magnetic random access memory. In the standby state shown in FIG. 4A, the word line driving circuit 5 grounds the word line WL (Gnd). The bit line drive circuit 7 precharges both the write bit lines WBL and / WBL and the read bit line RBL to the power supply voltage Vdd.

FIG. 4B shows the write operation of this magnetic random access memory. In FIG. 4B, as an example, the word line driving circuit 5 selects the word line WL0 as the selected word line WL, and the bit line driving circuit 7 writes the write bit as the selected write bit lines WBL, / WBL and the selected read bit line RBL, respectively. Lines WBL0 and / WBL0 and read bit line RBL0 are selected. Thereby, the memory cell C00 located at the intersection of the selected word line WL, the selected write bit lines WBL, / WBL and the selected read bit line RBL is selected (selected cell = memory cell C00). At this time, the memory cell C01 is a non-selected cell at the intersection of the selected row and the non-selected column, the memory cell C10 is a non-selected cell at the intersection of the non-selected row and the selected column, and the memory cell C11 is non-selected. Each of the non-selected cells at the intersection with the selected column is shown.

First, attention is focused on the selected cell C00 during the write operation. The word line driving circuit 5 applies a boost voltage Vdh (> Vdd) higher than the power supply voltage Vdd to the selected word line WL0. At the same time, the bit line drive circuit 7 controls the voltages of the selected write bit line WBL0 and the selected write bit line / WBL so that a potential difference is generated between the selected write bit line WBL0 and the selected write bit line / WBL0. For example, the power supply voltage Vdd is applied to one of the selected write bit line WBL0 and the selected write bit line / WBL0, and the other is grounded (Gnd). Which of the selected write bit line WBL0 and the selected write bit line / WBL0 is grounded is determined according to the write data. For example, when the write data is “1”, the selected write bit line / WBL0 is grounded. On the other hand, when the write data is “0”, the selected write bit line WBL0 is grounded. Since the voltage Vdh equal to or higher than the threshold voltage Vth is applied to the gate-source voltage of the cell transistors M1 and M2 of the selected cell C00, the cell transistors M1 and M2 are turned on. Accordingly, the write current Iw conducts the selected cell C00 from the selected write bit line WBL0 (or selected write bit line / WBL0) and flows to the selected write bit line / WBL0 (or selected write bit line WBL0). At this time, it is desirable that the read bit line RBL0 be in a high impedance state (HiZ) so that the write current Iw does not leak through the magnetoresistive element 11. In this write operation, a boost voltage Vdh higher than the power supply voltage Vdd is applied to the cell transistors M1 and M2, thereby substantially increasing the on-currents of the cell transistors M1 and M2 and driving a larger write current Iw to the selected cell C00. It becomes possible to do.

Next, attention is paid to the non-selected cell C01 during the write operation. The bit line drive circuit 7 places the write bit lines WBL1 and / WBL in the non-selected columns in a state where the power supply voltage Vdd is applied. Here, when the boost voltage Vdh> (power supply voltage Vdd + threshold voltage Vth), the cell transistors M1 and M2 of the non-selected cell C01 are on. However, the potential difference between the write bit line WBL1 and the write bit line / WBL1 is zero. Therefore, the write current Iw does not conduct the non-selected cell C01. In addition, a voltage (boost voltage Vdh−power supply voltage Vdd) is applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cell C01. That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cell C01. Thereby, the reliability of the cell transistors M1 and M2 can be maintained. At this time, it is desirable that the read bit line RBL1 be in a high impedance state in order to prevent a leakage current through the magnetoresistive element 11. It is more desirable to design the boost voltage Vdh <(power supply voltage Vdd + threshold voltage Vth). This is because the cell transistors M1 and M2 of the non-selected cell C01 can be turned off.

Furthermore, attention is paid to the non-selected cells C10 and C11 during the write operation. The word line driving circuit 5 brings the word line WL1 of the non-selected row to a grounded (Gnd) state. Accordingly, the cell transistors M1 and M2 of the non-selected cells C10 and C11 are in an off state. Therefore, the write current Iw is not conducted to the non-selected cells C10 and C11. Further, the gate oxide films of the cell transistors M1 and M2 of the non-selected cells C10 and C11 are grounded (Gnd). That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cells C10 and C11. Thereby, the reliability of the cell transistors M1 and M2 can be maintained.

FIG. 4C shows the read operation of this magnetic random access memory. 4C, as an example, as in FIG. 4B, the word line drive circuit 5 selects the word line WL0, the bit line drive circuit 7 selects the write bit lines WBL0, / WBL0, and the read bit line RBL0. Yes. As a result, the selected cell C00 is selected.

First, focus on the selected cell C00 during the read operation. Similarly to the write operation, the word line drive circuit 5 applies the boost voltage Vdh (> Vdd) to the selected word line WL0. At the same time, the bit line drive circuit 7 controls at least the voltage of the selected write bit line WBL so that a potential difference is generated between one end and the other end of the magnetoresistive element 11. For example, the clamp voltage Vc is applied to the selected read bit line RBL0, and both the selected write bit lines WBL0 and / WBL0 are grounded (Gnd). The clamp voltage Vc is applied by a read circuit (not shown) in (or outside) the bit line drive circuit 7. At this time, the cell transistors M1 and M2 of the selected cell C00 are turned on, and the read current (sense current) Is flows through the selected cell C00 with the clamp voltage Vc applied to the magnetoresistive element 11. That is, the read current Is is supplied from the magnetoresistive element 11 to the read circuit (not shown) through the cell transistors M1 and M2 and the selected write bit lines WBL0 and / WBL0. The read circuit detects the read current Is from the selected cell C00, for example, as in the case of a general MRAM, and compares the magnitude of the read current with the reference current Iref flowing through the selected reference cell in the same manner. decide. The MR ratio of the magnetoresistive element 11 (the ratio between the resistance value in the “0” state and the resistance value in the “1” state) has a characteristic that depends on the voltage across the magnetoresistive element 11, and typically When the voltage between both ends is 0.3V to 0.5V, the sense signal becomes the maximum value. Accordingly, the Vc is preferably designed to be in the range of 0.3V to 0.5V.

Next, attention is paid to the non-selected cell C01 during the read operation. The bit line driving circuit 7 sets the read bit line RBL1 of the non-selected column to a high impedance state, and puts both the write bit lines WBL1 and / WBL1 into a state where the power supply voltage Vdd is applied. Here, when the boost voltage Vdh> (power supply voltage Vdd + threshold voltage Vth), the cell transistors M1 and M2 of the non-selected cell C01 are on. However, the read bit line RBL1 and the read circuit (not shown) are electrically disconnected. Therefore, the read current Is does not flow through the non-selected cell C01. At this time, a voltage (boost voltage Vdh−power supply voltage Vdd) is applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cell C01. That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cell C01. Thereby, the reliability of the cell transistors M1 and M2 can be maintained. Further, when boost voltage Vdh <(power supply voltage Vdd + threshold voltage Vth), the gate-source voltages of the cell transistors M1 and M2 of the non-selected cell C01 are not more than Vth, so that they are in the off state. Accordingly, since the read current Is does not flow through the non-selected cell C01, the power supply voltage Vdd may be applied to the read bit line RBL1.

Furthermore, attention is paid to the non-selected cells C10 and C11 during the read operation. The word line driving circuit 5 brings the word line WL1 of the non-selected row to the ground (Gnd) state. Accordingly, the cell transistors M1 and M2 of the non-selected cells C10 and C11 are in an off state. Accordingly, the read current Is does not flow through the non-selected cells C10 and C11. Further, the gate oxide films of the cell transistors M1 and M2 of the non-selected cells C10 and C11 are grounded (Gnd). That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide films of the cell transistors M1 and M2 of the non-selected cells C10 and C11. Thereby, the reliability of the cell transistors M1 and M2 can be maintained.

Next, an example of the word line driving circuit 5 that realizes the above operation will be described. FIG. 5 is a circuit diagram showing an example of the configuration of the word line driving circuit in FIGS. 4A to 4C. The word line driving circuit 5 includes a row decoder 22 that selects a word line WLj (j = 0, 1,...), A word driver 21j (j = 0, 1,...) That supplies a boost voltage Vdh to the word line WLj. Have The row decoder 22 includes transistors M11 to M13 and M14j (j = 0, 1,...). The transistors M11 to M13 and M14j are core transistors whose power supply voltage is Vdd. The transistor M14j is provided corresponding to the word line WLj. The word driver 21j is provided corresponding to the word line WLj and includes transistors M15 to M18. The transistors M15 to M18 are transistors whose power supply voltage is Vdh and whose gate oxide film is thicker than the core transistor.

Subsequently, the operation of the word line driving circuit 5 will be described with reference to FIGS. However, FIG. 6 is a timing chart showing input signals and output signals of the word line driving circuit of FIG. Here, the signal RP is a low precharge signal, and its amplitude is the voltage Vdh. Signals X01ej, X234, X567, and X89 are signals obtained by predecoding the input row address, and their amplitude is the voltage Vdd. Here, the X01ej signal is an AND logic of a signal obtained by decoding a low-order two-bit row address and an access enable signal. Signal WLj indicates a voltage applied to word line WLj, and its amplitude is voltage Vdh.

In the standby state, the signal X01ej is at a low level (0 V), and the signal RP is also at a low level. Therefore, the transistor M14j is off and the transistor M18 is on. As a result, the terminal WLB is precharged to the voltage Vdh, so that a low level (0 V) is output to the word line WLj. The transistor M17 is provided to hold the terminal WLB at a high level (voltage Vdh), and its W / L (W: gate width, L gate length) is much smaller than other transistors.

When a write command and a read command are input, the signal RP becomes high level (voltage Vdh), and M18 is turned off. Subsequently, while the signals X234, X567, and X89 are at a high level (voltage Vdd), the signal X01ej is at a high level (voltage Vdd). Then, all of the transistors M11 to M14 are turned on, and the terminal WLB transitions to a low level. Accordingly, the transistor M17 is turned off, and the word line WLj is set to the high level (voltage Vdh). That is, the voltage Vdh is applied to the word line WLj. After that, when the writing operation and the reading operation are finished, the signal X01e becomes low level and the signal RP becomes low level. Then, the transistor M14 is turned off and the transistor M18 is turned on. As a result, the terminal WLB changes to the high level (voltage Vdh), and the word line WLj becomes the low level.

Next, an example of the bit line driving circuit 7 that realizes the above operation will be described. FIG. 7 is a circuit diagram showing an example of the configuration of the bit line driving circuit in FIGS. 4A to 4C. The bit line driving circuit 7 includes a column decoder 24k (k = 0, 1,...) That selects the write bit lines WBLk (k = 0, 1,...), / WBLk, and the read bit lines RBLk (k = 0, 1,. And a selector 25k (k = 0, 1,...) And a write driver 26k (k = 0, 1,...) For supplying a predetermined voltage to the write bit lines WBLk, / WBLk. The column decoder 24k is provided corresponding to the write bit lines WBLk, / WBLk and the read bit line RBLk. It has two AND circuits. The selector 25k is provided corresponding to the write bit lines WBLk, / WBLk and the read bit line RBLk. Transistors M20 and M21 are provided. The write driver 26k is provided corresponding to the write bit lines WBLk, / WBLk and the read bit line RBLk. It has two AND circuits and two NOR circuits.

Subsequently, the operation of the bit line driving circuit 7 will be described with reference to FIGS. 8 and FIG. 9 are timing charts showing input signals and output signals of the bit line driving circuit of FIG. Here, the signal Yi is a signal obtained by decoding the input column address. Signal WE is a write enable signal. The signal RE is a read enable signal. The signal CP is a column precharge signal. The signal Din is a data input signal. The signal SAIN is an input terminal of the readout circuit and is clamped at Vc.

In the standby state, both the signal WE and the signal RE are at a low level (0 V). Accordingly, the terminals YR and YW are at a low level. As a result, the voltages of the write bit lines WBLk and / WBLk both become high level (voltage Vdd). Further, the signal CP is at a low level. Accordingly, the transistor M20 is turned off and the transistor M21 is turned on. As a result, the voltage of the read bit line RBLk also becomes high level (voltage Vdd).

FIG. 8 shows a timing chart during the write operation. When a write command is input, the signal WE and the signal CP become high level (voltage Vdd). When the signal Yi is at high level and one column is selected, the terminal YW is at high level and the terminal YR is at low level. Accordingly, the transistor M21 is turned off and the transistor M20 is also kept off, so that the read bit line RBL is in a high impedance state (HiZ). When the write data is “1”, since the signal Din is at a high level, the write bit line WBL is at a high level (voltage Vdd), and the write bit line / WBL is at a low level (0 V). When the write data is “0”, since the signal Din is at the low level, the write bit line WBL is at the low level and the write bit line / WBL is at the high level. That is, a complementary voltage is applied to the write bit line WBL and the write bit line / WBL according to the write data, and the write current Iw can be supplied in different directions. When the write operation is completed, both the signal WE and the signal CP become low level, and the standby state, that is, the write bit lines WBL and / WBL and the read bit line RBL all become high level. On the other hand, when Yi is at a low level (non-selected state), both the terminals YW and YR are at a low level, so that both the write bit lines WBL and / WBL are at a high level and the read bit line RBL is in a high impedance state.

FIG. 9 shows a timing chart during the read operation. When a read command is input, the signal RE and the signal CP become high level (voltage Vdd). When the signal Yi is at high level and one column is selected, the terminal YW is at low level and the terminal YR is at high level. Accordingly, the transistor M21 is turned off and the transistor M20 is turned on, so that the read bit line RBL is clamped to Vc. At the same time, both the write bit lines WBL and / WBL become low level (0 V). Therefore, the read current Is flows through the magnetoresistive element 11 of the selected cell and is detected by the read circuit. On the other hand, when the signal Yi is at the low level (non-selected state), both the terminals YW and YR are at the low level, so that both the write bit lines WBL and / WBL are in the high level and the read bit line RBL is in the high impedance state.

In this embodiment, the write bit lines WBL and / WBL of the non-selected column may be set to the high impedance state (HiZ) after high precharging to the voltage Vdd during the write operation and the read operation. FIG. 10 is a circuit diagram showing another example of the configuration of the bit line driving circuit that realizes such an operation. The bit line drive circuit 7 is different from FIG. 7 only in the write driver 26k. The write driver 26k includes clocked inverters INV1, INV1b, an inverter, and transistors M22, M23, M22b, M23b.

In the standby state, the signal WE, the signal RE, and the signal CP are both at a low level. Accordingly, both the terminals YW and YR are at a low level. At this time, the clocked inverters INV1 and INV1b are in a high impedance state because the terminal YW is at a low level. The transistors M23 and M23b are on, and M22 and M22b are off. Accordingly, the write bit lines WBL and / WBL are precharged to a high level (voltage Vdd). The transistor M20 is off and the transistor M21 is on. Accordingly, the read bit line RBL is also precharged to a high level (voltage Vdd).

The operation when the write command is input and the signal WE becomes high level will be described. In the selected column, the signal Yi is at a high level, and thus the terminal YW is at a high level. At this time, the clocked inverters INV1 and INV1b output a high level (voltage Vdd) to one of the write bit lines WBL and / WBL and a low level (0 V) to the other in accordance with the write data Din. Since the signal Yi is at a low level in the non-selected column, the terminal YW is at a low level. Therefore, the clocked inverters INV1 and INV1b are in a high impedance state. Since the terminal YR is at a low level, the transistors M20, M22, and M22b are turned off. On the other hand, since the signal CP is at a high level, the transistors M21, M23, and M23b are also turned off. That is, the write bit lines WBL and / WBL in the non-selected column are in a high impedance state while maintaining the voltage Vdd. In addition, the read bit line RBL in the write operation is in a high impedance state regardless of selection / non-selection.

Next, the operation when a read command is input and the signal RE becomes high level will be described. In the selected column, the signal Yi is at a high level, and thus the terminal YR is at a high level. At this time, the transistor M20 is turned on, and the transistors M22 and M22b are also turned on. Further, since the signal CP is at a high level, the transistor M21 is in an off state, and the transistors M23 and M23b are also in an off state. Further, since the terminal YW is at a low level, the clocked inverters INV1 and INV1b output high impedance. That is, the read bit line RBL is connected to the read circuit and clamped at the clamp voltage Vc, and the write bit lines WBL and / WBL are at the low level. In the non-selected column, the signal Yi is at a low level, and the terminal YR is also at a low level. Accordingly, the transistor M20 is turned off, and the read bit line RBL is disconnected from the read circuit and is in a high impedance state. The transistors M22 and M22b are also turned off, and the write bit lines WBL and / WBL are in a high impedance state while maintaining the voltage Vdd.

According to the first embodiment described above, the cell area can be reduced by the word boost effect while ensuring the reliability of the gate oxide films of the cell transistors M1 and M2. That is, by maintaining the bit line potential of the unselected column at Vdd, the number of memory cells in the state where an excessive voltage is applied to the gate oxide film can be reduced to only the selected memory cell. As a result, the number of reads and writes in the magnetic random access memory can be improved.

This embodiment can be appropriately changed within the scope of the technical idea of the present invention. For example, in a read operation, the bit line drive circuit 7 applies an intermediate value Vm between the ground voltage Gnd and the power supply voltage Vdd to the write bit lines WBL, / WBL of the selected column and applies (Vm + Vc) to the read bit line RBL. It is also possible to apply.

(Second Embodiment)
The configuration of the magnetic random access memory according to the second embodiment of the present invention will be described. 11A to 11C are block diagrams showing the configuration of the magnetic random access memory according to the second embodiment of the present invention. This embodiment is different from the first embodiment in that the memory cell C uses a spin injection writing method. Accordingly, the configuration of the memory cell C, the configuration of the bit line driving circuit 7, and the configuration of the bit line are different from those of the first embodiment. The magnetic random access memory 1 includes a memory array 3, a plurality of word lines WL, a plurality of bit lines BL and a plurality of bit lines / BL, a word line driving circuit 5, and a bit line driving circuit 7. Yes.

The memory array 3 includes a plurality of memory cells C (C00, C01,..., C10, C11,...) Arranged in a matrix. However, in this drawing, for convenience of explanation, only the memo cells C in 2 rows and 2 columns are shown. The plurality of word lines WL (WL0, WL1,...) Extend in parallel to each other in the X direction. Moreover, it arrange | positions along with the Y direction. The plurality of bit lines BL (BL0, BL1,...) And the plurality of bit lines / BL (/ BL0, / BL1,...) Extend in parallel to each other in the Y direction. Moreover, it arrange | positions along with the X direction. Adjacent bit line BL (example: BL0) and bit line / BL (example: / BL0) form a pair.

The word line driving circuit 5 selects a selected word line WL from a plurality of word lines WL. For example, the selected word line WL is set to a predetermined voltage level. The word line driving circuit 5 has at least functions of a row decoder and a word driver. The bit line driving circuit 7 selects the selected bit line BL and the selected bit line / BL from the plurality of bit lines BL and the plurality of bit lines / BL. For example, each of the selected bit line BL and the selected bit line / BL is set to a predetermined voltage level. The bit line driving circuit 7 has at least functions as a column decoder and a write / read driver.

The memory cell C includes a first selection transistor M1 and a magnetoresistive element 11. That is, the memory cell C has a 1T1MTJ cell configuration. The first selection transistor M1 has a gate connected to a corresponding one of the plurality of word lines WL, and one source / drain connected to a corresponding one of the plurality of bit lines BL. The magnetoresistive element 11 is exemplified as an MTJ element, and one end is connected to the other source / drain of the first selection transistor M1, and the other end is connected to a corresponding one of the plurality of bit lines / BL.

Next, an operation method of the magnetic random access memory according to the second embodiment of the present invention will be described.
FIG. 11A shows a standby state of the magnetic random access memory. In the standby state shown in FIG. 11A, the word line driving circuit 5 grounds the word line WL (Gnd). The bit line drive circuit 7 precharges both the bit lines BL and / BL to the power supply voltage Vdd.

FIG. 11B and FIG. 11C show the write operation and read operation of this magnetic random access memory, respectively. 11B and 11C, as an example, the word line driving circuit 5 selects the word line WL0 as the selected word line WL, and the bit line driving circuit 7 selects the bit lines BL0, / BL as the selected bit lines BL and / BL, respectively. BL0 is selected. Thereby, the memory cell C00 located at the intersection of the selected word line WL and the selected bit line BL, / BL is selected (selected cell = memory cell C00). At this time, the memory cell C01 is a non-selected cell at the intersection of the selected row and the non-selected column, the memory cell C10 is a non-selected cell at the intersection of the non-selected row and the selected column, and the memory cell C11 is non-selected. Each of the non-selected cells at the intersection of the selected column is shown.

First, attention is focused on the selected cell C00 during the write operation. As shown in FIG. 11B, the word line drive circuit 5 applies a boost voltage Vdh (> Vdd) higher than the power supply voltage Vdd to the selected word line WL0. At the same time, the bit line driving circuit 7 controls the voltages of the selected bit line BL0 and the selected bit line / BL so that a potential difference is generated between the selected bit line BL0 and the selected bit line / BL0. For example, the power supply voltage Vdd is applied to one of the selected bit line BL0 and the selected bit line / BL0, and the other is grounded (Gnd). Which of the selected bit line BL0 and the selected bit line / BL0 is grounded is determined according to the write data. For example, when the write data is “1”, the selected bit line / BL0 is grounded. On the other hand, when the write data is “0”, the selected bit line BL0 is grounded. Since the voltage Vdh equal to or higher than the threshold voltage Vth is applied to the gate-source voltage of the cell transistor M1 of the selected cell C00, the cell transistor M1 is turned on. Accordingly, the write current Iw flows from the selected bit line BL0 (or selected bit line / BL0) to the selected bit line / BL0 (or selected bit line BL0) through the selected cell C00. In this write operation, by applying a boost voltage Vdh higher than the power supply voltage Vdd to the cell transistor M1, it is possible to substantially increase the on-current of the cell transistor M1 and drive a larger write current Iw to the selected cell C00. It becomes.

Next, attention is paid to the non-selected cell C01 during the write operation. The bit line driving circuit 7 brings both the bit lines BL1 and / BL of the non-selected columns into a high impedance state or a state in which the power supply voltage Vdd is applied. Here, when the boost voltage Vdh> (power supply voltage Vdd + threshold voltage Vth), the cell transistor M1 of the non-selected cell C01 is in the ON state. However, the potential difference between the bit line BL1 and the bit line / BL1 is zero. Therefore, the write current Iw does not conduct the non-selected cell C01. Further, (boost voltage Vdh−power supply voltage Vdd) is applied to the gate oxide film of the cell transistor M1 of the non-selected cell C01. That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide film of the cell transistor M1 of the non-selected cell C01. Thereby, the reliability of the cell transistor M1 can be maintained. It is more desirable to design the boost voltage Vdh <(power supply voltage Vdd + threshold voltage Vth). This is because the cell transistor M1 of the non-selected cell C01 can be turned off.

Furthermore, attention is paid to the non-selected cells C10 and C11 during the write operation. The word line driving circuit 5 brings the word line WL1 of the non-selected row to a grounded (Gnd) state. Accordingly, the cell transistors M1 of the non-selected cells C10 and C11 are in the off state. Therefore, the write current Iw is not conducted to the non-selected cells C10 and C11. Further, the gate oxide films of the cell transistors M1 of the non-selected cells C10 and C11 are grounded (Gnd). That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide films of the cell transistors M2 of the non-selected cells C10 and C11. Thereby, the reliability of the cell transistor M1 can be maintained.

Next, attention is focused on the selected cell C00 during the read operation. As shown in FIG. 11C, as in the write operation, the word line drive circuit 5 applies the boost voltage Vdh (> Vdd) to the selected word line WL0. At the same time, the bit line driving circuit 7 controls at least the voltage of the selected bit line BL so that a potential difference is generated between one end and the other end of the magnetoresistive element 11. For example, the clamp voltage Vc is applied to one selected bit line BL0, and the other selected bit line / BL0 is grounded (Gnd). The clamp voltage Vc is applied by a read circuit (not shown) in (or outside) the bit line drive circuit 7. At this time, the cell transistor M1 of the selected cell C00 is turned on, and a read current (sense current) Is flows through the selected cell C00 with the clamp voltage Vc applied to the magnetoresistive element 11.

Next, attention is paid to the non-selected cell C01 during the read operation. The bit line driving circuit 7 sets the bit line / BL1 in the non-selected column to a high impedance state and applies the power supply voltage Vdd to the bit line BL1. Here, when the boost voltage Vdh> (power supply voltage Vdd + threshold voltage Vth), the cell transistor M1 of the non-selected cell C01 is in the ON state. However, the bit line BL1 and the read circuit (not shown) are electrically disconnected. Therefore, the read current Is does not flow through the non-selected cell C01. At this time, a voltage (boost voltage Vdh-power supply voltage Vdd) is applied to the gate oxide film of the cell transistor M1 of the non-selected cell C01. That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide film of the cell transistor M1 of the non-selected cell C01. Thereby, the reliability of the cell transistor M1 can be maintained. When boost voltage Vdh <(power supply voltage Vdd + threshold voltage Vth), Vdd may be applied to bit line / BL1. At this time, since the gate-source voltage of the cell transistor M1 of the non-selected cell C01 is equal to or lower than Vth, the cell transistor M1 is in an off state and the read current Is does not flow.

Furthermore, attention is paid to the non-selected cells C10 and C11 during the read operation. The word line driving circuit 5 brings the word line WL1 of the non-selected row to the ground (Gnd) state. Accordingly, the cell transistors M1 of the non-selected cells C10 and C11 are in the off state. Accordingly, the read current Is does not flow through the non-selected cells C10 and C11. Further, the gate oxide films of the cell transistors M1 of the non-selected cells C10 and C11 are grounded (Gnd). That is, an excessive voltage (boost voltage Vdh) is not applied. Therefore, an excessive electric field is not applied to the gate oxide films of the cell transistors M1 of the non-selected cells C10 and C11. Thereby, the reliability of the cell transistor M1 can be maintained.

An example of the row-related word line driving circuit 5 that realizes the above operation can be the same as that of FIG. 5 (and FIG. 6) exemplified above. Therefore, the description regarding the word line driving circuit 5 is omitted.

Next, an example of the bit line driving circuit 7 that realizes the above operation will be described. FIG. 12 is a circuit diagram showing an example of the configuration of the bit line driving circuit in FIGS. 11A to 11C. The bit line drive circuit 7 includes a column decoder 24k (k = 0, 1,...) And a selector 25k (k = 0, 1,...) For selecting the bit lines BLk (k = 0, 1,...), / BLk. , And a write driver 26k (k = 0, 1,...) For supplying a predetermined voltage to the bit lines BLk, / BLk. The column decoder 24k is provided corresponding to the bit lines BLk and / BLk. It has two AND circuits. The selector 25k is provided corresponding to the bit lines BLk and / BLk. A transistor M20 is provided. The write driver 26k is provided corresponding to the bit lines BLk and / BLk. Clocked inverters INV1 and INVb, inverters, transistors M22, M23, and M23b are included.

Next, the operation of the bit line driving circuit 7 will be described with reference to FIG.
In the standby state, the signal WE, the signal RE, and the signal CP are all at a low level (0 V). Accordingly, both the terminals YW and YR are at a low level. At this time, the clocked inverters INV1 and INV1b are in a high impedance state because the terminal YW is at a low level. Then, the transistors M20 and M22 are turned off, and the transistors M23 and M23b are turned on. Thereby, both the bit lines BL and / BL are precharged to a high level (voltage Vdd).

Next, the operation when the write command is input and the signal WE becomes high level will be described. In the selected column, the signal Yi is at a high level, and thus the terminal YW is at a high level. At this time, the clocked inverters INV1 and INV1b output a high level (voltage Vdd) to one of the bit lines BL and / BL and a low level (0 V) to the other in accordance with the write data Din. Since the signal Yi is at a low level in the non-selected column, the terminal YW is at a low level. Therefore, the clocked inverters INV1 and INV1b are in a high impedance state. Since the terminal YR is at a low level, the transistors M20 and M22 are also turned off. On the other hand, since the signal CP is at a high level, the transistors M23 and M23b are in an off state. That is, the bit lines BL and / BL in the non-selected column are in a high impedance state while maintaining the power supply voltage Vdd.

Next, the operation when a read command is input and the signal RE becomes high level will be described. In the selected column, the signal Yi is at a high level, and thus the terminal YR is at a high level. At this time, the transistor M20 is turned on, and the transistor M22 is also turned on. Further, since the signal CP is at a high level, the transistors M23 and M23b are in an off state. Further, since the terminal YW is at a low level, the clocked inverters INV1 and INV1b are in a high impedance state. That is, the bit line BL is connected to the read circuit and clamped to the clamp voltage Vc, and the bit line / BL becomes low level. In the non-selected column, the signal Yi is at a low level, and the terminal YR is also at a low level. Accordingly, the transistor M20 is turned off, and the transistor M23 is also turned off. Therefore, the bit line BL is disconnected from the reading circuit, and the power supply voltage Vdd is maintained and the high impedance state is maintained. Since the transistors M22 and M23b are also in the off state, the bit line / BL is in a high impedance state while maintaining the power supply voltage Vdd.

According to the second embodiment described above, the cell area can be reduced by the word boost effect while ensuring the reliability of the gate oxide film of the cell transistor M1. That is, by maintaining the bit line potential of the unselected column at the power supply voltage Vdd, the number of memory cells in the state where an excessive voltage is applied to the gate oxide film can be reduced to only the selected memory cell. As a result, the number of reads and writes in the magnetic random access memory can be improved.

This embodiment can be changed as appropriate within the scope of the technical idea of the present invention. For example, it is possible to apply the bit line driving circuit 7 that applies an intermediate value Vm between the ground voltage and the power supply voltage to the bit line / BL of the selected column and applies (Vm + Vc) to the bit line BL during the read operation. It is.

According to the present invention, it is possible to provide a magnetic random access memory and an operation method of the magnetic random access memory that can reduce the bit cost more efficiently while maintaining the number of times of reading and writing.

The technologies in the above embodiments can be applied to each other as long as no technical contradiction arises.

Although the present invention has been described above with reference to the embodiment, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application is based on Japanese Patent Application No. 2008-255463 filed on Sep. 30, 2008, claiming the benefit of priority from that application, the disclosure of that application should be cited Is incorporated here as it is.

Claims

A memory array in which a plurality of memory cells are arranged in a matrix;
A plurality of word lines extending in a first direction;
A plurality of first bit lines and a plurality of second bit lines extending in a second direction different from the first direction;
A word line driving circuit for selecting a selected word line from the plurality of word lines;
A bit line driving circuit for selecting a selected first bit line and a selected second bit line from the plurality of first bit lines and the plurality of second bit lines;
Each of the plurality of memory cells includes
A first select transistor having a gate connected to a corresponding one of the plurality of word lines and one source / drain connected to a corresponding one of the plurality of first bit lines;
A magnetoresistive element having one end connected to the other source / drain of the first selection transistor,
In standby state
The word line driving circuit grounds the plurality of word lines;
The bit line driving circuit applies a first voltage to the plurality of first bit lines and the plurality of second bit lines;
In the write operation,
The word line driving circuit applies a second voltage higher than the first voltage to the selected word line;
The bit line driving circuit controls voltages of the selected first bit line and the selected second bit line so that a potential difference is generated between the selected first bit line and the selected second bit line. Access memory.
The magnetic random access memory according to claim 1,
A plurality of third bit lines extending in the second direction;
The bit line driving circuit further selects a selected third bit line from the plurality of third bit lines;
Each of the plurality of memory cells includes
A second select transistor having a gate connected to a corresponding one of the plurality of word lines and one source / drain connected to a corresponding one of the plurality of second bit lines;
The magnetoresistive element further has one end connected to the other source / drain of the second selection transistor and the other end connected to a corresponding one of the plurality of third bit lines. memory.
The magnetic random access memory according to claim 1,
Each of the plurality of memory cells includes
The magnetic random access memory, wherein the magnetoresistive element is connected at the other end to a corresponding one of the plurality of second bit lines.
The magnetic random access memory according to any one of claims 1 to 3,
In the write operation and the read operation,
The bit line drive circuit applies the first voltage to the plurality of first bit lines and the plurality of second bit lines excluding the selected first bit line and the selected second bit line. Magnetic random access memory.
The magnetic random access memory according to any one of claims 1 to 3,
In the write operation and the read operation,
The bit line driving circuit sets the plurality of first bit lines and the plurality of second bit lines excluding the selected first bit line and the selected second bit line to a high impedance state. Magnetic random access memory.
The magnetic random access memory according to claim 2,
In read operation,
The word line driving circuit applies a third voltage higher than the first voltage to the selected word line;
The bit line driving circuit includes the selected third bit line and the selected first bit so that a potential difference is generated between the selected third bit line and the selected first bit line and the selected second bit line. Magnetic random access memory for controlling the voltage of the line and the selected second bit line.
The magnetic random access memory according to claim 3,
In read operation,
The word line driving circuit applies a third voltage higher than the first voltage to the selected word line;
The bit line driving circuit controls voltages of the selected first bit line and the selected second bit line so that a potential difference is generated between the selected first bit line and the selected second bit line. Access memory.
A method of operating a magnetic random access memory, comprising:
Here, the magnetic random access memory is
A memory array in which a plurality of memory cells are arranged in a matrix;
A plurality of word lines extending in a first direction;
A plurality of first bit lines and a plurality of second bit lines extending in a second direction different from the first direction;
Each of the plurality of memory cells includes
A first select transistor having a gate connected to a corresponding one of the plurality of word lines and one source / drain connected to a corresponding one of the plurality of first bit lines;
A magnetoresistive element having one end connected to the other source / drain of the first selection transistor,
The operation method of the magnetic random access memory is as follows:
In standby state
Grounding the plurality of word lines;
Applying a first voltage to the plurality of first bit lines and the plurality of second bit lines,
In the write operation,
Applying a second voltage higher than the first voltage to a selected word line selected from the plurality of word lines;
The plurality of first bit lines and the plurality of second bit lines excluding the selected first bit line selected from the plurality of first bit lines and the selected second bit line selected from the plurality of second bit lines. Applying the first voltage to:
Controlling the voltages of the selected first bit line and the selected second bit line so that a potential difference is generated between the selected first bit line and the selected second bit line. How it works.
The operation method of the magnetic random access memory according to claim 8,
In read operation,
Applying a third voltage higher than the first voltage to the selected word line;
Applying the first voltage to the plurality of first bit lines and the plurality of second bit lines excluding the selected first bit line and the selected second bit line;
A method of operating a magnetic random access memory, comprising: controlling at least a voltage of the selected first bit line so that a potential difference is generated between the one end and the other end of the magnetoresistive element.