JP5315940B2 - Magnetic random access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic random access memory which allows the bit cost thereof to be more efficiently reduced while keeping the number of times of reading and writing. <P>SOLUTION: The magnetic random access memory includes word lines WL, memory cells C00, 01, 10, 11, and a row selecting circuit 2. In read out operation, the row selecting circuit 2 supplies first voltage to a word line WLi to be connected to a selection memory cell Cij. In write-in operation, the row selecting circuit 2 supplies second voltage being higher than the first voltage to a word line WLi to be connected to the selection memory cell Cij. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a magnetic random access memory using a magnetoresistive element (MTJ element) as a memory cell.

  Magnetic random access memory (MRAM) is one of the memories expected as a non-volatile memory that can be read and written indefinitely, can be operated at low voltage, and can operate at high speed. In the MRAM, a magnetoresistive element exhibiting a TMR (Tunnel MagnetoResistance) effect is used as a memory cell. In the magnetoresistive element, for example, a magnetic tunnel junction (MTJ: Magnetic Tunnel Junction) in which a tunnel barrier layer is sandwiched between two ferromagnetic layers is formed. One of the two ferromagnetic layers is a pinned layer whose magnetization direction is fixed, and the other one is a free layer whose magnetization direction can be reversed.

  A typical writing method in the MRAM cell is a biaxial writing method in which a writing current is supplied to each of two orthogonal wires, and the magnetization of the magnetoresistive element is reversed by a synthetic magnetic field generated by the current. When this biaxial writing method is employed, the memory cell typically employs a 1T1MTJ configuration including one MTJ element and one cell transistor for selecting the memory cell at the time of reading. In this case, there is a possibility that the memory cell area can realize a cell size similar to that of a DRAM. However, since a non-selected memory cell also has a state in which a magnetic field is applied (semi-selected state), the write operation margin is narrow. Typically, the write current is as large as about 5 mA, and it is difficult to increase the cell occupation ratio and increase the capacity.

  As an MRAM cell that solves this problem, an MRAM cell has been proposed in which a write current is conducted to a selected memory cell via a cell transistor to improve cell selectivity. For example, a 2T1MTJ cell can apply a reversal magnetic field only to the MTJ element of the selected memory cell by turning on two cell transistors and conducting a write current. In addition, the 1T1MTJ cell in which data is written by spin injection magnetization reversal is excellent in cell selectivity because a write current is supplied to the MTJ element of the selected memory cell via the cell transistor.

  A problem common to these MRAM cells is that the write current that can be supplied is limited by the size of the cell transistor, that is, the gate width. When the write current is large, the memory cell size depends on the size of the cell transistor. In order to realize it as a semiconductor memory, it is necessary to make its cell size as small as that of SRAM or DRAM, that is, reduction of write current is inevitable. For example, it is necessary to reduce the write current value to 500 μA or less in order to realize a bit cost equivalent to SRAM, and it is necessary to reduce it to 200 μA or less in order to realize a bit cost comparable to DRAM. Advances in magnetic thin film technology for reducing the magnetization reversal current of MTJ elements to this level are eagerly desired.

  As an approach for reducing the cell size of the MRAM cell, there is a word boost technique in which a voltage higher than the power supply voltage is applied to the word line in addition to a method of reducing the write current. As a result, the on-state current of the cell transistor can be substantially increased, and a larger write current can be driven to the memory cell.

  16A to 16C show an example of word boost for 2T1MTJ cells. As shown in FIG. 16A, all word lines WL and write bit lines WBL are grounded during standby. As shown in FIG. 16B, at the time of writing, a boost voltage Vdh higher than the power supply voltage Vdd is applied to the selected word line, a power supply voltage Vdd is applied to one of the write bit lines WBL, and the other write bit is applied. The write current Iw is supplied by grounding the line / WBL. On the other hand, as shown in FIG. 16C, at the time of reading, both the write bit lines WBL and / WBL are grounded, and the read bit line RBL is clamped to about 0.3 V to penetrate the MTJ element of the selected memory cell. The tunnel current Is is detected.

  Since the on-current of the cell transistor is substantially increased by this word boost technique, the gate width size of the cell transistor can be reduced with respect to the design parameter called the write current value. Accordingly, as shown in FIG. 17, it is possible to reduce the cell size of an MRAM cell of a type in which a write current is conducted to a memory cell via a cell transistor.

  In the above write operation and read operation, the write bit lines WBL, / WBL of the non-selected memory cells connected to the selected word line are in a grounded state. Accordingly, the boost voltage Vdh is applied between the gates and sources of all the cell transistors connected to the selected word line, and a high electric field is applied to the gate oxide film of the cell transistors. This is not preferable because it can be a factor that impairs the reliability of the cell transistor and limits the number of times of reading and writing.

  Therefore, an object of the present invention is to realize a magnetic random access memory that can reduce the bit cost more efficiently while maintaining the number of times of reading and writing.

  The magnetic random access memory according to the present invention includes a plurality of word lines, a plurality of memory cells, and a row selection circuit. In a read operation, the row selection circuit supplies a first voltage to a word line connected to the selected memory cell among the plurality of memory cells. In the write operation, the row selection circuit supplies a second voltage higher than the first voltage to a word line connected to the selected memory cell of the plurality of memory cells.

  According to the present invention, it is possible to provide a magnetic random access memory capable of reducing the bit cost more efficiently while maintaining the number of times of reading and writing.

  Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
1A to 1C are circuit diagrams illustrating the configuration of the MRAM according to the first embodiment. In the first embodiment, there is shown a so-called 2T1MTJ cell MRAM configuration in which each memory cell is composed of two cell transistors and a magnetoresistive element.

  In the memory array 1, memory cells Cij are arranged in a matrix. Each memory cell Cij includes two cell transistors 4 and 5 and a magnetoresistive element 6. In the present embodiment, NMOS transistors are used as the cell transistors 4 and 5, and MTJ elements are used as the magnetoresistive element 6. In the memory array 1, word lines WL are further extended in the row direction, and write bit lines WBL, / WBL and read bit line RBL are extended in the column direction. The word line WL is connected to the row selection circuit 2, and the write bit lines WBL, / WBL and the read bit line RBL are connected to the column selection circuit 3. 1A to 1C, a large number of memory cells are actually arranged in a matrix in the memory array 1, but only the memory cells C00, C01, C10, and C11 in 2 rows and 2 columns are shown for convenience of explanation.

  Hereinafter, access to the selected memory cell in the first embodiment will be described with reference to FIGS. 1A to 1C. In the following description, it is assumed that the memory cell C00 is a selected memory cell. That is, the memory cell C01 is an unselected memory cell at the intersection of the selected row and the unselected column, the memory cell C10 is an unselected memory cell at the intersection of the unselected row and the selected column, and the memory cell C11 is unselected from the unselected row. Unselected memory cells at the intersection of columns.

  FIG. 1A illustrates the state of each signal line in the standby state. Specifically, in the standby state, all word lines WL, write bit lines WBL, / WBL, and read bit line RBL are grounded.

  On the other hand, FIG. 1B illustrates the state of each signal line in the write operation. In the write operation, the word line WL0 and the write bit lines WBL0 and / WBL0 corresponding to the selected memory cell C00 are selected, and the write current Iw flows through the selected memory cell C00.

  Specifically, boost voltage Vdh higher than power supply voltage Vdd is applied to selected word line WL0. At the same time, the power supply voltage Vdd is applied to one of the selected write bit lines WBL0 and / WBL0, and the other is grounded. Which of the selected write bit lines WBL0 and / WBL0 is grounded is determined according to the write data. In one embodiment, when the write data is “1”, the selected write bit line / WBL0 is grounded, and when it is “0”, the selected write bit line WBL0 is grounded.

  As a result, the cell transistors 4 and 5 of the selected memory cell C00 are turned on when the boost voltage Vdh exceeding the threshold voltage Vth is applied between the gate and the source thereof. Therefore, the write current Iw flows from the selected write bit line WBL0 through the memory cell C00 to the selected write bit line / WBL0 (or from the selected write bit line / WBL0 through the memory cell C00 to the selected write bit line WBL0). . Due to the write current Iw, the magnetization of the free layer of the magnetoresistive element 6 is directed in a desired direction. That is, desired data is written into the magnetoresistive element 6 of the selected memory cell C00. As described above, the boost voltage Vdh higher than the power supply voltage Vdd is supplied to the selected word line WL0 in order to flow a large write current Iw while reducing the size of the cell transistors 4 and 5. During the write operation, the read bit line RBL0 is desirably set in a high impedance state so that the write current Iw does not leak through the magnetoresistive element 6.

  On the other hand, the write current Iw does not flow through the unselected memory cells C01, C10, and C11. First, for the non-selected memory cell C01 connected to the selected word line WL0, the cell transistors 4 and 5 of the memory cell C01 are turned on, but the potential difference between the write words WBL1 and / WBL1 is zero. Accordingly, the write current Iw does not flow through the non-selected memory cell C01. For the unselected memory cells C10 and C11 connected to the unselected word line WL1, since the word line WL1 is grounded, the cell transistors 4 and 5 of the memory cells C10 and C11 are in the off state. Accordingly, the write Iw does not flow to the memory cells C10 and C11.

  Furthermore, FIG. 1C illustrates the state of each signal line in the read operation. During the read operation, unlike the write operation, the power supply voltage Vdd is applied to the selected word line WL0. At the same time, the clamp voltage Vc is applied to the selected read bit line RBL0 by a read circuit (not shown), and both the selected write bit lines WBL0 and / WBL0 are grounded. As a result, the cell transistors 4 and 5 of the selected memory cell C00 are turned on, and the sense current Is flows through the selected memory cell C00 with the clamp voltage Vc applied to the magnetoresistive element 6. Here, it should be noted that in the read operation, the power supply voltage Vdd is applied between the gate and the source of the cell transistors 4 and 5 of the selected memory cell C00, that is, no excessive high voltage is applied. The sense current Is is detected by the read circuit, and the data stored in the selected memory cell C00 is identified from the current level of the sense current Is. In one embodiment, the data stored in the selected memory cell C00 is identified by comparing the sense current Is with the reference current Iref flowing through the selected reference cell.

  The MR ratio of the MTJ element (that is, the ratio between the resistance value in the “0” state and the resistance value in the “1” state) has a characteristic that depends on the voltage across the MTJ element. When the voltage is 0.3V to 0.5V, the sense signal becomes the maximum value. Therefore, the clamp voltage Vc is preferably designed to be in the range of 0.3V to 0.5V.

  On the other hand, the sense current Is does not flow for the non-selected memory cells C01, C10, and C11. First, for the non-selected memory cell C01 connected to the selected word line WL0, the non-selected read bit line RBL1 is set to a high impedance state, and the non-selected write bit lines WBL1 and / WBL1 are both grounded. Although the cell transistors 4 and 5 of the unselected memory cell C01 connected to the selected word line WL0 are turned on, the read bit line RBL1 is set to a high impedance state and is electrically disconnected from the read circuit, so that the sense current Is does not flow. Note that the unselected read bit line RBL1 may be grounded during the read operation.

  For the memory cells C10 and C11 connected to the non-selected word line WL1, since the non-selected word line WL1 is grounded, the cell transistors 4 and 5 of the memory cells C10 and C11 are turned off. Therefore, the sense current Is does not flow through the memory cells C10 and 11.

  It should be noted in the above write operation and read operation that the selected word line is driven with the boost voltage Vdh only during the write operation, and the selected word line is driven with the power supply voltage Vdd during the read operation. In the present embodiment, during the write operation, a boost voltage Vdh higher than the power supply voltage Vdd is applied to the gate of the selected word line WL0 in order to flow a large write current Iw. However, during the read operation, the selected word line WL0 is driven with the power supply voltage Vdd in order to reduce the time during which a high voltage (that is, the boost voltage Vdh) is applied to the gate oxide films of the cell transistors 4 and 5. Thereby, the area of the cell transistors 4 and 5, that is, the area of the memory cell Cij can be reduced while improving the reliability of the gate oxide film and maintaining the number of times of reading and writing.

  As described above, the row selection circuit 2 has a function of supplying the boost voltage Vdh to the selected word line at the time of writing and supplying the power supply voltage Vdd to the selected word line at the time of reading. Hereinafter, the configuration of the row selection circuit 2 for realizing such a function will be described.

  FIG. 2 is a block diagram showing an example of the configuration of the row selection circuit 2. The row selection circuit 2 in FIG. 2 includes a plurality of row decoders 21, word drivers 22-0 to 22-n, and a word voltage control unit 23. The row decoder 21 and the word drivers 22-0 to 22-n function as a word line selection circuit that selects a word line corresponding to the memory cell Cij. The row decoder 21 and the word drivers 22-0 to 22-n are arranged side by side in the column direction. The word drivers 22-0 to 22-n are provided corresponding to the word lines WL0 to WLn, respectively. One row decoder 21 is provided for every four word lines WL.

  FIG. 3 is a circuit diagram showing details of the configuration of the row decoder 21, the word drivers 22-0 to 22-n, and the word voltage control unit 23. The row decoder 21 includes NMOS transistors M11 to M14. Each word driver 22-i includes an NMOS transistor M15 and PMOS transistors M16 to M18. The word voltage control unit 23 includes PMOS transistors M19, M20, and M22 and an NMOS transistor M21.

  For the row decoder 21, the word drivers 22-0 to 22-n, and the word voltage control unit 23, two types of transistors, a normal withstand voltage transistor (core transistor) and a high withstand voltage transistor, are used. The high breakdown voltage transistor is configured such that the gate oxide film is thicker than the core transistor and can withstand the application of the boost voltage Vdh. In FIG. 2 (and FIG. 9, FIG. 12, FIG. 14), the MOS transistor shown with the channel portion being a double line is a high breakdown voltage transistor.

  In detail, a core transistor is used as the NMOS transistors M11 to M13 of the row decoder 21, and a high breakdown voltage transistor is used as the NMOS transistor M14. High breakdown voltage transistors are used as the NMOS transistors M15 and PMOS transistors M16 to M18 of the word drivers 22-0 to 22-n. In addition, high voltage transistors are used as the PMOS transistors M20 and M22 and the NMOS transistor M21 of the word voltage control unit 23, and a core transistor is used as the PMOS transistor M19.

The row selection circuit 2 generally operates as follows. When data access is requested, the row decoder 21 selects the word driver 22-i corresponding to the word line WLi to be selected in response to the row address, and is connected to the selected word driver 22-i. Pull down the current node N2i to low level. The word voltage control unit 23 has a function of supplying the drive voltage V _DRV to the word driver 22. Word voltage control unit 23 sets the drive voltage _{V DRV} during write operation to the boost voltage Vdh, during a read operation to set the driving voltage _{V DRV} to the power supply voltage Vdd. The selected word driver 22-i drives the selected word line WLi to the drive voltage V _DRV received from the word voltage control unit 23 in response to the pull-down of the node N 2 i. The drive voltage V _DRV supplied from the word voltage control unit 23 is set to the boost voltage Vdh during the write operation and set to the power supply voltage Vdd during the read operation. As a result, the boost voltage Vdh is set to the selected word line WLi during the write operation. At the time of reading, the power supply voltage Vdd is supplied to the selected word line WLi.

  Hereinafter, details of the driving operation of the word line WL by the row selection circuit 2 will be described with reference to FIGS. 3 and 4. In the following, only operations related to driving when any one of the word lines WL0 to WL3 is selected will be described, but those skilled in the art will understand that other word lines WL are driven in the same manner.

  In FIG. 3, control signals X234, X567, and X89 are signals obtained by predecoding input row addresses, and their amplitudes are the same as the power supply voltage Vdd. Here, the control signals X01e0 to X01e3 are signals generated by taking the AND logic of the signal obtained by decoding the lower 2 bits of the row address and the access enable signal, and the amplitude thereof is the boost voltage. It is the same as Vdh. The symbol “RP” represents a low precharge signal. The row precharge signal RP is a signal for instructing to precharge the nodes N20 to N23 connected to each word driver 22 to a high level (Vdh), and the amplitude thereof is the same as the boost voltage Vdh. In addition, a write enable signal WE is supplied to the word voltage control unit 23. The write enable signal WE is set to a high level (Vdh) during a write operation, and is set to a low level (0 V) during a read operation.

  In the standby state, the control signals X01e0 to X01e3 are set to a low level (0V), and the low precharge signal RP is also set to a low level. Thereby, the NMOS transistor M14 is turned off and the PMOS transistor M18 is turned on. The That is, the nodes N20 to N23 are precharged to the boost voltage Vdh, and the word lines WL0 to WL3 are set to a low level (0 V). The PMOS transistor M17 is provided to hold the nodes N20 to N23 at a high level (Vdh), and the W / L ratio (W: gate width, L: gate length) is higher than that of other MOS transistors. Is much smaller.

During a read operation, the write enable signal WE is set to a low level (0 V). As a result, the PMOS transistor M19 of the word voltage control unit 23 is turned on, the PMOS transistor M20 is turned off, and the power supply voltage Vdd is supplied to the node N3. That is, the drive voltage V _DRV supplied to each word driver 22 is set to the power supply voltage Vdd. In each word driver 22, the low precharge signal RP is set to a high level (Vdh), and the PMOS transistor M18 is turned off. Further, in the selected row decoder 21, the control signals X234, X567, and X89 are set to the high level (Vdd), and the control signal X01ei corresponding to the selected word line WLi among the control signals X01e0 to X01e3 is high. Set to level (Vdh). As a result, the NMOS transistors M11 to M13 and the NMOS transistor M14-i are turned on, and the node N2i transits to a low level (0 V).

At this time, the NMOS transistor M15 is turned off of the word driver 22-i, since the PMOS transistor M16 is set to ON, the driving voltage _{V DRV} of the node N3 is supplied to the selected word line WLi. As described above, since the drive voltage V _DRV matches the power supply voltage Vdd during the read operation, as a result, the selected word line WLi is driven to the power supply voltage Vdd.

  When the read operation is completed, the control signal X01ei and the row precharge signal RP are returned to the low level. As a result, the NMOS transistor M14-i is turned off, the PMOS transistor M18 is turned on, the node N2i transits to the high level (Vdh), and the word line WLi goes to the low level.

On the other hand, in the write operation, the word enable signal WE is set to a high level (Vdh), the PMOS transistor M19 of the word voltage control unit 23 is turned off, and the PMOS transistor M20 is turned on. As a result, the boost voltage Vdh is supplied to the node N3. That is, the drive voltage V _DRV supplied to each word driver 22 is set to the boost voltage Vdh. In each word driver 22, the row precharge signal RP becomes high level (Vdh), and the PMOS transistor M18 is turned off. Further, in the selected row decoder 21, the control signals X234, X567, and X89 are set to the high level (Vdd), and the control signal X01ei corresponding to the selected word line WLi among the control signals X01e0 to X01e3 is high. Set to level (Vdh). As a result, the NMOS transistors M11 to M13 and the NMOS transistor M14-i are turned on, and the node N2i transits to a low level (0 V).

At this time, the NMOS transistor M15 is turned off of the word driver 22-i, since the PMOS transistor M16 is set to ON, the driving voltage _{V DRV} of the node N3 is supplied to the selected word line WLi. Since the driving voltage _{V DRV} during a read operation matches the boost voltage Vdh, as a result, the selected word line WLi is driven to boosted voltage Vdh.

  When the write operation is completed, the control signal X01ei and the row precharge signal RP are returned to the low level. As a result, the NMOS transistor M14-i is turned off, the PMOS transistor M18 is turned on, the node N2i changes to the high level (Vdh), and the word line WLi becomes the low level.

  According to the MRAM of the first embodiment described above, the cell area can be reduced by the word boost technique while ensuring the reliability of the gate oxide film of the cell transistor of the memory cell. That is, by driving the word line with the boost voltage Vdh only during the write operation and driving the word line with the power supply voltage Vdd during the read operation, it is possible to reduce the time during which an excessive voltage is applied to the gate oxide film. In many applications, the number of times of reading data is larger than that of writing data to the memory. Therefore, according to the configuration of the MRAM of this embodiment in which an excessive voltage is not applied to the gate oxide film of the memory cell during the read operation, the reliability of the gate oxide film can be effectively improved.

  As a modification of the MRAM of the first embodiment, there is an MRAM having a configuration in which write wirings to which a complementary voltage is applied at the time of writing are arranged at right angles. In this modification, one of the write wirings is connected to the column selection circuit, and the other of the write wirings is connected to the row selection circuit 2. At the time of writing, the row selection circuit 2 is configured to supply the boost voltage Vdh and the ground voltage to the word line, and is configured to supply the power supply voltage Vdd or the ground voltage to the write wiring connected thereto. . Therefore, in this modification, the row selection circuit 2 needs to be configured to be able to output three voltages. One method for realizing such an operation is to add a write row decoder and a write word driver to the row selection circuit 2 of the first embodiment in addition to the row decoder 21 and the word driver 22. The word driver 22 is selected by the row decoder 21 using a selection signal whose amplitude is equal to the boost voltage Vdh, while the write word driver connected to the write wiring is a write row decoder using a selection signal whose amplitude is equal to the power supply voltage Vdd. Is selected. Since the amplitude of the output of the row decoder 21 is Vdh and the amplitude of the output of the write row decoder is Vdd, these row decoders cannot be shared and the circuit area increases.

  On the other hand, in the MRAM configured as shown in FIGS. 1A to 1C, the row selection circuit 2 and the column selection circuit 3 are used by using two write bit lines WBLi and / WBLi in parallel as write wirings to which complementary voltages are applied during writing. Thus, the circuit area can be reduced. That is, at the time of writing, the row selection circuit 2 need only supply the boost voltage Vdh or the ground potential Gnd to the word line, and does not need to supply the power supply voltage Vdd. In the column selection circuit 3, the write driver that supplies a voltage to one write bit line WBLi and the write driver that supplies a voltage to the other write bit line WBLi both receive a selection signal whose amplitude is the power supply voltage Vdd. And can be selected by a column decoder (not shown). Therefore, a part of the column decoder that selects these write drivers can be shared. As a result, the area of the row selection circuit 2 and the column selection circuit 3 can be reduced as compared with the above-described modification.

  In the present embodiment, the configuration of the row selection circuit 2 can be changed to various configurations other than the configuration illustrated in FIG. FIG. 5 shows another example of the configuration of the row selection circuit 2. In the row selection circuit 2 of FIG. 5, a plurality of word voltage control units 23 are provided. In one embodiment, the row selection circuit 2 is provided with four word voltage controllers 23, and each word voltage controller 23-i is connected to every fourth word driver 22. Control signals WE0 to WE3 are supplied to the word voltage controllers 23-0 to 23-3, respectively. The control signals WE0 to WE3 are generated by taking the AND logic of the signal obtained by decoding the lower 2 bits of the row address and the write enable signal WE. Each configuration of the word voltage control units 23-0 to 23-3 is the same as that of the word voltage control unit 23 of FIG.

It should be noted that the number of word voltage control units 23 is not limited to four. At this time, the number of lower bits of the row address used for generating the control signal WEi is changed according to the number of word voltage control units 23. When 2 ^N word voltage control units 23 are provided, control signals WE0 to WE (2 ^N −1) are generated from the lower N bits of the row address and the write enable signal WE.

During the read operation, all the control signals WE0 to WE3 are set to the low level, and the four word voltage control units 23-0 to 23-3 supply the power supply voltage Vdd to the nodes N30 to N33, respectively. That is, the drive voltage V _DRV generated at the nodes N30 to N33 is the power supply voltage Vdd. The word driver 21 corresponding to the selected word line WLi sets the node N2i to the low level in response to a signal (not shown) obtained by predecoding the row address, whereby one word driver 22 -I is selected. The selected word driver 22-i drives the selected word line WLi to the drive voltage V _DRV supplied from the corresponding word voltage control unit 23. During the read operation, the drive voltage V _DRV generated at any of the nodes N30 to N33 matches the power supply voltage Vdd. As a result, the selected word line WLi is driven to the power supply voltage Vdd.

During the write operation, one of the control signals WE0 to WE3 is set to the high level and the other three are set to the low level according to the lower 2 bits of the selected row address. Hereinafter, a case where the control signal WE0 is at a high level will be described as an example. The word voltage control unit 23-0 selected by the control signal WE0 supplies the boost voltage Vdh to the node N30. That is, the drive voltage V _DRV supplied from the word voltage control unit 23-0 matches the boost voltage Vdh. The other three word voltage controllers 23-1 to 23-3 supply the power supply voltage Vdd to the nodes N31 to N33. In response to a signal (not shown) obtained by predecoding the row address, the word driver 21 corresponding to the selected word line WLi sets the node N2i to the low level, whereby one word driver 22-i Is selected. The selected word driver 22-i is driven to the drive voltage V _DRV supplied from the selected word voltage control unit 23-0. During the write operation, the drive voltage V _DRV supplied from the selected word voltage control unit 23-0 matches the boost voltage Vdh. As a result, the selected word line WLi is driven to the boost voltage Vdh.

  In the configuration of the row selection circuit 2 in FIG. 5, the power consumption of the word selection circuit can be reduced as compared with the row selection circuit 2 in FIG. In the row selection circuit 2 in FIG. 2, when the read operation is performed following the write operation, or when the write operation is performed subsequent to the read operation, the voltage of the node N3 is changed from the boost voltage Vdh to the power supply voltage Vdd. Or, it is necessary to switch to the reverse. Since the parasitic capacitance of the node N3 is large, large power consumption is required to switch the voltage of the node N3. On the other hand, in the row selection circuit 2 of FIG. 5, since the number of word drivers 22 connected to each of the nodes N30 to N33 is smaller than that of the node N3, the parasitic capacitance of the nodes N30 to N33 is smaller than that of the node N3 of FIG. . In the circuit configuration of FIG. 5, since only one of the nodes N30 to N33 is switched from the boost voltage Vdh to the power supply voltage Vdd or vice versa, the power required to drive the one node is The power is smaller than that required for driving the node N3 of the row selection circuit 2 in FIG. Therefore, according to the circuit configuration of FIG. 5, power consumption can be reduced.

  Furthermore, according to the circuit configuration of FIG. 5, the operation of the word selection circuit can be accelerated compared to the circuit configuration of FIG. In the circuit configuration of FIG. 5, the parasitic capacitance of the nodes (that is, the nodes N30 to N33) whose potential is switched from the boost voltage Vdh to the power supply voltage Vdd or vice versa is small. Therefore, when the potential of the node is switched from the boost voltage Vdh to the power supply voltage Vdd or vice versa, the delay time due to the resistance and parasitic capacitance of the node can be shortened.

  FIG. 6 is a circuit diagram showing still another example of the configuration of the row selection circuit 2. In the row selection circuit 2 of FIG. 6 as well, the row decoder 21 and the word driver 22 are arranged in the column direction, and a plurality of word voltage control units 23 are provided. In FIG. 6, two word voltage control units 23-0 and 23-1 are provided. One word voltage control unit 23-0 is connected to the lower half word drivers 22-0 to 22- (m-1), and the other word voltage control unit 23-1 is connected to the upper half word driver 22-m. To 22-n. The word voltage control units 23-0 and 23-1 can also be arranged between the row decoders 21. Each configuration of the word voltage control units 23-0 to 23-1 is the same as that of the word voltage control unit 23 of FIG.

  The control signals WE0 and WE1 are signals generated by taking the AND logic of the signal obtained by decoding the upper 1 bit of the row address and the write enable signal WE. It should be noted that the number of word voltage control units 23 is not limited to two. At this time, the number of lower bits of the row address used for generating the control signal WEi is changed according to the number of word voltage control units 23.

During the read operation, both the control signals WE0 and WE1 are set to a low level. Accordingly, the two word voltage control units 23-0 and 23-1 supply the power supply voltage Vdd to the nodes N30 and N31, respectively. That is, the drive voltage V _DRV supplied to the nodes N30 and N31 both matches the power supply voltage Vdd. In response to a signal (not shown) obtained by predecoding the row address, the word driver 21 sets one node N2i among the nodes N20 to N2n to the low level, thereby one word The driver 22-i is selected. The selected word driver 22-i drives the selected word line WLi using the drive voltage _VDRV supplied from the word voltage control unit 23-0 or 23-1. Since drive voltage _VDRV matches power supply voltage Vdd, selected word line WLi is driven to power supply voltage Vdd.

During the write operation, one of the control signals WE0 and WE1 is set to the high level and the other is set to the low level according to the upper 1 bit of the row address of the selected memory cell. Hereinafter, a case where the control signal WE0 is set to a high level (that is, one of the word lines WL0 to WL (m−1) is selected as a selected word line) will be described as an example. The selected word voltage control unit 23-0 supplies the boost voltage Vdh to the node N30. That is, the drive voltage V _DRV supplied from the word voltage control unit 23-0 matches the boost voltage Vdh. The other word voltage control unit 23-1 supplies the power supply voltage Vdd to the node N31. The row decoder 21 responds to a signal (not shown) obtained by predecoding the row address, and one node N2i among the nodes N20 to N2m (i is an integer of 0 to m-1). As a result, one word driver 22-i is selected. Word driver 22-i selected by using the driving voltage V _DRV supplied from a word voltage control unit 23-0 which are selected to drive the selected word line WLi. During the write operation, the drive voltage V _DRV supplied from the selected word voltage control unit 23-0 matches the boost voltage Vdh. As a result, the selected word line WLi is driven to the boost voltage Vdh.

  According to the configuration of the cell selection circuit 2 in FIG. 6, the power consumption can be reduced as compared with the circuit configuration in FIG. 2, and the operation of the word selection circuit can be accelerated. In the circuit configuration of FIG. 6, the number of word drivers 22 connected to each of the nodes N30 and N31 can be reduced, and the lengths of the nodes N30 and N31 can be made shorter than the node N3 of the circuit of FIG. That is, according to the circuit of FIG. 6, the parasitic capacitances and wiring resistances of the nodes N30 and N31 can be made smaller than the node N3 of the circuit of FIG. Therefore, according to the circuit configuration of FIG. 6, power consumption can be reduced and the operation of the word selection circuit can be accelerated.

  FIG. 7 is a diagram showing still another example of the configuration of the row selection circuit 2. In the configuration of FIG. 7, the word lines are hierarchized. That is, the sub word line SWL is provided in the memory array 1 in addition to the main word line MWL. The length of the sub word line SWL is shorter than that of the main word line MWL. In addition, the row selection circuit 2 includes a main row selection circuit 12 and a sub row selection circuit 13. In one embodiment, two sub-row selection circuits 13-0 and 13-1 are provided in the memory array 1. The configuration and operation of the main row selection circuit 12 are the same as those of the row selection circuit 2 in FIG. 4 except that the main word line MWL is driven instead of the word line WL. The main row selection circuit 12 is connected to the sub row selection circuits 13-0 and 13-1 via the main word line MWL. Memory array 1 is divided into four sub memory arrays 11-0 to 11-3. The sub memory arrays 11-0 and 11-1 are connected to the sub row selection circuit 13-0, and the sub memory arrays 11-2 and 11-3 are connected to the sub row selection circuit 13-1. Each sub row selection circuit 13 selects a sub word line SWL in response to the voltage level of the main word line MWL and the column address signals Y0 and Y0B.

  In one embodiment, the sub row selection circuit 13-0 includes PMOS transistors M000 to M003 and NMOS transistors M100 to 103. Similarly, the sub row selection circuit 13-1 includes PMOS transistors M010-M013 and an NMOS transistor M110-113. As these MOS transistors, high breakdown voltage transistors are used. The column address signals Y0 and Y0B supplied to the sub-row selection circuits 13-0 and 13-1 are at the boost voltage Vdh at the high level and the ground potential Gnd at the low level.

  Note that the number of sub-row selection circuits 13 is not limited to two. The number of sub-row selection circuits 13 is changed according to the division of the memory array 1.

Next, the operation of the row selection circuit (that is, the main row selection circuit 12 and the sub row selection circuit 13) in FIG. 7 will be described. In the read operation, the write enable signal WE is set to a low level, and the word voltage control unit 23 sets the drive voltage _VDRV supplied to the node N3 to the power supply voltage Vdd. The word driver 22-i corresponding to the selected main word line MWLi sets the node N2i to the low level in response to the row address signal, whereby one word driver 22-i is selected. The selected word driver 22-i drives the selected main word line MWLi to the drive voltage V _DRV supplied from the word voltage control unit 23. During the read operation, the drive voltage _VDRV supplied to the node N3 is set to the power supply voltage Vdd. As a result, the selected main word line MWLi is driven to the power supply voltage Vdd. The non-selected word driver 22 sets the other main word line MWL to the ground voltage.

  Hereinafter, a case where the selected memory cell is included in the sub memory array 11-0 or 11-1 and not included in the sub memory arrays 11-2 and 11-3 will be described. The selected main word line MWLi supplies the power supply voltage Vdd to the PMOS transistor M00i of the sub row selection circuit 13-0 corresponding to the sub memory arrays 11-0 and 11-1. The column address signal Y0 is set to the low level, and the PMOS transistors M000 to M003 of the sub-row selection circuit 13-0 are turned on, and the NMOS transistors M100 to M103 are turned off. The selected sub word line SWLi0 is driven to the power supply voltage Vdd. On the other hand, the other main word line MWL supplies the ground voltage to the PMOS transistors M00x other than the PMOS transistor M00i of the sub-row selection circuit 13-0. Therefore, the non-selected sub word line SWL connected to the sub row selection circuit 13-0 is driven to the ground voltage.

  Further, the selected main word line MWLi supplies the power supply voltage Vdd to the PMOS transistor M01i of the sub-row selection circuit 13-1. However, the column address signal Y0B is set to the high level, the PMOS transistors M010 to M013 of the sub-row selection circuit 13-1 are turned off, and the NMOS transistors M110 to M113 are turned on. As a result, they are connected to the sub-row selection circuit 13-1. All the sub-word lines SWL01-31 that are connected are grounded.

In the write operation, the write enable signal WE is set to the high level, setting the drive voltage V _DRV word voltage control unit 23 is supplied to the node N3 to the boost voltage Vdh. The word driver 22-i corresponding to the selected main word line MWLi sets the node N2i to the low level in response to the row address signal, thereby selecting one word driver 22-i. The selected word driver 22-i drives the selected main word line MWLi to the drive voltage V _DRV supplied from the word voltage control unit 23. During the write operation, the boost voltage Vdh is supplied to the node N3. As a result, the selected main word line MWLi is driven to the boost voltage Vdh.

  Hereinafter, a case where the selected memory cell is included in the sub memory array 11-0 or 11-1 and not included in the sub memory array 2-3 will be described. The selected main word line MWLi supplies the boost voltage Vdh to the PMOS transistor M00i of the sub row selection circuit 13-0 corresponding to the sub memory arrays 11-0 and 11-1. The column address signal Y0 is set to the low level, the PMOS transistors M000 to M003 of the sub row selection circuit 13-0 are turned on, the NMOS transistors M100 to M103 are turned off, and the selected sub word line SWLi0 is driven to the boost voltage Vdh. . The other main word line MWL supplies the ground voltage to the PMOS transistors M00x other than the PMOS transistor M00i of the sub-row selection circuit 13-0. Therefore, the non-selected sub third line SWL connected to the sub row selection circuit 13-0 is driven to the ground voltage.

  Further, the selected main word line MWLi supplies the boost voltage Vdh also to the PMOS transistor M01i of the corresponding sub-row selection circuit 1. However, the column address signal Y0B is set to the high level, the PMOS transistors M010 to M013 of the sub-row selection circuit 13-1 are turned off, and the NMOS transistors M110 to M113 are turned on. As a result, the column address signal Y0B is connected to the sub-row selection circuit 13-1. All the sub-word lines SWL01-31 that are connected are grounded.

  According to the configuration of the row selection circuit 2 in FIG. 7, it is expected that the cell area is reduced by the word boost technique while ensuring the reliability of the gate oxide film of the cell transistor of the memory cell. That is, by driving the word line with the boost voltage Vdh only during the write operation and driving the word line with the power supply voltage Vdd during the read operation, it is possible to reduce the time during which an excessive voltage is applied to the gate oxide film. Furthermore, since the word lines are hierarchized, the number of memory cells selected simultaneously can be reduced. As a result, the time during which an excessive voltage is applied to the gate oxide film can be reduced. In many applications, the number of times of reading data is larger than that of writing data to the memory. Therefore, according to the configuration of the MRAM of this embodiment, the reliability of the gate oxide film can be improved more effectively.

  In the MRAM of the present embodiment, the number of main word lines and sub word lines is the same for convenience of explanation, but by supplying a signal obtained by predecoding a row address to the sub row selection circuit 13, It should be noted that a configuration in which the number of main word lines is reduced can be taken.

(Second Embodiment)
8A to 8C are circuit diagrams showing a configuration of the MRAM according to the second exemplary embodiment of the present invention. In the second embodiment, reference cells Rij arranged in two rows of reference cell rows are used for data reading. The configuration of each reference cell Rij is the same as that of the memory cell Cij. In the memory array 1, reference word lines WLR0 and WLR1 for selecting the reference cell Rij are extended in the row direction. In addition, in the present embodiment, the read bit line / RBL is arranged in the memory array 1 in addition to the read bit line RBL.

  8A to 8C, a large number of memory cells are actually arranged in a matrix in the memory array 1, but only the memory cells C00, C01, C10, and C11 of 2 rows and 2 columns are shown for convenience of explanation. . Similarly, for the reference cells, a large number of reference cells are actually arranged in the reference row, but only the reference cells R00, R01, R10, and R11 in 2 rows and 2 columns are shown for convenience of explanation. Note that the number of columns of reference cells is preferably the same as the number of columns of memory cells. In the present embodiment, in the memory array 1, even-numbered memory cells are shifted from the odd-numbered memory cells by a half of the length of the memory cells in the row direction. In the two reference rows, the reference cell of one reference row is arranged with a shift of half the length of the memory cell in the row direction with respect to the reference cell of the other reference row.

  The access to the selected memory cell in the second embodiment will be described below with reference to FIGS. 8A to 8C. In the following description, it is assumed that the memory cell C00 is a selected memory cell. That is, the memory cell C01 is an unselected memory cell at the intersection of the selected row and the unselected column, the memory cell C10 is an unselected memory cell at the intersection of the unselected row and the selected column, and the memory cell C11 is unselected from the unselected row. Unselected memory cells at the intersection of columns.

  FIG. 8A illustrates the state of each signal line in the standby state. Specifically, in the standby state, all word lines WL, write bit lines WBL, / WBL, and read bit lines RBL, / RBL are grounded.

  On the other hand, FIG. 8B illustrates the state of each signal line in the write operation. In the write operation, the word line WL0 is selected, and the write bit lines WBL0 and / WBL0 and the read bit line RBL0 are selected, and thereby the memory cell C00 is selected. Specifically, boost voltage Vdh higher than power supply voltage Vdd is applied to selected word line WL0. At the same time, the power supply voltage Vdd is applied to one of the selected write bit lines WBL0 and / WBL0, and the other is grounded. Which of the selected write bit lines WBL0 and / WBL0 is grounded is determined according to the write data. In one embodiment, when the write data is “1”, the selected write bit line / WBL0 is grounded, and when it is “0”, the selected write bit line WBL0 is grounded.

  As a result, the cell transistors 4 and 5 of the selected memory cell C00 are turned on when the boost voltage Vdh exceeding the threshold voltage Vth is applied between the gate and the source thereof. Accordingly, the write current Iw conducts the memory cell C00 from the selected write bit line WBL0 to the selected write bit line / WBL0 (or conducts the memory cell C00 from the selected write bit line / WBL0 to the selected write bit line WBL0. ) Flowing. The write current Iw directs the magnetization of the free layer of the magnetoresistive element 6 in a desired direction, that is, desired data is written to the magnetoresistive element 6 of the selected memory cell C00. At this time, it is desirable that the read bit line RBL0 be in a high impedance state so that the write current does not leak through the MTJ element.

  On the other hand, the write current Iw does not flow through the unselected memory cells C01, C10, and C11. First, for the non-selected memory cell C01 connected to the selected word line WL0, the cell transistors 4 and 5 of the memory cell C01 are turned on, but the potential difference between the write words WBL1 and / WBL1 is zero. Accordingly, the write current Iw does not flow through the memory cell C01. For the unselected memory cells C10 and C11 connected to the unselected word line WL1, since the word line WL1 is grounded, the cell transistors 4 and 5 of the memory cells C10 and C11 are in the off state. Accordingly, the write current Iw does not flow through the memory cells C10 and C11.

  Similarly, the write current Iw does not flow in the reference cells R00, 01, 10, and 11. That is, during the write operation, the reference word lines WLR0 and WLR1 are grounded, so that the cell transistors 4 and 5 of each reference cell are turned off. Accordingly, the write current Iw is not conducted to the reference cells R00, 01, 10, and 11 during the write operation.

  Further, FIG. 8C illustrates the state of each signal line in the read operation. In the read operation, unlike the write operation, the power supply voltage Vdd is applied to the selected word line WL0. At the same time, the clamp voltage Vc is applied to the selected read bit line RBL0 by a read circuit (not shown), and both the selected write bit lines WBL0 and / WBL0 are grounded. As a result, the cell transistors 4 and 5 of the selected memory cell C00 are turned on, and the sense current Is flows through the selected memory cell C00 with the clamp voltage Vc applied to the magnetoresistive element 6. Here, it should be noted that in the read operation, the power supply voltage Vdd is applied between the gate and the source of the cell transistors 4 and 5 of the selected memory cell C00, that is, no excessive high voltage is applied.

  In addition, in the read operation, the reference word line WLR1 is selected, and the write bit lines WBL1, / WBL0 and the read bit line / RBL0 are selected. That is, the reference cell R10 located at the intersection of the reference word line WLR1, the write bit lines WBL1, / WBL0 and the read bit line / RBL0 is selected.

  Specifically, the power supply voltage Vdd is applied to the selected reference word line WLR1. At the same time, the clamp voltage Vc is applied to the selected read bit line / RBL0 by the read circuit, and both the selected write bit lines WBL1 and / WBL0 are grounded. When the cell transistors 4 and 5 of the selected reference cell R10 are turned on and the clamp voltage Vc is applied to the magnetoresistive element 6, the reference current Iref flows through the selected reference cell R10. Here, it should be noted that the power supply voltage Vdd is applied between the gate and the source of the cell transistors 4 and 5 of the selected reference cell R10, that is, no excessive high voltage is applied.

  The data stored in the selected memory cell C00 is identified by comparing the sense current Is flowing through the selected memory cell C00 with the reference current Iref flowing through the selected reference cell R10.

  On the other hand, the sense current Is does not flow for the non-selected memory cells C01, C10, and C11. First, for the non-selected memory cell C01 connected to the selected word line WL0, the non-selected read bit line RBL1 is set to a high impedance state, and the non-selected write bit lines WBL1 and / WBL1 are both grounded. Although the cell transistors 4 and 5 of the unselected memory cell C01 connected to the selected word line WL0 are turned on, the read bit line RBL1 is set to a high impedance state and is electrically disconnected from the read circuit, so that the sense current Is does not flow. Note that the unselected read bit line RBL1 may be grounded during the read operation.

  Further, for the memory cells C10 and C11 connected to the non-selected word line WL1, since the non-selected word line WL1 is grounded, the cell transistors 4 and 5 of the memory cells C10 and C11 are turned off. Therefore, the sense current Is does not flow through the memory cells C10 and 11.

  Further, the reference current Iref does not flow for the non-selected reference cells R00, R01, R11. First, for the reference cell R11 connected to the selected reference word line WLR1, the unselected read bit line / RBL1 is set to a high impedance state, and the unselected write bit lines WBL1 and / WBL1 are both grounded. The cell transistors 4 and 5 of the reference cell R11 are turned on, but the reference bit Iref does not flow because the read bit line / RBL1 is set to a high impedance state and is electrically disconnected from the read circuit. Note that the unselected read bit line / RBL1 may be grounded during the read operation.

  FIG. 9 is a circuit diagram showing an example of the configuration of the row selection circuit 2 for realizing the above access method. The row selection circuit 2 in FIG. 9 includes a row decoder 21, a word driver 22, a word voltage control unit 23, a reference row decoder 24, and a word driver 25. The row decoder 21 and the word driver 22 function as a word line selection circuit that selects the word line WL. On the other hand, the reference row decoder 24 and the word driver 25 function as a reference word line selection circuit that selects the reference word line WLR. In FIG. 9, actually, a plurality of row decoders 21 and the same number of word drivers 22 as word lines WL are provided (for example, as shown in FIG. 2). 21 and only word drivers 22-0 to 22-3 for driving four word lines WL are shown. FIG. 9 shows only one reference row decoder 24. However, when there are more than four reference word lines WLR, a plurality of reference row decoders 24 may be provided. The configuration of the row decoder 21 in FIG. 9 is the same as the row decoder 21 in FIG. 2, and the configuration of the word voltage control unit 23 in FIG. 9 is the same as the word line pressure control unit 23 in FIG.

  The reference row decoder 24 includes an NMOS transistor M11R and M14R-0 to M14R-3. As the NMOS transistor M11R, a core transistor (that is, a normal withstand voltage MOS transistor) is used. On the other hand, as the NMOS transistors M14R-0 to M14R-3, high breakdown voltage transistors whose gate oxide films are thicker than the core transistors are used.

  Each of the word drivers 25-0 to 25-3 includes an NMOS transistor M15R and PMOS transistors M16R to M18R. As the NMOS transistor M15R and the PMOS transistors M16R to M18R, high breakdown voltage transistors whose gate oxide films are thicker than the core transistors are used.

  Hereinafter, the operation of the row selection circuit 2 in the second embodiment will be described with reference to FIGS. 9, 10A, and 10B. In FIG. 9, control signals X234, X567, and X89 are signals obtained by predecoding an input row address, and their amplitude is Vdd. The control signals X01e0 to X01e3 are signals generated by taking the AND logic of the signal obtained by decoding the lower 2 bits of the row address and the access enable signal.

  The row precharge signals RP0 to RP3 are signals generated from the row precharge signal RP, and the amplitude thereof is Vdh. Here, each row precharge signal RPi is a signal instructing to precharge the node N2i and the node N2iR. Based on the control signal x01ei, the row precharge signal RP, and the write enable signal WE, Generated according to 10B logic. That is, the row precharge signal RPi has the same value as the row precharge signal RP when the control signal x01ei is “1”. On the other hand, when the control signal x01ei is “0”, the row precharge signal RPi is read (that is, the write enable signal WE is “0”) even if the row precharge signal RP is “1”. It is not activated.

  The write enable signal WE is supplied to the word voltage control unit 23. The write enable signal WE is at a high level (Vdh) during a write operation, and is at a low level (0 V) during a read operation.

  In the standby state, the control signals X01e0 to X01e3 are set to a low level (0 V), and the row precharge signals RP0 to RP3 are also set to a low level. As a result, the NMOS transistors M14-0 to M14-3 of the row decoder 21 are set to an off state, and the PMOS transistor M18 of the word drivers 22-0 to 22-3 is set to an on state. That is, the nodes N20 to N23 are precharged to the boost voltage Vdh, and a low level (0 V) is output to the word line WL. The PMOS transistor M17 of the word driver 22 is provided to hold the nodes N20 to N23 at a high level (Vdh), and the W / L ratio (W: gate width, L: gate length) is higher than that of other transistors. Is much smaller.

  On the other hand, for the reference row decoder 24 and the word drivers 25-0 to 25-3, similarly, the NMOS transistors M14R-0 to M14R-3 of the reference row decoder 24 are turned off and the PMOS transistor M18R of the word driver 25 is turned on. Set to That is, the nodes N20R to N23R are precharged to Vdh, and a low level (0 V) is output to the reference word line WLR. The PMOS transistor M17R is provided to hold the node N20R at a high level (Vdh), and its W / L (W: gate width, L: gate length) is much smaller than other transistors.

In the read operation, the write enable signal WE is set to a low level (0 V), and the word voltage control unit 23 supplies the power supply voltage Vdd to the node N3. That is, the word voltage control unit 23 sets the drive voltage V _DRV to the power supply voltage Vdd. Hereinafter, a case where the word line WL0 and the reference word line WLR1 are selected will be described as an example.

In each word driver 22 connected to the word line WL, the row precharge signals RP0 to RP3 are set to a high level (Vdh), and the PMOS transistor M18 is turned off. In the selected row decoder 21, the control signals X234, X567, and X89 are set to the high level (Vdd), and the NMOS transistors M11 to M13 are turned on. Further, when the control signal X01e0 corresponding to the word line WL0 becomes high level (Vdh), the NMOS transistor M14-0 is turned on, and the node N20 transits to low level (0V). At this time, the word driver 22-0, the NMOS transistor M15 is turned off, PMOS transistor M16 is turned on, the driving voltage _{V DRV} node N3 is transmitted to the word line WL0. Here, since the drive voltage _VDRV matches the power supply voltage Vdd, as a result, the word line WL0 is driven to the power supply voltage Vdd.

Similarly, in the word driver 25 connected to the reference word line WLR, since the row precharge signals RP0 to RP3 are at the high level (Vdh), the PMOS transistor M18R is turned off. In the selected reference row decoder 21, the control signal XREF is set to the high level (Vdd), and the NMOS transistor M11R is turned on. Further, when the control signal X01e0 becomes high level (Vdh), the NMOS transistor M14R-1 is turned on, and the node N21R changes to low level (0V). Here, it should be noted that the arrangement of the control signals X01e0 to X01e3 differs between the reference row decoder 24 and the row decoder 21. At this time, NMOS transistors M15R off, since PMOS transistors M16R is turned on, the driving voltage _{V DRV} node N3 is transmitted to the reference word line WLR1. Here, since the drive voltage V _DRV matches the power supply voltage Vdd, as a result, the reference word line WLR1 is driven to the power supply voltage Vdd.

  When the read operation is completed, the control signal X01e0 and the row precharge signals RP0 to RP3 are returned to the low level. As a result, the NMOS transistor M14-0 of the row decoder 21 is turned off, the PMOS transistor M18 of the word driver 22 is turned on, and the node N20 transits to a high level (Vdh). For this reason, the word line WL0 returns to the low level. Similarly, when the control X01e0 is returned to the low level, the NMOS transistor M14R1 of the reference row decoder 24 is turned off, the PMOS transistor M18R of the word driver 25 is turned on, and the node 21R transits to the high level (Vdh). . As a result, the reference word line WLR1 returns to the low level.

In the write operation, the write enable signal WE is set to the high level (Vdh), and the word voltage control unit 23 supplies the boost voltage Vdh to the node N3. That is, the word voltage control unit 23 sets the drive voltage V _DRV to the boost voltage Vdh. Hereinafter, an operation when the word line WL0 is selected will be described.

In the word driver 22-0 corresponding to the word line WL0, the row precharge signal RP0 is at the high level (Vdh), and the PMOS transistor M18 is turned off. In the row decoder 21, the control signals X234, X567, and X89 are set to a high level (Vdd), thereby turning on the NMOS transistors M11 to M13. Further, the control signal X01e0 is set to the high level (Vdh), the NMOS transistor M14-0 is turned on, and the node N20 transitions to the low level (0V). At this time, the NMOS transistor M15 of the word driver 22-0 is turned off, the PMOS transistor M16 is turned on, the driving voltage _{V DRV} node N3 is transmitted to the word line WL0. Here, since the driving voltage _{V DRV} matches the boost voltage Vdh, as a result, the word line WL0 is driven to boosted voltage Vdh.

  On the other hand, in the word line driver 25-0 corresponding to the reference word line WLR, the row precharge signal RP0 is at the high level (Vdh), and the PMOS transistor M18R is turned off. In the reference row decoder 24, since the control signal XREF is set to the low level (Gnd), the NMOS transistor M11R remains off. Therefore, even when the control signal X01e0 is at the high level (Vdh) and the NMOS transistor M14R-1 is turned on, the nodes N20R to N23R remain at the high level (Vdh). Therefore, the reference word lines WLR0 to WLR3 are maintained at the low level (Gnd).

  When the write operation is completed, the control signal X01e0 and the row precharge signal RP0 are returned to the low level. At this time, the NMOS transistor M14-0 of the row decoder 21 is turned off, and the PMOS transistor M18 of the word driver 22-0 is turned on. As a result, the node N20 changes to the high level (Vdh), and the selected word line WL0 is returned to the low level. On the other hand, even if the NMOS transistor M14R-1 of the reference row decoder 24 is turned off and the PMOS transistor M18R of the word line driver 25-0 is turned on, the node N20 remains at the high level (Vdh). The word lines WLR0 to WLR3 are maintained at the low level (Gnd).

  One advantage of the row selection circuit 2 configured as shown in FIG. 9 is that the write operation can be started quickly even when a write command is received during the read operation. In the following, this advantage will be described in detail.

  According to the specification of the write operation of the MRAM, there is a case where it is allowed to perform a write operation to the same address after the read operation in order to make it compatible with an SRAM or the like. In order to perform such an operation at high speed, the selected word line is directly shifted from the power supply voltage Vdd to the boost voltage Vdh without grounding the selected word line (that is, without temporarily deselecting the selected word line). preferable.

The most convenient way to transition without grounding the selected word line from the power supply voltage Vdd to boost voltage Vdh, by switching the driving voltage V _DRV outputted from the word voltage control unit 23 from the power supply voltage Vdd to boost voltage Vdh is there. However, a problem in performing such an operation is that the reference word line WLR selected during the read operation also changes from the power supply voltage Vdd to the boost voltage Vdh. During the write operation, all reference word lines WLR must be set to a low level. In the configuration of the row selection circuit 2 shown in FIG. 9, only the node N2iR connected to the word driver 25-i corresponding to the reference word line WLRi selected during the read operation is selectively precharged to reference word line. WLRi can be deselected. Therefore, it is possible to make a direct transition from the power supply voltage Vdd to the boost voltage Vdh without grounding the selected word line.

  Hereinafter, the operation of the row selection circuit 2 when a write command is received during the read operation will be described with reference to FIGS. 9 and 10C.

During the read operation, the write enable signal WE is set to a low level (0 V), and the word voltage control unit 23 supplies the power supply voltage Vdd to the node N3. That is, the word voltage control unit 23 sets the drive voltage V _DRV to the power supply voltage Vdd. Hereinafter, a case where the word line WL0 and the reference word line WLR1 are selected during a read operation and a write operation performed subsequently will be described as an example.

In the word driver 22 corresponding to the word line WL, the row precharge signals RP0 to RP3 are at a high level (Vdh), and the PMOS transistor M18 is turned off. In the selected row decoder 21, the control signals X234, X567, and X89 are at the high level (Vdd), and the NMOS transistors M11 to M13 are turned on. Further, when the control signal X01e0 becomes high level (Vdh), the NMOS transistor M14-0 is turned on, and the node N20 transits to low level (0V). At this time, NMOS transistor M15 in the word driver 22-0 is turned off, PMOS transistor M16 is turned on, the driving voltage _{V DRV} node N3 is transmitted to the word line WL0. In the read operation, the drive voltage _VDRV is set to the power supply voltage Vdd, and as a result, the word line WL0 is driven to the power supply voltage Vdd.

On the other hand, in the word driver 25 corresponding to the reference word line WLR, the row precharge signals RP0 to RP3 are at the high level (Vdh), and the PMOS transistor M18R is turned off. In the selected reference row decoder 24, the control signal XREF becomes high level (Vdd), and the NMOS transistor M11R is turned on. Further, the control signal X01e0 is set to the high level (Vdh), the NMOS transistor M14R-1 is turned on, and the node N21R transitions to the low level (0V). Here, it should be noted that the arrangement of the control signals X01e0 to X01e3 is different between the reference row decoder 24 and the row decoder 21. At this time, in the word driver 25 - 1, NMOS transistors M15R is off, PMOS transistors M16R is turned on, the driving voltage _{V DRV} node N3 is transmitted to the reference word line WLR1. Since the read operation driving voltage _{V DRV} is set to the power supply voltage Vdd, as a result, the reference word line WLR1 is driven to the power supply voltage Vdd.

When a write command is received during the read operation, the write enable signal WE becomes high level (Vdh), and the word voltage control unit 23 drives the node N3 from the power supply voltage Vdd to the boost voltage Vdh. That is, the drive voltage V _DRV is switched from the power supply voltage Vdd to the boost voltage Vdh. Furthermore, the driving voltage _{V DRV} of the node N3 because transmitted to the word line WL0, as a result, the word line WL0 is driven from the power supply voltage Vdd to boost voltage Vdh.

  On the other hand, for the word driver 25 corresponding to the reference word line WRL, the row precharge signals RP1 to RP3 are set to the low level, and the control signal XREF supplied to the reference row decoder 24 is set to the low level. As a result, the NMOS transistor M11R of the reference row decoder 24 is turned off, the PMOS transistor M18R of the word driver 25-1 is turned on, and the node 21R changes to the high level (Vdh). As a result, the reference word line WLR1 becomes low level. For this reason, the write current Iw is not conducted to the reference cell.

  When the write operation is completed, the control signal X01e0 and the row precharge signal RP0 become low level. At this time, the NMOS transistor M14-0 of the row decoder 21 is turned off, and the PMOS transistor M18 of the word driver 22-0 is turned on. As a result, the node N20 changes to the high level (Vdh), and the word line WL0 becomes the low level.

  In the second embodiment described above, the cell area can be reduced by the word boost technique while ensuring the reliability of the gate oxide film of the cell transistor integrated in the memory cell, as in the first embodiment. I can expect. That is, by driving the word line with the boost voltage Vdh only at the time of writing and driving the word line with the power supply voltage Vdd at the time of reading, the time for applying the excessive voltage to the gate oxide film can be reduced. Therefore, the MRAM according to this embodiment that does not apply an excessive voltage to the gate oxide film of the memory cell at the time of reading can effectively improve the reliability of the gate oxide film.

  Furthermore, according to the second embodiment, when a write command is received during reading, it is possible to shift to a write operation without providing a reset period for a row decoder that selects a memory cell, so that a high-speed operation can be performed. That is, only the word driver corresponding to the reference word line performs the precharge operation, so that it is possible to operate at high speed without requiring a period for raising the selected word line.

  In the second embodiment, the word driver 25 that selects the reference cell is not connected to the word voltage control unit 23, and the power source voltage Vdd is always applied to the transistor (that is, the PMOS transistor M16R) in the output stage of the word driver 25. May be supplied.

(Third embodiment)
11A to 11C are circuit diagrams showing the configuration of the MRAM according to the third embodiment of the present invention. In the third embodiment, a memory cell (spin injection cell) configured to invert the magnetization of the free layer of the magnetoresistive element using spin injection magnetization reversal, that is, to write data, is used. Spin-injection magnetization reversal means that when a spin-polarized current is injected into a ferromagnet, the magnetization is reversed due to the direct interaction between the spin of the conduction electron carrying the current and the magnetic moment of the conductor. It is a phenomenon. An MRAM that performs a write operation by spin-injection magnetization reversal is advantageous for high integration because the memory cell is miniaturized and the write current is reduced.

  Hereinafter, the configuration of the MRAM according to the third embodiment will be described in detail. In the memory array 1, memory cells Cij are arranged in a matrix. Each memory cell Cij includes one cell transistor 4 and a magnetoresistive element 6. In the present embodiment, an MTJ element is used as the magnetoresistive element 6. The memory array 1 further has word lines WL extending in the row direction and bit lines BL and / BL extending in the column direction. The word line WL is connected to the row selection circuit 2, and the bit lines BL and / BL are connected to the column selection circuit 3. 11A to 11C, a large number of memory cells are actually arranged in a matrix in the memory array 1, but only the memory cells C00, C01, C10, and C11 in 2 rows and 2 columns are shown for convenience of explanation.

  Next, access to the selected memory cell in the third embodiment will be described with reference to FIGS. 11A to 11C. In the following description, it is assumed that the memory cell C00 is a selected memory cell. That is, the memory cell C01 is an unselected memory cell at the intersection of the selected row and the unselected column, the memory cell C10 is an unselected memory cell at the intersection of the unselected row and the selected column, and the memory cell C11 is unselected from the unselected row. Unselected memory cells at the intersection of columns.

  FIG. 11A illustrates the state of each signal line in the standby state. In the standby state, all word lines WL and bit lines BL and / BL are grounded.

  On the other hand, FIG. 11B illustrates the state of each signal line in the write operation. In the write operation, the word line WL0 and the bit lines BL0 and / BL0 corresponding to the selected memory cell C00 are selected, whereby the write current Iw flows through the selected memory cell C00.

  Specifically, boost voltage Vdh higher than power supply voltage Vdd is applied to selected word line WL0. At the same time, the power supply voltage Vdd is applied to one of the selected bit lines BL0 and / BL0, and the other is grounded. Which of the selected bit lines BL0 and / BL0 is grounded is determined according to the write data. For example, when the write data is “1”, the bit line / BL0 is grounded, and when it is “0”, the bit line BL0 is grounded.

  As a result, the cell transistor 4 of the memory cell C00 is turned on, and the write current Iw passes from the bit line BL0 through the memory cell C00 to the bit line / BL0 (or from the selected write bit line / WBL0 to the memory cell C00). To the selected write bit line WBL0). The write current Iw directs the magnetization of the free layer of the magnetoresistive element 6 in a desired direction, that is, desired data is written to the magnetoresistive element 6 of the selected memory cell C00.

  On the other hand, the write current Iw does not flow through the unselected memory cells C01, C10, and C11. First, for the non-selected memory cell C01 connected to the selected word line WL0, the cell transistor 4 of the memory cell C01 is turned on, but the potential difference between the words BL1 and / BL1 is zero. Accordingly, the write current Iw does not flow through the non-selected memory cell C01. For the unselected memory cells C10 and C11 connected to the unselected word line WL1, since the word line WL1 is grounded, the cell transistors 4 and 5 of the memory cells C10 and C11 are in the off state. Accordingly, the write Iw does not flow to the memory cells C10 and C11. During the write operation, the unselected words BL1 and / BL1 can be set to a high impedance state.

  Further, FIG. 11C illustrates the state of each signal line in the read operation. During the read operation, unlike the write operation, the power supply voltage Vdd is applied to the selected word line WL0. At the same time, the clamp voltage Vc is applied to one selected bit line / BL0 by a read circuit (not shown), and the other selected bit line BL0 is grounded. As a result, the cell transistor 4 of the selected memory cell C00 is turned on, and the sense current Is flows through the selected memory cell C00 with the clamp voltage Vc applied to the magnetoresistive element 6.

  On the other hand, the sense current Is does not flow for the non-selected memory cells C01, C10, and C11. First, for the non-selected memory cell C01 connected to the selected word line WL0, the non-selected bit line BL1 is set to a high impedance state, and the non-selected bit line / BL1 is grounded. Although the cell transistor 4 of the non-selected memory cell C01 connected to the selected word line WL0 is turned on, the sense line Is flows because the bit line WL1 is set to a high impedance state and is electrically disconnected from the read circuit. Absent. Note that the unselected bit line BL1 may be grounded during the read operation.

  For the memory cells C10 and C11 connected to the non-selected word line WL1, since the non-selected word line WL1 is grounded, the cell transistors 4 of the memory cells C10 and C11 are turned off. Therefore, the sense current Is does not flow through the memory cells C10 and 11.

  As the row selection circuit 2, the same configuration as that of FIG. 2 can be used. A description of the row selection circuit 2 is omitted.

  According to the third embodiment described above, the cell area can be reduced by the word boost technique while ensuring the reliability of the gate oxide film of the cell transistor included in the memory cell. That is, by driving the word line with the boost voltage Vdh only at the time of writing and driving the word line with the power supply voltage Vdd at the time of reading, the time for applying the excessive voltage to the gate oxide film can be reduced. In many applications, the number of times of reading data is larger than that of writing data to the memory. Therefore, the MRAM according to this embodiment that does not apply an excessive voltage to the gate oxide film of the memory cell at the time of reading can effectively improve the reliability of the gate oxide film.

  As a modification of the MRAM of the third embodiment, there is an MRAM having a configuration in which write wirings to which a complementary voltage is applied at the time of writing are arranged at right angles. In this modification, one of the write wirings is connected to the column selection circuit, and the other of the write wirings is connected to the row selection circuit 2. At the time of writing, the row selection circuit 2 is configured to supply the boost voltage Vdh and the ground voltage to the word line, and is configured to supply the power supply voltage Vdd or the ground voltage to the write wiring connected thereto. . Therefore, in this modification, the row selection circuit 2 needs to be configured to be able to output three voltages. One method for realizing such an operation is to add a write row decoder and a write word driver to the row selection circuit 2 of the first embodiment in addition to the row decoder 21 and the word driver 22. The word driver 22 is selected by the row decoder 21 using a selection signal whose amplitude is equal to the boost voltage Vdh, while the write word driver connected to the write wiring is a write row decoder using a selection signal whose amplitude is equal to the power supply voltage Vdd. Is selected. Since the amplitude of the output of the row decoder 21 is Vdh and the amplitude of the output of the write row decoder is Vdd, these row decoders cannot be shared and the circuit area increases.

  On the other hand, in the MRAM configured as shown in FIGS. 11A to 11C, the row selection circuit 2 and the column selection circuit 3 are used by using two write bit lines WBLi and / WBLi in parallel as write wirings to which complementary voltages are applied during writing. Thus, the circuit area can be reduced. That is, at the time of writing, the row selection circuit 2 need only supply the boost voltage Vdh or the ground potential Gnd to the word line, and does not need to supply the power supply voltage Vdd. In the column selection circuit 3, the write driver that supplies a voltage to one write bit line WBLi and the write driver that supplies a voltage to the other write bit line WBLi both receive a selection signal whose amplitude is the power supply voltage Vdd. And can be selected by a column decoder (not shown). Therefore, a part of the column decoder that selects these write drivers can be shared. As a result, the area of the row selection circuit 2 and the column selection circuit 3 can be reduced as compared with the above-described modification.

(Fourth embodiment)
FIG. 12 is a circuit diagram showing a configuration of the row selection circuit 2 in the fourth embodiment of the present invention. In the fourth embodiment, the row selection circuit 2 supplies the boost voltage Vdh to the word line during the write operation, and supplies the word line with a voltage lower than the boost voltage Vdh by the threshold voltage of the NMOS transistor during the read operation. Configured. In the present embodiment, such an operation is realized by using a PMOS transistor as a transistor for pulling up the word line WL during a write operation, and using an NMOS transistor as a transistor for pulling up the word line WL during a read operation. ing. Hereinafter, the row selection circuit 2 in the fourth embodiment will be described in detail.

  The row selection circuit 2 according to the fourth embodiment includes a row decoder 21, a word driver 22, and a word voltage control unit 23. In FIG. 12, actually, a plurality of row decoders 21 and the same number of word drivers 22 as word lines WL are provided (for example, as shown in FIG. 2). 21 and only word drivers 22-0 to 22-3 for driving four word lines WL are shown.

  The row decoder 21 includes NMOS transistors M11 to M13 and M14-0 to M14-3. Each word driver 22-i includes NMOS transistors M15, M19, and M20 and PMOS transistors M16 to M18 and M21. The word voltage control unit 23 includes a PMOS transistor M22.

  For the row decoder 21, the word driver 22-i, and the word voltage control unit 23, two types of transistors, a normal withstand voltage transistor (core transistor) and a high withstand voltage transistor, are used. Specifically, core transistors are used as the NMOS transistors M11 to M13 of the row decoder 21, and high voltage transistors are used as the NMOS transistors M14-0 to M14-3. Further, high-breakdown-voltage transistors are used as all the MOS transistors M15 and PMOS transistors M16 to M18 of the word driver 22-i and as the PMOS transistor M22 of the word voltage control unit 23.

  The operation of the row selection circuit 2 according to the fourth embodiment will be described with reference to FIGS. Hereinafter, the operation of the row selection circuit 2 will be described assuming that the word line WL0 is selected in the read operation and the write operation. The control signals X234, X567, and X89 are signals obtained by predecoding the input row address, and their amplitude is Vdd. Here, the control signals X01e0 to X01e3 are signals obtained by ANDing the signal obtained by decoding the lower 2 bits of the row address and the access enable signal. The symbol “RP” indicates a row precharge signal, and the amplitude of the row precharge signal RP is Vdh. The low precharge signal RP is a signal for instructing to precharge the nodes N20 to N23 to a high level (Vdh). The write enable signal WEB is supplied to the word voltage control unit 23. The write enable signal WEB is a low active signal, and is set to a high level (Vdh) during a read operation and set to a low level (0 V) during a write operation.

  In the standby state, the control signals X01e0 to X01e3 and the row precharge signal RP are set to a low level (0 V), the NMOS transistors M14-0 to M14-3 are set to an off state, and the PMOS transistor M18 is set to an on state. . That is, the nodes N20 to N23 are high precharged to the boost voltage Vdh, and the word line WL0 is set to a low level (0 V). The PMOS transistor M17 is provided to hold the nodes N20 to N23 at a high level (Vdh), and its W / L (W: gate width, L: gate length) is much smaller than other transistors.

  During the read operation, the write enable signal WEB is set to a high level (Vdh), and the PMOS transistor M22 of the word voltage control unit 23 is turned off. As a result, the node N3 enters a high impedance state. Further, the low precharge signal RP becomes high level (Vdh), and the PMOS transistor M18 is turned off. In the selected row decoder 21, the control signals X234, X567, and X89 are set to the high level (Vdd), and the NMOS transistors M11 to M13 are set to the on state. Further, when the control signal X01e0 is set to the high level (Vdh) and the NMOS transistor M14-0 is set to the on state, the node N20 transitions to the low level (0V). At this time, the NMOS transistor M15 of the word driver 22-0 is turned off and the PMOS transistor M16 is turned on. However, since the node N3 is in a high impedance state, even if the PMOS transistor M16 is turned on, the potential of the selected word line WL0 is not affected. In response to the transition of the node N20 to the low level, the NMOS transistor M20 is turned off, the PMOS transistor M21 is turned on, and the NMOS transistor M19 is turned on. When the NMOS transistor M19 is turned on, the word line WL0 is connected to the power supply line having the boost voltage Vdh. However, due to the voltage drop in the NMOS transistor M19, the word line WL0 becomes lower than the boost voltage Vdh by the threshold voltage of the NMOS transistor M19.

  When the read operation is completed, the control signal X01e0 and the row precharge signal RP are returned to the low level. As a result, the NMOS transistor M14-0 is turned off, the PMOS transistor M18 is turned on, the node N20 transits to the high level (Vdh), and the word line WL0 returns to the low level.

  During the write operation, the write enable signal WEB is set to a low level (0 V). As a result, the PMOS transistor M22 of the word voltage control unit 23 is turned on, and the boost voltage Vdh is supplied to the node N3. In each word driver 22, the row precharge signal RP becomes high level (Vdh), and the PMOS transistor M18 is turned off. Further, in the selected row decoder 21, the control signals X234, X567, and X89 are set to the high level (Vdd), and the NMOS transistors M11 to M13 are turned on. Further, when the control signal X01e becomes high level (Vdh), the NMOS transistor M14-0 is turned on, and the node N20 transits to low level (0V). As a result, the NMOS transistor M15 is turned off and the PMOS transistor M16 is turned on, the boost voltage Vdh at the node N3 is transmitted to the word line WL0, and the word line WL0 is driven to the boost voltage Vdh. At this time, the NMOS transistor M19 is also turned on, contributing to rapidly charging the word line WL0 when the word line WL0 is driven.

  When the write operation is completed, the control signal X01e0 and the row precharge signal RP are returned to the low level. As a result, the NMOS transistor M14-0 is turned off, the PMOS transistor M18 is turned on, the node N20 transits to the high level (Vdh), and the word line WL0 returns to the low level.

  Even when the row selection circuit 2 of the fourth embodiment described above is used, the cell area can be reduced by the word boost technique while ensuring the reliability of the gate oxide film of the cell transistor of the memory cell. That is, the word line is driven with the boost voltage Vdh only at the time of writing, and the word line is driven with a voltage lower than the boost voltage Vdh by the threshold value of the transistor at the time of reading, thereby reducing the time during which an excessive voltage is applied to the gate oxide film. be able to.

(Fifth embodiment)
FIG. 14 is a circuit diagram showing a configuration of the row selection circuit 2 in the fifth embodiment of the present invention. Similarly to the other embodiments, the row selection circuit 2 of the present embodiment is also configured to supply the boost voltage Vdh to the selected word line at the time of writing and supply the power supply voltage Vdd to the selected word line at the time of reading.

  The row selection circuit 2 in FIG. 14 includes a row decoder 21, a word driver 22, and a word voltage control unit 23. In FIG. 14, actually, a plurality of row decoders 21 and the same number of word drivers 22 as word lines WL are provided (for example, as shown in FIG. 2). 21 and only the word driver 22-0 for driving one word line WL0 are shown.

  In the present embodiment, the row decoder 21 is configured by a NAND circuit, and each word driver 22 is configured by NMOS transistors M10, M12, M13, M14, and a PMOS transistor M11. The word voltage control unit 23 includes an NMOS transistor M15, PMOS transistors M16 and M17, NAND circuits ND1 and ND2, and inverters INV1 and INV2.

  The NAND circuit of the row decoder 21 is composed of a (normal withstand voltage) core transistor. Further, as the NMOS transistor M10 and NMOS transistor M11 of the word driver 22, core transistors are used. On the other hand, as the NMOS transistors M12 to M14 of the word driver 22, and the NMOS transistors M15 and PMOS transistors M16 and M17 of the word voltage control unit 23, high breakdown voltage transistors whose gate oxide films are thicker than the core transistors are used. Furthermore, the inverters INV1 and INV2 and the NAND circuits ND1 and ND2 of the word voltage control unit 23 are composed of high voltage transistors.

  Subsequently, the operation of the row selection circuit 2 according to the fifth embodiment will be described with reference to FIGS. 14 and 15. Hereinafter, the operation of the row selection circuit 2 will be described assuming that the word line WL0 is selected in the read operation and the write operation.

The difference of the operation of the row selection circuit 2 in the fifth embodiment from the first, second, and fourth embodiments is in the transition of the voltage level of the drive voltage V _DRV output from the word voltage control unit 23. is there. In the first, second, and fourth embodiments, the drive voltage V _DRV output from the word voltage control unit 23 is always maintained at the power supply voltage Vdd or the boost voltage Vdh, and does not become low level. On the other hand, in the fifth embodiment, the drive voltage V _DRV output from the word voltage control unit 23 is pulled up from the low level to the power supply voltage Vdd when the read operation is started, and the write operation is started. When pulled up, it is pulled up from the low level to the boost voltage Vdh. When the read operation and the write operation are completed, the drive voltage V _DRV output from the word voltage control unit 23 is returned to the low level. Details of the operation of the row selection circuit 2 in the fifth embodiment will be described below.

  Control signals X234, X567, and X89 are signals obtained by predecoding the input row address. The control signal X01e is a signal obtained by ANDing the signal obtained by decoding the lower 2 bits of the row address and the access enable signal. The amplitude of the control signal X01e is Vdh, and the other amplitude is Vdd. The write enable signal WE is supplied to the word voltage control unit 23. The write enable signal WE is set to a high level (Vdh) during a write operation, and is set to a low level (0 V) during a read operation.

  In the standby state, the control signal X01e is set to a low level (0 V), whereby the NMOS transistor M15 of the word voltage control unit 23 is turned on and the PMOS transistors M16 and M17 are turned off. That is, the node N3 is at a low level. Further, the control signals X234, X567, and X89 are at a low level (0 V), and the NMOS transistor M13 is set to an on state and the NMOS transistor M14 is set to an off state. As a result, a low level (0 V) is output to all the word lines WL.

  In the read operation, in the selected row decoder 21, the control signals X234, X567, and X89 are at the high level (Vdd), the node N1 is at the low level (0V), and the node N2 is at the high level (Vdd). Further, the write enable signal is set to a low level (0V) and the control signal X01e is set to a high level (Vdh), whereby the NMOS transistor M15 and the PMOS transistor M16 of the word voltage control unit 23 are turned off, and the PMOS transistor M17 is turned on. Turns on. As a result, the node N3 transitions from the low level to the power supply voltage Vdd. At this time, the voltage level of the gate of the NMOS transistor M14 of the word driver 22-0 is pushed up by the gate-drain capacitance of the NMOS transistor M14, and the same voltage as the power supply voltage Vdd is supplied to the word line WL0.

  When the read operation ends, the control signal X01e is set to a low level. At this time, the NMOS transistor M15 of the word voltage control unit 23 is turned on, the PMOS transistors M16 and M17 are turned off, the node N3 transitions to the low level (0 V), and the word line WL0 becomes the low level.

  During the write operation, in the selected row decoder 21, the control signals X234, X567, and X89 are at the high level (Vdd), the node N1 is at the low level (0 V), and the node N2 is at the high level (Vdd). Further, the write enable signal WE is set to a high level (Vdh), and the control signal X01e is set to a high level (Vdh). As a result, the NMOS transistor M15 and the PMOS transistor M17 of the word voltage control unit 23 are turned off, the PMOS transistor M16 is turned on, and the node N3 transits to the boost voltage Vdh. At this time, the voltage level of the gate of the NMOS transistor M14 of the word driver 22-0 is pushed up by the gate-drain capacitance of the NMOS transistor M14, and the boost voltage Vdh is supplied to the word line WL0.

  When the write operation is completed, the control signal X01e becomes low level. At this time, the NMOS transistor M15 of the word voltage control unit 23 is turned on, the PMOS transistors M16 and M17 are turned off, the node N3 transitions to the low level (0 V), and the word line WL0 becomes the low level.

  Even when the row selection circuit 2 of the fifth embodiment described above is used, the cell area can be reduced by the word boost effect while ensuring the reliability of the gate oxide film of the cell transistor of the memory cell. That is, by driving the word line with the boost voltage Vdh only at the time of writing and driving the word line with the power supply voltage Vdd at the time of reading, the time for applying the excessive voltage to the gate oxide film can be reduced.

  Although specific embodiments of the present invention have been described above, it is obvious to those skilled in the art that various modifications can be made within the scope of the technical idea of the present invention. It should be noted that the above embodiments can be implemented in combination as long as there is no contradiction.

FIG. 1A is a circuit diagram of the MRAM according to the first embodiment of the present invention, and shows the potential of each signal line in the standby state. FIG. 1B is a circuit diagram of the MRAM according to the first embodiment, and shows the potential of each signal line during the write operation. FIG. 1C is a circuit diagram of the MRAM according to the first embodiment, and shows the potential of each signal line during a read operation. FIG. 2 is a block diagram illustrating a configuration of the row selection circuit according to the first embodiment. FIG. 3 is a circuit diagram showing details of the configuration of the row selection circuit of the first embodiment. FIG. 4 is a timing chart showing the operation of the row selection circuit of the first embodiment. FIG. 5 is a block diagram showing another configuration of the row selection circuit of the first embodiment. FIG. 6 is a block diagram showing still another configuration of the row selection circuit of the first embodiment. FIG. 7 is a block diagram showing still another configuration of the row selection circuit of the first embodiment. FIG. 8A is a circuit diagram of the MRAM according to the second embodiment of the present invention, and shows the potential of each signal line in the standby state. FIG. 8B is a circuit diagram of the MRAM according to the second embodiment, and shows the potential of each signal line during the write operation. FIG. 8C is a circuit diagram of the MRAM according to the second embodiment, and shows the potential of each signal line during the read operation. FIG. 9 is a circuit diagram showing a configuration of the row selection circuit of the second embodiment. FIG. 10A is a timing chart illustrating the operation of the row selection circuit according to the second embodiment. FIG. 10B is a truth table showing the operation of the row selection circuit of the second embodiment. FIG. 10C is a timing chart illustrating the operation of the row selection circuit according to the second embodiment. FIG. 11A is a circuit diagram of the MRAM according to the third embodiment of the present invention, and shows the potential of each signal line in the standby state. FIG. 11B is a circuit diagram of the MRAM according to the third embodiment, and shows the potential of each signal line during the write operation. FIG. 11C is a circuit diagram of the MRAM according to the third embodiment, and shows the potential of each signal line during the read operation. FIG. 12 is a circuit diagram showing a configuration of a row selection circuit in the fourth embodiment of the present invention. FIG. 13 is a timing chart showing the operation of the row selection circuit of the fourth embodiment. FIG. 14 is a circuit diagram showing a configuration of a row selection circuit in the fifth embodiment of the present invention. FIG. 15 is a timing chart showing the operation of the row selection circuit of the fifth embodiment. FIG. 16A is a circuit diagram showing a typical configuration of an MRAM that employs 2T1MTJ cells, and shows the potential of each signal line in a standby state. FIG. 16B is a circuit diagram showing a typical configuration of an MRAM that employs 2T1MTJ cells, and shows the potential of each signal line during a write operation. FIG. 16C is a circuit diagram showing a typical configuration of an MRAM that employs 2T1MTJ cells, and shows the potential of each signal line during a read operation. FIG. 17 is a graph showing the advantages of the word boost technique.

Explanation of symbols

1: Memory array 2: Row selection circuit 3: Column selection circuit 4, 5: MOS transistor 6: Magnetoresistive element 11: Sub memory array 12: Main row selection circuit 13: Sub row selection circuit 21: Row decoder 22: Word driver 23: Word voltage control unit 24: reference row decoder 25: word driver

Claims (13)

Multiple word lines,
A plurality of memory cells each including a magnetoresistive element;
A row selection circuit,
In a read operation, the row selection circuit supplies a first voltage to a word line corresponding to a selected memory cell selected from the plurality of memory cells,
In the write operation, the row selection circuit supplies a second voltage higher than the first voltage to the word line corresponding to the selected memory cell selected from the plurality of memory cells ,
When a write operation is performed subsequent to a read operation without changing the address of the selected memory cell, the row selection circuit starts from the first voltage without grounding the word line connected to the selected memory cell. A magnetic random access memory configured to transition to a second voltage . The magnetic random access memory according to claim 1,
Furthermore,
A column selection circuit;
A plurality of first bit lines and a plurality of second bit lines provided to extend in a direction intersecting with the plurality of word lines;
The memory cell is provided at an intersection of the word line, the first bit line, and the second bit line,
In the write operation, the column selection circuit supplies one of a third voltage and a ground voltage to the first bit line connected to the selected memory cell selected from the plurality of memory cells according to the write data. A magnetic random access memory for supplying the other of the third voltage and the ground voltage to a second bit line connected to a selected memory cell. The magnetic random access memory according to claim 2,
And a plurality of read bit lines provided to extend in a direction intersecting with the plurality of word lines,
Each of the plurality of memory cells further comprises a first transistor and a second transistor,
The first transistor has a gate connected to a corresponding word line, one source / drain connected to a corresponding first bit line, and the other source / drain connected to one end of the magnetoresistive element and the second transistor. Connected to one source / drain,
The second transistor has a gate connected to the corresponding word line, and the other source / drain connected to the corresponding second bit line,
A magnetic random access memory in which the other end of the magnetoresistive element is connected to a corresponding read bit line. The magnetic random access memory according to claim 2,
Each of the plurality of memory cells further comprises a first transistor;
The first transistor has a gate connected to a corresponding word line, one source / drain connected to a corresponding first bit line, and the other source / drain connected to a magnetoresistive element,
A magnetic random access memory in which the other end of the magnetoresistive element is connected to a corresponding second bit line. The magnetic random access memory according to any one of claims 1 to 4,
Furthermore, a plurality of sub-row selection circuits and a plurality of sub-word lines are provided,
The length of the sub word line is shorter than that of the word line,
In a read operation, the sub row selection circuit supplies the first voltage to a sub word line corresponding to a selected memory cell selected from the plurality of memory cells,
In a write operation, the sub-row selection circuit supplies the second voltage to a sub-word line corresponding to a selected memory cell selected from the plurality of memory cells. Magnetic random access memory. The magnetic random access memory according to any one of claims 1 to 5,
Furthermore, a plurality of reference cells are provided,
In the read operation, the row selection circuit supplies a first voltage to a word line connected to a selected reference cell selected from the plurality of reference cells,
In a write operation, the row selection circuit grounds a word line connected to the plurality of reference cells. Magnetic random access memory. The magnetic random access memory according to any one of claims 1 to 6 ,
The row selection circuit includes:
A word voltage controller;
A first word driver connected to a word line connected to the plurality of memory cells;
A row decoder for selecting the first word driver;
In a read operation, the word voltage control unit supplies the first voltage to the first word driver, and the first word driver selected by the row decoder passes through a first transistor of the first word driver. Supplying the first voltage to a word line connected to the selected memory cell;
In the write operation, the word voltage controller supplies the second voltage to the first word driver, and the first word driver selected by the row decoder passes through the first transistor of the first word driver. And supplying the second voltage to a word line connected to the selected memory cell. The magnetic random access memory according to claim 7 ,
The row selection circuit further includes:
A second word driver connected to a word line connected to the plurality of reference cells;
A reference row decoder for selecting the second word driver;
In a read operation, the word voltage control unit supplies the first voltage to the second word driver, and the second word driver selected by the reference row decoder passes through a second transistor of the second word driver. Supplying the first voltage to the word line,
In a write operation, the second word driver supplies a ground potential to a word line via a third transistor of the second word driver. Magnetic random access memory. Multiple word lines,
A plurality of memory cells each including a magnetoresistive element;
A row selection circuit;
Multiple reference cells
And
In a read operation, the row selection circuit supplies a first voltage to a word line corresponding to a selected memory cell selected from the plurality of memory cells,
In the write operation, the row selection circuit supplies a second voltage higher than the first voltage to the word line corresponding to the selected memory cell selected from the plurality of memory cells,
In the read operation, the row selection circuit supplies the first voltage to a word line connected to a selected reference cell selected from the plurality of reference cells,
In a write operation, the row selection circuit grounds a word line connected to the plurality of reference cells,
The plurality of word lines are divided into a plurality of groups according to row addresses,
The first group including the word line connected to the selected memory cell is different from the second group including the word line connected to the selected reference cell.
A first precharge signal for instructing precharge of the first word line driver is supplied to the first word drivers connected to the word lines of the first group;
A second precharge signal instructing precharge of the second word line driver is supplied to the second word driver connected to the second group of word lines;
In the read operation, the first precharge signal and the second precharge signal are deactivated,
In the write operation, the first precharge signal is deactivated and the second precharge signal is activated. Magnetic random access memory. Multiple word lines,
A plurality of memory cells each including a magnetoresistive element;
Row selection circuit
And
In a read operation, the row selection circuit supplies a first voltage to a word line corresponding to a selected memory cell selected from the plurality of memory cells,
In the write operation, the row selection circuit supplies a second voltage higher than the first voltage to the word line corresponding to the selected memory cell selected from the plurality of memory cells,
The row selection circuit includes a word driver,
During a read operation, the word driver supplies the first voltage, which is lower than the second voltage by the threshold voltage of the NMOS transistor, to the word line connected to the selected memory cell via the NMOS transistor included in the word driver. And
In a write operation, the word driver supplies the second voltage to a word line connected to the selected memory cell via a PMOS transistor included in the word driver. Magnetic random access memory. The magnetic random access memory according to any one of claims 1 to 6 ,
The row selection circuit includes:
A word voltage supply unit ;
With a word driver,
In the standby state, the word voltage supply unit supplies a low level voltage to the word driver and the word driver sets the plurality of word lines to a low level,
In a read operation, the word voltage supply unit supplies the first voltage to the word driver, and the word driver supplies the first voltage to a word line connected to the selected memory cell via a first transistor. And
In a write operation, the word voltage supply unit supplies the second voltage to the word driver, and the word driver applies to the word line that connects the second voltage to the selected memory cell via the first transistor. Supply magnetic random access memory. Multiple word lines,
A plurality of memory cells each including a magnetoresistive element ;
Row selection circuit
And
In a read operation, the row selection circuit supplies a first voltage to a word line corresponding to a selected memory cell selected from the plurality of memory cells,
In the write operation, the row selection circuit supplies a second voltage higher than the first voltage to the word line corresponding to the selected memory cell selected from the plurality of memory cells,
The row selection circuit includes a MOS transistor having a gate oxide film thicker than a MOS transistor integrated in the memory cell. Multiple word lines,
A plurality of memory cells each including a magnetoresistive element;
A row selection circuit;
A plurality of sub-row selection circuits;
Multiple sub word lines
And
In a read operation, the row selection circuit supplies a first voltage to a word line corresponding to a selected memory cell selected from the plurality of memory cells,
In the write operation, the row selection circuit supplies a second voltage higher than the first voltage to the word line corresponding to the selected memory cell selected from the plurality of memory cells,
The length of the sub word line is shorter than that of the word line,
In a read operation, the sub row selection circuit supplies the first voltage to a sub word line corresponding to a selected memory cell selected from the plurality of memory cells,
In a write operation, the sub row selection circuit supplies the second voltage to a sub word line corresponding to a selected memory cell selected from the plurality of memory cells,
The sub-row selection circuit includes a transistor in which a gate oxide film is thicker than a cell transistor. Magnetic random access memory.

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