JP2003297071A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device which can rewrite data with smaller current consumption than a case of feeding a rewrite-current each bit line. <P>SOLUTION: This memory device is provided with a bit line BL0 and a bit line BL1 having a current path independently of the bit line BL0, write-in current paths of the bit line BL0 and the bit line BL1 are made common. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a memory device such as a magnetic memory device including a memory element exhibiting a ferromagnetic tunnel effect.

[0002]

2. Description of the Related Art Conventionally, an MRAM (Magnetic R), which is a non-volatile memory for recording data using magnetism
and Anom Access Memory) is known. About this MRAM, NIKKEI ELE
CTRONICS 1999.11.15 (no. 75
7) pp. 49-56 and the like.

7 and 8 are schematic views for explaining the structure of the memory element of the MRAM disclosed in the above-mentioned document. Referring to FIG. 7, a storage element 1 of the conventional MRAM.
10 includes a ferromagnetic layer 101, a ferromagnetic layer 103, and a non-magnetic layer 102 arranged between the ferromagnetic layers 101 and 103.

The ferromagnetic layer 101 is less likely to be inverted than the ferromagnetic layer 103. Here, ferromagnetism refers to magnetism when magnetic atoms or free atoms of metals form spontaneous magnetization by aligning magnetic moments in parallel by positive exchange interaction, and a substance exhibiting this ferromagnetism. Is called a ferromagnet.
The ferromagnetic layers 101 and 103 are made of this ferromagnetic material. Further, conventionally, G using a metal as the non-magnetic layer 102 has been used.
MR (Giant Magneto Resistan)
ce) membranes are used. In recent years, the non-magnetic layer 102
TMR (Tunneling M
An Agneto Resistance) membrane has been developed. This TMR film has the advantage that it has a higher resistance than the GMR film. Specifically, the MR ratio (rate of change in resistance) of the GMR film is in the 10% range, while the MR ratio of the TMR film is
The ratio (rate of change in resistance) is 20% or more. In addition, this TM
Hereinafter, the memory element 110 including the R film will be referred to as the TMR element 11
0.

Next, the storage principle of the MRAM using the conventional TMR element 110 will be described with reference to FIGS. 7 and 8. First, as shown in FIG. 7, two ferromagnetic layers 1
The state in which the magnetizations of 01 and 103 are in the same direction (parallel) corresponds to the data “0”. Also, as shown in FIG.
The state in which the magnetizations of the two ferromagnetic layers 101 and 103 are in opposite directions (antiparallel) corresponds to data “1”. Where TM
The R element 110 has a resistance (R ₀ ) when the magnetization directions are parallel.
Has a property that the resistance (R ₁ ) is large when is small and antiparallel. TM depending on whether this magnetization direction is parallel or antiparallel
By utilizing the characteristic that the resistance of the R element 110 is different, it is determined whether it is “0” or “1”.

FIG. 9 shows an M in the case where a memory cell is composed of one conventional TMR element and one transistor.
It is the block diagram which showed the whole RAM structure. The configuration of the conventional MRAM 150 will be described below with reference to FIG.

The memory cell array 151 is formed by arranging a plurality of memory cells 120 in a matrix form (in FIG. 9, only four memory cells 120 are shown to simplify the drawing). One memory cell 120
Is composed of one TMR element 110 and one NMOS transistor 111.

In each memory cell 120 arranged in the row direction, the gate of the NMOS transistor 111 is connected to the common read word lines RWL _{1 to} RWL _n . In each memory cell 120 arranged in the row direction, the rewriting word lines WWL _{1 to} WWL _n are arranged on _one ferromagnetic layer of the TMR element 110.

In each memory cell 120 arranged in the column direction, one ferromagnetic layer of the TMR element 110 is connected to the common bit lines BL _{1 to} BL _n .

Read word lines RWL _{1 to} RWL
_n is connected to the row decoder 152 and each bit line BL ₁
To BL _n is connected to the column decoder 153.

A row address and a column address designated from the outside are input to the address pin 154. The row address and the column address are transferred from the address pin 154 to the address latch 155. Of the addresses latched by the address latch 155, the row address is transferred to the row decoder 152 via the address buffer 156, and the column address is transferred to the column decoder 153 via the address buffer 156.

The row decoder 152 selects the read word line RWL corresponding to the row address latched by the address latch 155 among the read word lines RWL _{1 to} RWL _n , and also each rewrite word line W.
Of WL _{1 to} WWL _n , the rewriting word line WW corresponding to the row address latched by the address latch 155.
Select L. Further, the row decoder 152, based on the signal from the voltage control circuit 157, the potentials of the read word lines RWL _{1 to} RWL _n and the rewrite word lines W.
The potentials of WL _{1 to} WWL _n are controlled.

The column decoder 153 has each bit line BL ₁
Of to BL _n, as well as select a bit line corresponding to the latched column address in the address latch 155, on the basis of a signal from the voltage control circuit 158, controls the potential of the bit lines BL ₁ to BL _n.

Data designated externally is input to the data pin 159. The data is transferred from the data pin 159 to the column decoder 153 via the input buffer 160. The column decoder 153 is provided for each bit line BL.
The potentials of _{1 to} BL _n are controlled according to the data.

The data read from any memory cell 120 is transferred from each bit line BL _{1 to} BL _n to the sense amplifier group 161 via the column decoder 153. The sense amplifier group 161 is a current sense amplifier. The data determined by the sense amplifier group 161 is the output buffer 1
It is output from 62 via the data pin 159 to the outside.

The above-mentioned circuits (152-162)
The operation of is controlled by the control core circuit 163.

Next, the conventional MR constructed as described above is used.
The write (rewrite) operation and read operation of the AM 150 will be described.

(Write Operation) In this write operation, the selected rewriting word line WWL and bit line B are selected.
An orthogonal current is applied to L. As a result, the TM at the intersection of the bit line BL and the rewriting word line WWL
Only the R element 110 can be rewritten. Specifically, each current flowing through the rewriting word line WWL and the bit line BL generates a magnetic field, and the sum of the two magnetic fields (combined magnetic field) acts on the TMR element 110. The direction of the magnetization of the TMR element 110 is reversed by this synthetic magnetic field, and for example,
It changes from "1" to "0".

The TMR elements 110 other than the intersections are
There is a type in which no current flows at all and a type in which current flows only in one direction. In the TMR element 110 in which no current flows, no magnetic field is generated, and therefore the direction of magnetization does not change. A magnetic field is generated in the TMR element 110 in which only a current flows in one direction, but its magnitude is insufficient for reversing the magnetization. Therefore, in the TMR element 110 in which only current in one direction flows, the direction of magnetization does not change.

As described above, by passing a current through the bit line BL corresponding to the selected address and the rewriting word line WWL, the position is located at the intersection of the selected bit line BL and the rewriting word line WWL. It is possible to write the magnetization direction of the TMR element 110 to the direction shown in FIG. 7 or 8. As a result, data "0"
Alternatively, "1" can be written.

(Read Operation) When reading the data written as described above, a voltage is applied to the read word line RWL to make the NMOS transistor 111 conductive. In this state, it is determined whether the current value flowing through the bit line BL is larger or smaller than the current value of the reference to determine "1" or "0".

In this case, in the case of the data "0" shown in FIG. 7, since the magnetization directions are parallel, the resistance value (R ₀ ) is small. Therefore, the current value flowing through the bit line BL is larger than the reference current value. On the other hand, in the case of the data “1” shown in FIG. 8, since the magnetization directions are antiparallel, the resistance value (R ₁ ) becomes larger than that in the case shown in FIG. 7. Therefore, the value of the current flowing through the bit line BL is
It is less than the reference current value.

[0023]

DISCLOSURE OF THE INVENTION The above-mentioned conventional MRA
In M150, an orthogonal current is passed through the selected rewriting word line WWL and bit line BL during the data write operation. In this case, if the TMR element 110 is miniaturized, the direction of magnetization becomes difficult to be reversed, so that it is difficult to rewrite data unless the current for writing is increased. Furthermore, conventional M
In the RAM 150, the selected rewriting word line WW
When rewriting cells connected to L at the same time, it is necessary to pass a current through each bit line, and therefore, a current required for each cell × a current equal to the number of bit lines is required. Therefore, there is a problem that a very large current is required.

The selected rewriting word line WW
Even when the cells connected to L are continuously rewritten, the rewriting current needs to be equal to the rewriting cycle × the number of bit lines, so that there is a problem that a large current is required.

The present invention has been made to solve the above problems, and one of the objects of the present invention is to:
It is an object of the present invention to provide a memory device capable of rewriting data with less current consumption as compared with a case where a rewriting current is supplied to each bit line.

Another object of the present invention is to provide a memory device as described above, wherein the current path of the first bit line and the second bit line can be easily formed.
It is to connect with the current path of the bit line.

[0027]

In order to achieve the above object, a memory device according to a first aspect of the present invention comprises a first bit line and a first bit line.
A second bit line having a current path independent of the bit line is provided, and the write current path for the first bit line and the second bit line is shared.

According to the first aspect of the present invention, as described above, the second bit line has the first bit line and the current path independent of the first bit line.
By sharing the write current path with the bit line, compared to the case where a rewrite current is passed for each bit line,
Data can be rewritten with low current consumption.

According to another aspect of the storage device of the present invention, a first bit line, a first pair line paired with the first bit line, a second bit line, and a second pair line paired with the second bit line. , The current path between the first bit line and the second bit line is connected by connecting either the first bit line or the first pair line and the second bit line or the second pair line at the time of writing. And a current path control circuit. In addition,
The pair line in the present invention includes an inverted bit line forming a bit line pair with a bit line, and a simple wiring connected to the bit line.

In the second aspect, as described above, by connecting either the first bit line or the first pair line with the second bit line or the second pair line at the time of writing, the first bit line is connected. By providing the current path control circuit that connects the current path between the line and the second bit line, the rewriting current can be passed through the first and second bit lines as one current path during writing. As a result, it is possible to rewrite data with less current consumption as compared with the case where a rewrite current is supplied to each bit line.

According to a third aspect of the present invention, in a storage device according to the first or second aspect, a first latch circuit for storing write data for the first bit line and a write data for the second bit line are stored. A second latch circuit is further provided, and based on outputs of the first latch circuit and the second latch circuit, a current path of the first bit line and a second bit line.
Connect to the current path of the bit line. According to this structure, the current path of the first bit line and the current path of the second bit line can be easily connected by using the first latch circuit and the second latch circuit.

According to a fourth aspect of the present invention, in the memory device according to the second or third aspect, the current path control circuit operates based on the outputs of the first latch circuit and the second latch circuit, and the output of the logic circuit. And a switching element that is on / off controlled based on the above. With this configuration, the on / off control of the switching element facilitates
The current path of the first bit line and the current path of the second bit line can be connected.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the overall configuration of an MRAM according to the first embodiment of the present invention. FIG. 2 shows an MRA according to the first embodiment shown in FIG.
6 is a circuit diagram showing details of a memory cell portion of M. FIG. Figure 3
2 is a circuit diagram showing a memory cell array unit and a current path control circuit unit of the MRAM according to the first embodiment shown in FIG. 1.

First, the overall configuration of the MRAM of the first embodiment will be described with reference to FIGS. The MRAM according to the first embodiment is mainly composed of a matrix-shaped memory cell array 51. Memory cell array 5
1 is composed of memory cells 52 arranged in a row direction and a column direction. The memory cell 52 stores 1-bit data, which is the minimum unit of storage.

In the MRAM of the first embodiment, one memory cell 52 has two TMR elements 4a and 4b and two TMR elements 4a and 4b.
It is composed of two NMOS transistors 5a and 5b. As shown in FIG. 2, the TMR element 4a includes a ferromagnetic layer 3a, an insulating barrier layer 2a, and a ferromagnetic layer 1a that is harder to invert than the ferromagnetic layer 3a. Also, TMR
The element 4b includes a ferromagnetic layer 3b, an insulating barrier layer 2b, and a ferromagnetic layer 1b that is harder to invert than the ferromagnetic layer 3b. Also, two NMOS transistors 5a and 5b
The word line WL is connected to the gate of the.

In the memory cell array 51, each memory cell 52 arranged in the row direction (vertical direction in FIG. 1) is connected to the word line WL and the auxiliary word line SWL.
Each memory cell 52 arranged in the column direction (horizontal direction in FIG. 1) is connected to the bit line BL and the inverted bit line / BL. Inverted bit line / BL constitutes one set of bit line pair with corresponding bit line BL. In addition,
The inverted bit line / BL is an example of the "pair line" in the present invention.

Further, each bit line pair BL, / BL is connected to each cross-coupled latch type sense amplifier (SA) 53. In each bit line pair BL, / BL, the signal levels of the bit line BL and the inverted bit line / BL change complementarily.

Here, the MRAM according to the first embodiment
Then, a current path control circuit 70 is provided between each bit line pair BL, / BL and each sense amplifier (SA) 53 for connecting the current path of each bit line BL at the time of writing data. There is. This current path control circuit 70
As shown in FIG. 3, NAND circuits 71 and 72 and A
ND circuits 73 to 78, switching transistors Tr1 and Tr2 formed of PMOS transistors, and NM
Switching transistor T consisting of OS transistor
r3 to Tr8 and NMOS transistors 8a and 8b
Includes and. The NAND circuits 71 and 72
And AND circuits 73 to 78 are the "logic circuits" of the present invention.
Is an example. In addition, the switching transistor Tr1
~ Tr8 are examples of the "switching element" of the present invention.

The NMOS transistors 8a and 8b are
Each bit line pair BL, / BL and each sense amplifier (SA)
It is provided to separate 53. That NMOS
The signal line Φ3 is connected to the gates of the transistors 8a and 8b.
Are connected.

The outputs of the NAND circuits 71 and 72 are connected to the gates of the switching transistors Tr1 and Tr2, which are PMOS transistors, respectively. The gates of the switching transistors Tr3 to Tr8, which are NMOS transistors, are
The outputs of the AND circuits 73 to 78 are connected to each other. Therefore, when the outputs of the NAND circuits 71 and 72 are at L level, the switching transistors Tr1 and Tr2, which are PMOS transistors, are turned on. The outputs of the AND circuits 73 to 78 are H
In the case of the level, the switching transistors Tr3 to Tr8, which are NMOS transistors, are turned on.

One source / drain of the switching transistor Tr1 is connected to Vcc, and the other source / drain is connected to the bit line BL0. One source of the switching transistor Tr2 /
The drain is connected to Vcc and the other source /
The drain is connected to the inverted bit line / BL0.

Further, one source / drain of the switching transistor Tr3 is connected to the bit line BL0, and the other source / drain thereof is connected to the bit line BL1. One source / drain of the switching transistor Tr4 is connected to the bit line BL0, and the other source / drain is the inverted bit line / BL.
Connected to 1. Further, one source / drain of the switching transistor Tr5 has an inverted bit line / B.
It is connected to L0, and the other source / drain is connected to the bit line BL1. One source / drain of the switching transistor Tr6 is connected to the inverted bit line / BL0, and the other source / drain is connected to the inverted bit line / BL1. The switching transistors Tr3 to Tr6 and the AND circuits 73 to 76 are connected to the bit lines BL2, BL3, not shown.
Are similarly provided.

Further, one source / drain of the switching transistor Tr7 is connected to the bit line BLn, and the other source / drain is grounded.
Further, one source / drain of the switching transistor Tr8 is connected to the inverted bit line / BLn, and the other source / drain is grounded.

Further, one input terminals of the NAND circuits 71 and 72, second input terminals of the AND circuits 73 to 76,
The write enable signal line WE is connected to one input terminals of the AND circuits 77 and 78, respectively.

The other input terminal of the NAND circuit 71 is connected to the bit line BL0, and the NAND circuit 7
The other input terminal of 2 is connected to the inverted bit line / BL0. The first input terminal of the AND circuit 73 is connected to the bit line BL1 and the third input terminal of the AND circuit 75. The third input terminal of the AND circuit 73 is connected to the inverted bit line / BL0 and the third input terminal of the AND circuit 74. The first input terminal of the AND circuit 74 is connected to the inverted bit line / BL1 and the third input terminal of the AND circuit 76. The first input terminal of the AND circuit 75 is connected to the bit line BL0 and the first input terminal of the AND circuit 76. The third input terminal of the AND circuit 76 is connected to the inverted bit line / BL1 and the first input terminal of the AND circuit 74.

The other input terminal of the AND circuit 77 is
It is connected to the inverted bit line / BLn. Also, AND
The other input terminal of the circuit 78 is connected to the bit line BLn.

Further, as shown in FIG. 1, each word line WL
Are connected to the row decoder 54. When the row address RA is specified from the outside, the row address RA
Are supplied from the row address buffer 55 to the row decoder 54. As a result, the row decoder 54
The word line WL corresponding to the row address RA is selected.

One end of the auxiliary word line SWL is connected to each word line WL via an inverter circuit including an NMOS transistor 6 and a PMOS transistor 7. At the other end of the auxiliary word line SWL, a PMOS is provided.
Vcc is connected through the transistor 9. The signal line Φ4 is connected to the gate of the PMOS transistor 9.

The word line WL is connected to one input terminal of the AND circuit 11 and the output terminal of the AND circuit 11. The other input terminal of the AND circuit 11 is connected to the signal line Φ6 which is always 0 (L level) at the time of writing.

Further, the bit line BL and the inverted bit line /
NMOS transistors 10a and 10b are connected to BL, respectively. NMOS transistor 10
A signal line Φ5 is connected to the gates of a and 10b. One ends of the NMOS transistors 10a and 10b are connected to each other. N connected to each other
A precharge circuit 67 is connected to the MOS transistors 10a and 10b.

Further, the bit line BL and the inverted bit line / BL
An NMOS transistor 100 for connecting the bit line BL and the inverted bit line / BL is arranged between and. Further, Φ10 is connected to the gate of the NMOS transistor 100.

Each sense amplifier 53 is connected to the input / output line I / O and the inverted input / output line / I / O via each transfer gate 56. The input / output line I / O and the inverted input / output line / I / O form an input / output line pair I / O, / I / O. The input / output line pairs I / O and / I / O are connected to the read amplifier 57. The read amplifier 57 is connected to the data output circuit 58 via the data bus DB and the inverted data bus / DB. Data bus DB,
Data bus line pair DB, / D with inverted data bus / DB
It constitutes B. In addition, the I / O line pair I / O, / I / O
A precharge circuit 59 is connected to.

Input / output line I / O and inverted input / output line / I
The level with / O changes complementarily. Further, the levels of the data bus DB and the inverted data bus / DB change complementarily. Then, the output circuit 58 outputs the data to the outside.

Each transfer gate 56 is connected to a column decoder 60 via a column selection line CSL. Each transfer gate 56 includes an input / output line pair I / O,
It is composed of a pair of NMOS transistors connected between / I / O and the sense amplifier 53. The gates of the pair of NMOS transistors are connected to the column decoder 60 via one column selection line CSL. Therefore, when the column selection line CSL becomes H level, the pair of NMOS transistors are turned on and the transfer gate 56 is turned on. In FIG. 3, the transfer gate 56 is shown in order to simplify the drawing.
, I / O line pair I / O, / I / O, and column selection line CS
L is not shown.

When the column address CA is designated from the outside, the column address CA is supplied from the column address buffer 61 to the column decoder 60 and the address transition detection circuit (ATD: Address Transition).
Detector) 62.

The ATD 62 detects that the column address CA is designated from the outside by detecting the change of the column address CA, and detects the pulse signal ATD of one pulse.
1 is generated. That is, the pulse signal ATD1 is generated every time the column address CA changes. The pulse signal ATD1 is output to the column decoder control circuit 63, the precharge control circuit 64, and the read amplifier control circuit 65.

Precharge control circuit 64 generates one pulse of precharge circuit activation signal PC which is at H level for a preset time based on the fall of pulse signal ATD1 from H level to L level. The activation signal PC is output to the precharge circuit 59.

When the precharge circuit 59 is activated,
I / O line pair I / O and / I / O are set to the same potential,
Predetermined potential (for example, 1/2 Vcc: Vcc is MRA
The precharge is set to the M drive voltage).

The precharge circuit 59 has an activation signal PC.
Is input, it is deactivated (activated standby state) and precharge of the I / O line pair I / O and / I / O is stopped. The column decoder control circuit 63 uses the pulse signal AT
Based on the fall of D1 from the H level to the L level, a one-pulse column decoder activation signal YS that is at the H level for a preset time is generated. The activation signal YS is output to the column decoder 60.

When the activation signal YS is input, the column decoder 60 is activated and selects the column (one set of bit line pair BL, / BL) of the memory cell array 51 corresponding to the column address CA designated from the outside. That is, the column decoder 60 is activated when the activation signal YS is input. Then, when activated, the column decoder 60 selects the column selection line CSL corresponding to the column address CA externally designated, and the column selection line C
Set SL to H level. As a result, the transfer gate 56 connected to the column selection line CSL is turned on. Therefore, the transfer gate 56
The memory cell array 5 corresponding to the column address CA externally designated via the sense amplifier 53 corresponding to
Column 1 is selected.

The read amplifier control circuit 65 delays the pulse signal ATD1 by a predetermined time to generate a one-pulse read amplifier activation signal READ based on the fall of the pulse signal ATD1 from the H level to the L level. The timing and pulse width of the activation signal READ are preset. Then, the activation signal READ is output to the read amplifier 57.

The delay time of the activation signal READ is the time until the potential difference between the input / output line pair I / O, / I / O becomes a potential difference sufficient for reading data. That is,
Based on the data read from the memory cell 52, it is possible to change from the potential at which the input / output line pair I / O, / I / O is precharged to a potential difference sufficient for the read amplifier 57 not to perform erroneous reading. It is set to wait time.

In other words, each of the control circuits 63 to 65 receives the falling of the pulse signal ATD1 from the H level to the L level, and generates a delay circuit for activating signals YS, PC, and READ with appropriate timing and pulse width. And the pulse generation circuit.

A read detection circuit 66 is provided which detects the potential difference between the data bus line pair DB and / DB and generates a read detection signal READ based on the detection result. As a result, the data bus line pair DB, /
When the potential of DB exceeds a predetermined potential difference, the memory cell 5
The data read from 2 is confirmed and output to the outside. Therefore, the data output (read operation) can be detected by detecting the potential difference between the data bus line pair DB and / DB. Then, the read detection circuit 66 detects the read operation based on the potential difference between the data bus line pair DB, / DB, and generates the H level read detection signal READ based on the detection result. The detection signal READ is supplied to the column decoder control circuit 63, the precharge control circuit 64 and the read amplifier 6
It is output to 5.

Next, the write operation and read operation of the MRAM according to the first embodiment configured as described above will be described.

(Write Operation) In this write operation,
A case of writing to the memory cell 52 connected to the word line WL1 will be described. As shown in FIG. 3, while operating the column decoder 60, the write data is stored in the latch which is also the sense amplifier 53. Bit line B
The case where the H level is stored in L0, the L level is stored in the bit line BL1, and the L level is stored in the bit line BLn will be described.

First, when writing data,
The signal line Φ6 (see FIG. 2) is set to L level. As a result, the L level signal is input to the other input terminal of the AND circuit 11. In this case, the word line WL1 input to one input terminal of the AND circuit 11 is connected to the row decoder 54
Since it is a word line selected by, it is at H level. Therefore, the portion of the selected word line WL1 output from the AND circuit 11 is at the L level. In this way, by setting the signal line Φ6 to the L level, the AN
The word line WL1 connected to the output of the D circuit 11 is forced to the L level.

As a result, the NMOS transistors 5a and 5b connected to the word line WL1 connected to the output terminal of the AND circuit 11 are turned off. Then, by lowering the signal line Φ4 to the L level, the PMO
The S transistor 9 is turned on. In this case, since the word line WL1 connected to the SWL1 via the inverter is in the H level state, the NMOS that constitutes the inverter is
The transistor 6 is turned on. This allows the SW
The lower part of L1 is at ground potential. In the upper part of SWL1, the PMOS transistor 9 is turned on by the fall of Φ4 to reach the Vcc potential, so the auxiliary word line SWL1
An electric current flows from top to bottom.

On the other hand, as shown in FIG. 3, BL0, BL1
And BLn are at the H level, the L level and the L level, respectively, the inverted bit lines / BL0, / B
L1 and / BLn become L level, H level, and H level, respectively. In this case, one input terminal of the NAND circuit 71 becomes H level and the NAND circuit 7
One input terminal of 2 goes to L level. In this state, the write enable signal line WE is set to H level and the signal line Φ3 is set to L level. As a result, the output of the NAND circuit 71 becomes L level and the NAND circuit 7
Since the output of 2 becomes H level, the switching transistor Tr1 is turned on and the switching transistor Tr2 is turned off.

Further, since the output of the AND circuit 76 becomes H level, the switching transistor Tr6 is turned on. As a result, since the inverted bit line / BL0 and the inverted bit line / BL1 are connected, the bit line pair BL
The current paths of 0, / BL0 and the bit line pair BL1, / BL1 are connected. Since the outputs of the AND circuits 73 to 75 are at the L level, the switching transistor T
r3 to Tr5 are turned off. Similarly, the current paths of the bit lines BL2, BL3, ...
Switching transistors Tr3 to Tr6 and AND
Connected using circuits 73-76.

Since the output of the AND circuit 77 becomes H level and the output of the AND circuit 78 becomes L level, the switching transistor Tr7 is turned on and the switching transistor Tr8 is turned off. Further, Φ10 becomes H level, and the NMOS transistor 100 is turned on.

The above switching transistors Tr1 to Tr1
Depending on the on / off state of Tr8, each bit line (BL
0, BL1, ..., BLn), the current paths are connected, so that the current flows in a single stroke in the bit line, as indicated by the thick line in FIG. That is, since the current path of each bit line is connected by the current path control circuit 70, the rewrite current can be passed to each bit line as one current path. As a result, all the cells intersecting the selected auxiliary word line SWL1 are rewritten by the combined magnetic field of the magnetic field generated by the current of the auxiliary word line SWL1 and the magnetic field generated by the direction of the current flowing through each bit line. It should be noted that currents flowing in mutually opposite directions flow through each bit line pair BL, / BL.

In the first embodiment, as described above, at the time of writing data, the current path control circuit 70 is used to connect the current paths of the respective bit lines so that the rewrite current can flow as one current path. Therefore, the data can be rewritten with less current consumption as compared with the case where the rewriting current is supplied to each bit line.

As described above, in the selected memory cell, the auxiliary word line SWL1 is supplied with the current in the downward direction and the bit line pair BL, / BL is supplied with the opposite currents. , The ferromagnetic layer 3a of the TMR element 4a and the ferromagnetic layer 3b of the TMR element 4b of the selected memory cell are easily reversed (for example, "
1 "," 0 ") can be written.

The ferromagnetic layer 3a of the TMR element 4a,
When it is desired to write the opposite data (for example, "0", "1") to the ferromagnetic layer 3b of the TMR element 4b, the directions of the currents flowing through BL and / BL should be reversed. Good.

(Reading Operation) As described above, in the data writing operation, the ferromagnetic layer 3a of the TMR element 4a connected to the bit line BL and the inverted bit line / BL.
Data having opposite magnetic fields are written in the ferromagnetic layer 3b of the TMR element 4b connected to the. Hereinafter, the read operation when the memory cell 52 connected to the word line WL1 is selected will be described with reference to FIGS.
Will be described with reference to.

First, before the word line WL1 (see FIG. 2) rises, the word line WL1 is in the L level state. In this case, since the PMOS transistor 7 of the inverter circuit connected to the word line WL1 is turned on,
The potential of the auxiliary word line SWL1 becomes Vcc. As a result, the potential of the node a also becomes Vcc. Further, since the TMR elements 4a and 4b are conductors, the potentials of the TMR elements 4a and 4b are also Vcc. In this state, Φ5
Rises to H level and the precharge circuit 6
7, the bit line BL and the inverted bit line / BL are set to Vc
Precharge to c. Further, when the word line WL1 rises, the word line WL1 is set to H by the row decoder 54.
Since it is set to the level, the NMOS transistors 5a and 5b connected to the word line WL1 are turned on. As a result, the bit line BL and the inverted bit line /
BL and the TMR elements 4a and 4b are brought into conduction. In this state, the bit line BL and the inverted bit line / BL
And the potential of the node a is Vcc.

When the word line WL1 rises to the H level, Φ5 goes to the L level, and the precharge circuit 67
Since the NMOS transistor 6 of the inverter circuit connected to the word line WL1 is turned on, the potential of the auxiliary word line SWL1 is gradually lowered toward the GND potential. As a result, the potential of the node a is gradually lowered to the GND potential. As a result, the potentials of the bit line BL and the inverted bit line / BL are gradually lowered to the GND potential. Here, the TMR element 4a connected to the bit line BL side has opposite magnetic field directions in the upper and lower ferromagnetic layers 3a and 1a, so that the TMR element 4b connected to the inverted bit line / BL. The resistance is slightly higher than that of.

The bit line BL and the inverted bit line /
At the timing when the potential of BL starts to be lowered toward the GND potential, the bit line BL and the inverted bit line / B
Since there is a minute potential difference between L and the node a, the MR ratio (rate of resistance change) becomes the largest.

As the potential of the node a decreases, the potentials of the bit line BL and the inverted bit line / BL also decrease. In this case, the TMR element 4 on the bit line BL side
Since "a" has a slightly high resistance, the potential lowers more slowly than the inverted bit line / BL. As a result, the bit line B
A potential difference occurs between L and the inverted bit line / BL. At the timing when this potential difference occurs, as shown in FIG.
The word line WL1 is lowered from H level to L level.

The fall timing of the word line WL1 is performed before the potential of the node a becomes the GND potential. This is for the following reason. That is, the potential difference between the bit line BL and the inverted bit line / BL occurs only in the transient state.
Therefore, when the potentials of the ferromagnetic layers 1a and 1b (potential of the node a) of the TMR elements 4a and 4b reach the GND potential, the bit line BL and the inverted bit line / BL connected to the ferromagnetic layers 3a and 3b are also GND. It becomes a potential. In this case, the potential difference between the bit line BL and the inverted bit line / BL disappears, and the potential difference cannot be detected.

At a transitional timing, a potential difference occurs between the bit line BL and the inverted bit line / BL, but TMR
Since the elements 4a and 4b are conductors, the bit line BL and the inverted bit line / BL finally have the same potential.
Therefore, the signal line Φ3 (see FIG. 3) is lowered according to the falling timing of the word line WL1. As a result, the NMOS transistor (isolation transistor) 8a
And 8b are turned off, the bit line BL and the inverted bit line / BL are separated from the sense amplifier 53. After that, the sense amplifier 53 is activated by raising Φ1 and Φ2 of the sense amplifier 53. As a result, the potential difference between the bit line BL on the sense amplifier 53 side and the inverted bit line / BL on the sense amplifier 53 side is amplified and divided into Vcc and GND, respectively. In this way, the data read operation is performed.

Note that Φ5 is raised at the falling timing of the signal line Φ3, and the precharge circuit 67
Is turned on to precharge the bit line BL and the inverted bit line / BL to Vcc.

(Second Embodiment) FIG. 5 is a block diagram showing the overall configuration of an MRAM according to a second embodiment of the present invention. FIG. 6 shows an MRA according to the second embodiment shown in FIG.
3 is a circuit diagram showing a memory cell array unit of M and a current path control circuit unit. FIG. 5 and 6, the second embodiment is an application example of a case where the memory cell is configured by one transistor and one TMR element, which is different from the first embodiment.

That is, in the second embodiment, as shown in FIG. 5, one memory cell 92 is composed of one transistor 5a and one TMR element 4a. Then, in the second embodiment, each bit line BL
A corresponding auxiliary bit line SBL is provided. The auxiliary bit line SBL is an example of the “pair line” in the present invention.

Further, in the second embodiment, the latch 83 is provided between the current path control circuit 70 and the column decoder 60.
Is provided. The latch 83 is used for the column decoder 60.
3 and the sense amplifier 53 according to the first embodiment shown in FIG.
It has the same circuit configuration as. The latch 83 is an example of the “latch circuit” in the present invention.

Also, in the second embodiment, the reference bit line BLr and the auxiliary reference bit line SBLr are provided. The reference bit line BLr has one resistance element 14a and one resistance element 14a.
A reference memory cell 93 including one NMOS transistor 5a is included for each word line WL. The resistance element 14a of the reference memory cell 93 is TM when the magnetization directions are parallel.
TMR when the resistance value of the R element 4a and the magnetization direction are antiparallel
It has a resistance value Rr intermediate to the resistance value of the element 4a. The reference bit line BLr and the auxiliary reference bit line SBLr are connected to the sense amplifier 57a via the precharge circuit 59. Further, in the second embodiment, a sense amplifier control circuit 65a is connected to the sense amplifier 57a. Further, the I / O line and the / I / O line are also connected to the sense amplifier 57a via the precharge circuit 59.

The internal structure of the current path control circuit 70 in the second embodiment is the same as the internal structure of the current path control circuit 70 according to the first embodiment shown in FIG. The other configurations of the MRAM according to the second embodiment are similar to those of the first embodiment.

In the second embodiment, the memory cell 92 is composed of one transistor 5a and one TMR element 4a by providing the auxiliary bit line SBL paired with each bit line BL as described above. Also in this case, the current path control circuit 70 can be used to connect the current paths of the respective bit lines, so that the rewriting current can be passed through each bit line as one current path during writing. As a result, it is possible to rewrite data with less current consumption as compared with the case where a rewrite current is supplied to each bit line.

(Write Operation) The specific write operation (rewrite operation) is the same as in the first embodiment described above. That is, in the write operation of the MRAM according to the second embodiment, as shown in FIG.
The write data is stored in the latch 83 while operating. The case where the H level is stored in the bit line BL0, the L level is stored in the bit line BL1, and the L level is stored in the bit line BLn will be described.

First, using the same method as in the first embodiment, a current is passed through the auxiliary word line SWL1 from top to bottom.

On the other hand, as shown in FIG. 6, BL0, B
L1 and BLn are H level, L level,
Since it is at L level, inverted bit lines / BL0, / B
L1 and / BLn become L level, H level, and H level, respectively. In this case, the switching transistor Tr1 is turned on and the switching transistor Tr2 is turned off. Further, the switching transistor Tr6 is turned on, and the switching transistors Tr3 to Tr5 are turned off. Further, the switching transistor Tr7 is turned on and the switching transistor Tr8 is turned off.

The above switching transistors Tr1 to Tr1
Depending on the state of Tr8, each bit line (BL0, BL1,
, BLn), the current flows in a single stroke in the bit line, as indicated by the thick line in FIG. That is, since the current path of each bit line is connected by the current path control circuit 70, the rewrite current can be passed to each bit line as one current path. As a result, all the cells intersecting with the selected auxiliary word line SWL1 are rewritten by the combined magnetic field of the magnetic field generated by the current of SWL1 and the magnetic field generated by the direction of the current flowing through each bit line. Each bit line pair BL, /
Currents flowing in mutually opposite directions flow through BL.

(Read Operation) Next, the read operation when the memory cell 92 connected to the word line WL1 and the bit line BL2 is selected will be described with reference to FIGS.

First, as an initial state, each bit line BL
The auxiliary word line SWL, the I / O line, and the reference bit line BLr are at Vcc (H level). After that, each bit line BL and each auxiliary word line SWL is set to V
The cc state becomes the floating state. Then, the address is input to the row decoder 54 and the signal line Φ
When 6 is activated to H level, the output of the AND circuit 11 becomes H level, and the selected word line WL1 rises to H level. Also, the AND circuit 11
When the selected word line WL1 input to is set to the H level, the NMOS transistor 6 connected to the auxiliary word line SWL1 corresponding to the selected word line WL1 is turned on. As a result, the auxiliary word line SWL1 which has been in the floating state of Vcc is V
From cc, it gradually starts to drop to the ground potential (Vss).

At this time, the bit line BL2 and the auxiliary bit line SBL are connected to the I / O line and the / I / O line, respectively, by the address input to the column decoder 60. The reference bit line BLr and the auxiliary reference bit line S
BLr is connected to the precharge circuit 59. In this state, when the auxiliary word line SWL1 starts to drop from Vcc toward the ground potential (Vss), the bit line BL
2 and the reference bit line BLr also start to drop from Vcc to the ground potential (Vss). As a result, the I / O line and the reference bit line BLr which are the inputs of the sense amplifier 57a
Also starts to drop from Vcc toward the ground potential (Vss).

In this case, the T of the selected memory cell 52 is
The resistance value of the MR element 4a is smaller than the resistance value Rr of the resistance element 14a of the reference bit line BLr, assuming that the magnetization directions are parallel. Therefore, the I / O line connected to the bit line BL2 and the reference bit line BLr have different speeds of falling from Vcc toward the ground potential (Vss). Specifically, since the I / O line connected to the bit line BL2 tries to fall faster than the reference bit line BLr, a potential difference is generated between the I / O line connected to the bit line BL2 and the reference bit line BLr. Occurs.

The occurrence of the potential difference is detected at an appropriate timing. By this detection, the sense amplifier 57a is activated. Then, the activated sense amplifier 57a is used to amplify the potential difference generated between the I / O line connected to the bit line BL2 and the reference bit line BLr, so that the I / O line connected to the bit line BL2 is at the L level. And the reference bit line BLr goes high. Then, the corresponding signal is output from the output circuit 58.

On the other hand, when the selected memory cell stores the data when the magnetization directions are antiparallel, the reference bit line BLr is set to the reference bit line BLr rather than the resistance value of the TMR element 4a of the selected memory cell 52. Since the resistance value Rr of the connected resistance element 14a is smaller, the reference bit line BLr is the I / O connected to the bit line BL2, contrary to the above case.
Trying to fall faster than the line. If this potential difference is amplified using the sense amplifier 57a, the I / O line becomes H level and the reference bit line BLr becomes L level.

The timing for detecting the potential difference between the I / O line and the reference bit line BLr by the sense amplifier 57a is performed before the potentials of the bit line BL2 and the reference bit line BLr reach the GND potential. This is for the following reason. At the transitional timing, a potential difference occurs between the bit line BL and the reference bit line BLr, but the TMR element 4a
Since the resistance element 14a and the resistance element 14a are conductors, the bit line BL and the reference bit line BLr finally have the same potential.

In the second embodiment, as described above, one TMR element 4a and one NMOS transistor 5a constitute one memory cell 52, and
Data can be easily read by detecting the potential difference between the bit line BL connected to one TMR element 4a and the reference bit line BLr using the sense amplifier 57a.

It should be understood that the embodiments disclosed this time are examples in all respects and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes meanings equivalent to the scope of claims for patent and all modifications within the scope.

For example, although the TMR element is used as the memory element forming the memory cell in the above embodiment, the present invention is not limited to this, and any memory element other than the TMR element can be used as long as the memory element exhibits the ferromagnetic tunnel effect. A memory element can also be used. Further, the same effect as in the above embodiment can be obtained by using a memory element exhibiting a magnetoresistive effect other than the memory element exhibiting a ferromagnetic tunnel effect.

[0105]

As described above, according to the present invention, it is possible to rewrite data with a smaller current consumption as compared with the case where a rewriting current is supplied to each bit line.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an MRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a memory cell portion of the MRAM of the first embodiment shown in FIG.

FIG. 3 shows the M according to the first embodiment shown in FIGS. 1 and 2.
FIG. 3 is a circuit diagram showing a memory cell array unit and a current path control circuit unit of RAM.

FIG. 4 is an MRA of the first embodiment shown in FIGS. 1 and 2;
FIG. 7 is an operation waveform diagram for explaining a read operation of M.

FIG. 5 is a block diagram showing an overall configuration of an MRAM according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a memory cell array unit and a current path control circuit unit of the MRAM of the second embodiment shown in FIG.

FIG. 7 is a schematic diagram for explaining a configuration of a storage element of a conventional MRAM.

FIG. 8 is a schematic diagram for explaining a configuration of a storage element of a conventional MRAM.

FIG. 9 is a block diagram showing the overall configuration of a conventional MRAM.

[Explanation of symbols]

4a, 4b TMR elements 5a, 5b NMOS transistor 51 memory cell array 52, 92 memory cell 53 sense amplifier 83 latch (latch circuit) 60 column decoder 70 current path control circuits 71, 72 NAND circuit (logic circuit) 73, 74, 75, 76, 77, 78 AND circuit (logic circuit) Tr1 to Tr8 switching transistor (switching element)

Claims (4)

[Claims] 1. A first bit line and a second bit line having a current path independent of the first bit line, wherein a common write current path for the first bit line and the second bit line is provided. Storage device. 2. A first bit line, a first pair line paired with the first bit line, a second bit line, a second pair line paired with the second bit line, and the first bit line. A bit line and one of the first pair lines,
A current path control circuit for connecting a current path between the first bit line and the second bit line by connecting either the second bit line or the second pair line during writing. Storage device. 3. A first latch circuit for storing write data for the first bit line, and a second latch circuit for storing write data for the second bit line, the first latch The memory device according to claim 1, wherein the current path of the first bit line and the current path of the second bit line are connected to each other based on an output of a circuit and the second latch circuit. 4. The current path control circuit includes a logic circuit that operates based on the outputs of the first latch circuit and the second latch circuit, and a switching element that is on / off controlled based on the output of the logic circuit. The storage device according to claim 2, comprising: