WO2003028076A1 - Procede de fabrication d'un dispositif semi-conducteur ayant une couche tampon composite - Google Patents

Procede de fabrication d'un dispositif semi-conducteur ayant une couche tampon composite Download PDF

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Publication number
WO2003028076A1
WO2003028076A1 PCT/CN2002/000675 CN0200675W WO03028076A1 WO 2003028076 A1 WO2003028076 A1 WO 2003028076A1 CN 0200675 W CN0200675 W CN 0200675W WO 03028076 A1 WO03028076 A1 WO 03028076A1
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Prior art keywords
groove
semiconductor
semiconductor wafer
mask
dielectric layer
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PCT/CN2002/000675
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English (en)
French (fr)
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Xingbi Chen
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Tongji University
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Priority to US10/490,817 priority Critical patent/US7192872B2/en
Publication of WO2003028076A1 publication Critical patent/WO2003028076A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Definitions

  • the present invention relates to a method for manufacturing a semiconductor power device, and more particularly, to a method for manufacturing a semiconductor power device containing a composite buffer layer. Background technique
  • the reverse voltage applied to the n + region and the p + region is withstood by a lightly doped semiconductor layer.
  • This layer is hereinafter referred to as a voltage sustaining layer.
  • the on-resistance R. jos(Or on-voltage drop) is also mainly determined by the withstand voltage layer. The lighter the doping of this layer, or the larger the thickness, or both, the higher the breakdown voltage, but the on-resistance (or on-state) The voltage drop is also larger.
  • one of the most important issues is to have both a high breakdown voltage and a low on-resistance. Obstacles to power devices.
  • R refers to the conduction area in the voltage-resistant layer, and in fact, some areas in the voltage-resistant layer do not participate in conduction.
  • the area under the source substrate area of the vertical (vertical) M0SFET (metal oxide semiconductor field effect transistor) and the area under the contact layer of the base region of the bipolar transistor are all areas that do not participate in conduction.
  • the inventor's Chinese invention patent ZL91 101845. X and US invention patent 5, 216, 275 solve the above problems.
  • the solution is to use a composite buffer layer (Composi te Buffer Layer, or CB for short) in the P + region and n + region. Layer) to withstand pressure.
  • the CB layer contains two regions of opposite conductivity types. These two regions are arranged alternately from any section parallel to the interface between the CB layer and the n + layer (or p + layer).
  • the voltage-resistant layers used before were all single-conductivity semiconductors.
  • the invention also discloses an ON resistance R per unit area of an MOS tube using such a voltage-resistant layer.
  • SwiftProportional to the breakdown voltage of 1.3 power which represents a breakthrough in the relationship between the withstand voltage layers, and other electrical properties of the M0S tube are also very good.
  • MOS tube using the structure of a super junction device ie, a CB layer structure
  • CB layer structure a super junction device
  • FIG. 1 (a) to 1 (b) show a method for manufacturing a super-junction power device 1.
  • the process is to first grow a first epitaxial layer 3 from a semiconductor wafer of a substrate 2.
  • the substrate 2 is a heavily miscellaneous n + layer
  • the first epitaxial layer 3 is a lightly doped n layer, in which a p-type region 4 is ion-implanted.
  • an epitaxial layer is required for every 50 to 100 volts withstand voltage. Therefore, for a 600V transistor, the n-type epitaxial layers of 5, 7, 9, 11, and 13 in FIG. 1 (a) must be sequentially formed, and 6, 8 in FIG. 1 (a) must be performed after each epitaxy. 10, 12 and 14 p-type ion implanted layers.
  • the formed P-type ion-implanted layers 4, 6, 8, 10, 12 and 14 are diffused to form the p-region 16 in FIG. 1 (b).
  • the region not affected by the ion-implantation is the n-region 15, which forms an interphase. Queues p and n.
  • the device layer or device feature layer 17 is made.
  • the device characteristic layer 17 contains an n + source region 18 formed by ion implantation, an oxide layer 19 and a metal gate or a polysilicon gate 20 thereon.
  • the purpose of the present invention is to propose a simple CB layer manufacturing method, which does not require multiple epitaxy, multiple ion implantation, and multiple photolithography, so the cost can be reduced.
  • a first mask of a first conductivity type is covered with a first mask of a first pattern, and the first mask of the first pattern covers a part of the semiconductor surface with a mask and there is no mask other than these parts ;
  • Etching removes the semiconductor part without mask to form the first mosaic-shaped trench with the first depth, which has a bottom and a side wall;
  • the second mask of the second pattern enables the second semiconductor wafer to be covered by the mask and the first semiconductor
  • the pattern formed at the bottom of the slot of the sheet is consistent;
  • Etching removes the semiconductor portion that is not covered by the mask on the second semiconductor wafer to form a second mosaic-shaped groove, which has a bottom, a side wall, and a groove depth close to the first depth;
  • the outer semiconductor surface of the groove of the second semiconductor wafer where the groove has been formed is abutted with the bottom of the groove of the first semiconductor wafer where the groove is formed, and the bottom of the groove of the second semiconductor wafer is connected to the groove of the first semiconductor wafer.
  • the outer semiconductor surface is butted, and the side wall of the groove of the two semiconductor wafers is butted against the side wall, so that the two semiconductor wafers are joined to form a semiconductor wafer;
  • a composite buffer layer is formed in a groove of a first depth in the synthesized one semiconductor wafer.
  • the method for manufacturing a semiconductor device containing a composite buffer layer wherein the first semiconductor wafer including the first mosaic-shaped groove and the second semiconductor wafer including the second mosaic-shaped groove are formed on the groove.
  • a thin dielectric layer is formed on the semiconductor walls of the side walls, the bottom and the outside of the trench.
  • Another method for manufacturing a semiconductor device containing a composite buffer layer without a dielectric layer provided by the present invention includes the following steps: A first mask of a first conductivity type is covered with a first mask of a first pattern, and the first mask of the first pattern covers a part of the semiconductor surface with a mask and there is no mask other than these parts ;
  • Etching removes the semiconductor part without mask to form the first mosaic-shaped trench with the first depth, which has a bottom and a side wall;
  • the second mask of the second pattern enables the second semiconductor wafer to be covered by the mask and the first semiconductor
  • the pattern formed at the bottom of the slot of the sheet is consistent;
  • Etching removes the semiconductor portion that is not covered by the mask on the second semiconductor wafer to form a second mosaic-shaped groove, which has a bottom, a side wall, and a groove depth close to the first depth;
  • the outer semiconductor surface of the groove of the second semiconductor wafer where the groove has been formed is abutted with the bottom of the groove of the first semiconductor wafer where the groove is formed, and the bottom of the groove of the second semiconductor wafer is connected to the groove of the first semiconductor wafer.
  • the outer semiconductor surface is butted, and the side wall of the groove of the two semiconductor wafers is butted against the side wall, so that the two semiconductor wafers are joined to form a semiconductor wafer;
  • a first depth inner groove in the synthesized one semiconductor wafer forms a composite buffer layer.
  • an anisotropic etching method is used to form the first mosaic-shaped groove.
  • an anisotropic etching method is used in the step of forming a second damascene groove.
  • the first semiconductor wafer and the second semiconductor wafer are made of silicon.
  • the method for manufacturing a semiconductor device containing a composite buffer layer wherein the first semiconductor wafer of the first conductivity type comprises a first epitaxial layer of the first conductivity type and a heavily doped first conductivity Type substrate, the first mosaic groove is formed in the first epitaxial layer, and the thickness of the first epitaxial layer is close to the first depth of the groove.
  • the method for manufacturing a semiconductor device containing a composite buffer layer wherein the second semiconductor wafer of the second conductivity type comprises a second epitaxial layer of the second conductivity type and a heavily doped second conductivity Type substrate, the second mosaic groove is formed in the second epitaxial layer, and the thickness of the second epitaxial layer is close to the first depth of the groove.
  • the invention also discloses a semiconductor device containing a composite buffer layer, wherein a first semiconductor wafer of a first conductivity type is covered with a first mask of a first pattern, and the first mask of the first pattern makes There are masks on some parts of the semiconductor surface and no masks except on these places;
  • the non-mask-covered semiconductor portion removed by etching has a first mosaic-shaped trench of the first depth, which has a bottom and a side wall; 'on the first semiconductor wafer containing the first mosaic-shaped trench, A thin dielectric layer on the side wall of the groove, and / or a thin dielectric layer on the bottom of the groove, and / or a thin dielectric layer on the semiconductor surface outside the groove;
  • the second semiconductor wafer of the second conductivity type is covered with a second mask of a second pattern, and the second mask of the second pattern enables the second semiconductor wafer to be covered by the mask and the first semiconductor
  • the pattern formed at the bottom of the slot of the sheet is consistent;
  • the unmasked semiconductor portion of the second semiconductor wafer removed by etching has a second damascene A groove, which has a bottom, a side wall, and a groove depth close to the first depth;
  • a thin dielectric layer on the side wall of the groove there is a thin dielectric layer on the side wall of the groove, and / or a thin dielectric layer on the bottom of the groove, and / or in the groove A thin dielectric layer on the outer semiconductor surface;
  • the outer semiconductor surface of the groove of the second semiconductor wafer where the groove has been formed abuts against the bottom of the groove of the first semiconductor wafer where the groove has been formed, and the bottom of the groove of the second semiconductor wafer is in contact with the groove of the first semiconductor wafer.
  • the outer semiconductor surfaces are butted, and the side walls of the grooves of the two semiconductor wafers are butted against the side walls, so that the two semiconductor wafers are joined to form a semiconductor wafer;
  • a composite buffer layer is provided within a first depth of the synthesized semiconductor wafer.
  • the invention also discloses a semiconductor device containing a composite buffer layer, wherein a first semiconductor wafer of a first conductivity type is covered with a first mask of a first pattern, and the first mask of the first pattern Some areas of the semiconductor surface are covered with a mask and no areas other than these areas are covered;
  • the mask-free semiconductor portion removed by etching has a first mosaic-shaped trench of the first depth, which has a bottom and a side wall;
  • the second semiconductor wafer of the second conductivity type is covered with a second mask of a second pattern, and the second mask of the second pattern enables the second semiconductor wafer to be covered by the mask and the first semiconductor
  • the pattern of the bottom of the slot of the sheet is consistent;
  • the part of the semiconductor that is not covered by a mask on the second semiconductor wafer removed by etching has a second mosaic-shaped groove, which has a bottom, a side wall, and a groove depth close to the first depth;
  • the outer semiconductor surface of the groove of the second semiconductor wafer where the groove has been formed abuts against the bottom of the groove of the first semiconductor wafer where the groove has been formed, and the bottom of the groove of the second semiconductor wafer is in contact with the groove of the first semiconductor wafer.
  • the outer semiconductor surfaces are butted, and the side walls of the grooves of the two semiconductor wafers are butted against the side walls, so that the two semiconductor wafers are joined to form a semiconductor wafer;
  • a composite buffer layer is provided within a first depth of the synthesized semiconductor wafer.
  • the present invention proposes a simple CB layer manufacturing method, which does not require multiple epitaxy, multiple ion implantation, and multiple photolithography, so its manufacturing cost can be reduced.
  • Figures 1 (a) and 1 (b) are schematic diagrams of the prior art for manufacturing a CBM0SFET (or a super junction device); Figures 2 (a) and 2 (b) are dielectrically separated and dielectrically free according to the present invention Schematic diagram of two typical types of RM0ST separated;
  • FIG. 3 (a) to FIG. 3 (d) are the pattern arrangements of the section of the section line II-II 'of FIG. 2 (b);
  • Figure 4 (a) to Figure 4 (h) are the manufacturing process of the present invention.
  • FIG. 5 is a schematic diagram of a CB diode manufactured by the method of the present invention.
  • FIG. 6 is a schematic diagram of manufacturing a high-reverse-voltage CB diode by the method of the present invention.
  • FIG. 7 is a schematic diagram of manufacturing a CB bipolar transistor by the method of the present invention.
  • FIG. 8 is a schematic diagram of a VDM0ST of a CB pressure-resistant layer without a dielectric layer in the p-region and the n-region manufactured by the method of the present invention
  • Figures 9 (a) to 9 (b) are a VDM0ST of a CB pressure-resistant layer with a dielectric layer between p and n regions and a dielectric layer between p and n + drain regions manufactured by the method of the present invention.
  • schematic diagram; 10 is a schematic diagram of RM0ST with a dielectric layer between p and n regions and a dielectric layer between p and n + drain regions manufactured by the method of the present invention;
  • FIG. 11 is a schematic diagram of RM0ST with a dielectric layer between p-region and n-region but no dielectric layer between p-region and n + drain region manufactured by the method of the present invention
  • FIG. 12 shows a CB pressure-resistant layer similar to that of FIG. 8 manufactured by the method of the present invention, but with an n-region under the p-region.
  • the invention provides a method for manufacturing a CBMOSFET or a super-junction device.
  • C00LM0ST a novel M0SFET, called C00LM0ST. Because of its excellent electrical characteristics, it broke through the relationship between on-resistance and breakdown voltage in traditional power devices, and was called a milestone for power devices.
  • the pressure-resistant layer used in C00LM0ST is a CB structure based on the hexagonal pattern proposed in Chinese invention patent ZL91 101845. X and US invention patent 5, 216, 275. Such devices are also known as CBM0SFETs or Super-Junction Devices.
  • the device manufactured by the present invention contains a contact layer of a first conductivity type material, which may be an n + type semiconductor or a P + type semiconductor, but the n + type semiconductor is used for description in the present invention.
  • a plurality of polygonal cells are formed on this contact layer, and each cell has a device characteristic layer containing a device characteristic region.
  • the device characteristic layer functions as a second conductive type material and can function as a P + type semiconductor. It can also function as an n + -type semiconductor, but in the present invention, a p + -type semiconductor is used for illustration.
  • the CB layer contains a first semiconductor region composed of a first conductive type material.
  • This first conductive type material may be an n -type semiconductor or a p-type semiconductor, but in the present invention, an n-type conductive material is used for illustration.
  • the CB layer also contains a second semiconductor region made of a second conductive type material.
  • This second conductive type material may be a p-type semiconductor or an n-type semiconductor, but in the present invention, a p-type conductive material is used to illustrate .
  • the first semiconductor region and the second semiconductor region in the CB layer are alternately arranged. There may also be a thin dielectric layer between the first semiconductor region and the second semiconductor region in the CB layer to separate the first semiconductor region from the second semiconductor region. There may also be a thin dielectric layer between the second semiconductor region in the CB layer and the contact layer to separate the second semiconductor region from the contact layer.
  • the present invention provides a method for manufacturing such a semiconductor device, which mainly includes the following steps:
  • a first semiconductor wafer (wafer) having a first epitaxial layer is covered with a mask, and then some parts of the mask are removed by photolithography or other methods to form a first mask with a certain pattern, which is called The first mask of the first pattern.
  • the first mask of the first pattern means that there is a mask covering some parts of the semiconductor surface and there is no mask covering other than these places.
  • the unmasked portion of the first epitaxial layer on the first semiconductor wafer is removed by etching to form a first damascene pattern, the pattern contains a groove, the groove has a sidewall and a bottom, and the groove depth is the first depth.
  • a dielectric layer may be formed on the side wall of the trench, or a dielectric layer may be formed on the bottom of the trench.
  • a dielectric layer may also be formed on the groove-free portion of the first epitaxial layer on the first semiconductor wafer (ie, the surface of the semiconductor wafer without the groove). Alternatively, the dielectric layer may not be provided at all.
  • a second pattern is formed on the bottom of the groove of the first semiconductor wafer.
  • a second semiconductor wafer of the second conductivity type is covered with a mask, and then some parts of the mask are removed by photolithography or other methods to form a second mask with a second pattern.
  • the second mask of the second pattern makes the second piece half
  • the area covered by the mask on the conductor sheet is consistent with the pattern formed on the bottom of the groove of the first semiconductor chip.
  • Etching removes the uncovered semiconductor portion of the second semiconductor wafer to form a second damascene-shaped trench, which has a bottom, a sidewall, and a trench depth close to the first depth.
  • a thin dielectric layer can be formed on the side wall of the groove, or a thin dielectric layer can be formed on the bottom of the groove, or The outer semiconductor surface forms a thin dielectric layer. Alternatively, the dielectric layer may not be provided at all.
  • the outer semiconductor surface of the groove of the second semiconductor wafer where the groove has been formed is abutted with the bottom of the groove of the first semiconductor wafer where the groove is formed, and the bottom of the groove of the second semiconductor wafer is connected to the groove of the first semiconductor wafer.
  • the outer semiconductor surface is butted, and the side wall of the groove of the two semiconductor wafers is butted against the side wall, so that the two semiconductor wafers are joined to form a semiconductor wafer.
  • a composite buffer layer is formed in this semiconductor wafer within the first depth.
  • FIG. 2 (a) and Figure 2 (b) show two cases of CMOS structure containing RM0ST.
  • One is that there is no dielectric layer between the p-type region 24 and the n-type region 25, as shown in FIG. 2 (a).
  • the other is a thin dielectric layer 26 separated between the p-type region 24 and the n-type region 25, and a thin dielectric layer 27 is interposed between the p-type region 24 and the n + -type substrate 23, as shown in FIG. 2 (b ).
  • 28 is an n + source region
  • 29 is a source substrate region
  • 30 is a gate oxide layer.
  • Figures 3 (a) to 3 (d) show the four pattern arrangements of the n-region and p-region on the section line II-II 'of Fig. 2 (b).
  • the area to the left of the dotted line represents the active area, and the arrow 48 represents the direction from the boundary of the active area to the terminal.
  • 24 represents the p-region in the CB structure
  • 25 represents the n-region in the CB structure
  • 26 represents the thin dielectric layer between the p-region and the n-region in the CB structure.
  • the first mask of the first pattern means that some parts of the semiconductor surface are covered with a mask and there is no mask except for these parts.
  • the areas covered by the first mask are as shown in FIG. 3, respectively. (a) to the n-type regions of the four figures in Figure 3 (d).
  • the first pattern of the CB structure in which graph is made is like the n-type region in which graph.
  • FIG. 4 (a) to 4 (h) illustrates a method for producing CB layers according to the present invention, as follows: initially a material shown in FIG 4 (a), which is a substrate n + 23 long An n-type epitaxial layer 31 is formed.
  • the epitaxial layer can be firstly cleaned on the substrate with a gas such as HC1 under a high temperature under vacuum, and then exposed to silane (which can be carried by hydrogen) at a high temperature to deposit silicon on n + On the substrate 23.
  • FIG. 4 (b) The side wall of the trough in Fig. 4 (b) is inclined. This side wall should be as straight as possible. Therefore, a highly selective and anisotropic etching method should be used.
  • the groove depth may be up to the n + substrate 23, or may be slightly higher than the n + substrate 23.
  • a thin dielectric layer covering such as thermally grown silicon dioxide (SiO 2 ), can be formed on the silicon wafer, and the result is shown in FIG. 4 (c).
  • the dielectric layer on the side wall of the n region 25 and the dielectric layer on the semiconductor surface without the groove region are denoted by 33, and the dielectric layer at the bottom is denoted by 32.
  • FIG. 4 (d) Another P-type semiconductor wafer is formed by growing a p-type epitaxial layer 34 on a p + substrate 29.
  • photolithography is performed on the p-type epitaxial layer 34 with a mask, so that n - zone 3 (a) to 3 (d), 25 without a mask, and then the anisotropic etching method maskless portions of p type epitaxial layer 34 is etched so that the P-type epitaxial A groove is formed in the layer 34, and the result is shown in FIG. 4 (e).
  • the long oxide layer is shown in Fig. 4 (f).
  • the dielectric layer on the side wall of P region 24 and the dielectric layer on the semiconductor surface without grooves are denoted by 36, and the dielectric layer at the bottom is denoted by 35.
  • the mask used for the p-type semiconductor wafer should of course be designed so that the top of FIG. 4 (f) fits exactly at the bottom of the groove of FIG. 4 (c), and the top of FIG. 4 (c) fits exactly at FIG. 4 ( f) the bottom of the groove, and the height of the two grooves is also the same.
  • FIG. 4 (f) is connected to the bottom of the groove of FIG. 4 (c), and heated to about 1 100 ° (:, the two semiconductor wafers are directly bonded (Wafer Direct Bonding), or bonded through an oxide layer) .
  • the unetched groove portion of the P + substrate 29 is polished, polished, or chemically polished (Chemi cal Mechani cal Pol i shing), and exposed as shown in Figs. 3 (a) to 3 (d). As shown in FIG. 4 (h), within the depth range of the groove, there are CB layers in which p regions and n regions are alternately arranged.
  • the groove method is a method commonly used in the semiconductor industry. Considering chemical etching or reactive ion etching, which is often used in lateral etching, the mask pattern of the second semiconductor wafer may be slightly larger than the bottom of the first semiconductor wafer. Pattern so that the last two semiconductor wafers can be tightly bonded everywhere.
  • both semiconductor wafers have no dielectric layer, and the second p-type semiconductor wafer is a semiconductor wafer having a p-type epitaxial layer 24 on a p + substrate 29, the groove depth on the semiconductor wafer is close to Based on the thickness of the epitaxial layer, then the anode contact A and the cathode contact K are made to form a CB diode, as shown in FIG. 5.
  • the polishing and polishing of the semiconductor wafer in the last step described above does not need to expose the pattern of FIG. 3, but leaves a part of the p + layer 29.
  • FIG. 6 shows another example of a high-reverse-voltage CB diode made by the method of the present invention.
  • Both semiconductor wafers are non-heavy doped single crystals, and the groove depth of the two semiconductor wafers should be slightly larger than the required pressure-resistant layer thickness.
  • all the grooved parts on both sides are ground and polished to form the 47 part in the figure. Then p + region and n + region are deposited on both sides.
  • Such p + region and n + region can be formed by depositing p + polycrystalline semiconductor 38 above and n + poly semiconductor 37 below to make two kinds of polycrystalline Semiconductor lasers are formed by heating and recrystallization.
  • the p + region and the n + region can even be replaced with a suitable metal to form a Schottky junction.
  • FIG. 7 shows an example of manufacturing a bipolar transistor including a CB voltage-resistant layer by the method of the present invention.
  • the first semiconductor wafer is an n-type epitaxial layer 25 on an n + substrate 23, grooved to a depth close to the epitaxial layer, and the second semiconductor wafer is a P + substrate 29 with a thickness close to the first semiconductor
  • the groove depth of the p-type epitaxial layer 24 is the same as that of the second semiconductor wafer.
  • the second semiconductor wafer has no dielectric layer.
  • the grooveless surface of the first semiconductor wafer also had no dielectric layer.
  • the top of the first semiconductor wafer is masked, and the mask is removed after the medium is covered.
  • the surface is polished. , Throw to remove the top medium.
  • FIG. 8 shows an example of manufacturing a VDM0ST containing a CB pressure-resistant layer by the present invention.
  • the second semiconductor The wafer is a p-type epitaxial layer 24 on the P + substrate 29 with a thickness smaller than the groove depth of the first semiconductor wafer.
  • the groove depth of the second semiconductor wafer is the same as that of the first semiconductor wafer, and neither semiconductor wafer has a dielectric layer.
  • the P + substrate of the combined semiconductor wafer is removed by grinding and polishing until the n-type epitaxial layer of the first semiconductor wafer is exposed, so as to form a portion 41 in FIG. 8.
  • the active region of the device is composed of n + source region 28, gate oxide layer 30, gate electrode 0, source S, and drain D.
  • FIGS 9 (a) and 9 (b) show two examples of the CB pressure-resistant layer with a dielectric layer manufactured by the method of the present invention as VDM0ST. It is assumed that there is a dielectric between the p-region 24, the n-region 25, and the n + drain region 23.
  • the electrode contact of the source is not only connected to the n + source region 28 and the p + source substrate region 42, but also to the p region 24.
  • FIG. 9 (b) in which the neck of the top of each n region is sandwiched by the p + regions 42 on both sides of the source substrate. Can be further reduced.
  • the uppermost dielectric layer between the n-region 25 and the p-region 24 needs to be removed first. For example, by chemical etching. Then the polycrystalline semiconductor is filled in the removed part, and then this part is recrystallized into single crystal by laser heating.
  • the recrystallized part 43 is shown by the cross-hatched area in Fig. 9 (b).
  • the case with a dielectric layer has the following special advantages over the case without a dielectric layer: 1) In the case of Fig. 2 (a), when the lateral electric field at point C is high, the breakdown voltage cannot be increased any more. Its breakdown is along the line of power shown by dashed line 44 in the figure. In the case of Figure 2 (b) with a dielectric layer, the integral of the impact ionization rate that determines the breakdown voltage is only along the upper power line 45 (in the p-type region 24) or the lower power line 46 (in the n-type region 25 Within), so the breakdown voltage can be increased.
  • the miscellaneousness of the n-region 25 and the p-region 24 can be heavier, so that the on-resistance is reduced.
  • a dielectric layer when manufacturing a CB layer, a dielectric layer can be selected to block the diffusion of impurities in the n and P regions of the CB layer during a high temperature process, making control during manufacturing easier.
  • the semiconductor is Si
  • the silicon wafer bonding with a dielectric layer is Si-Si0 2 -S i bonding. This bonding is easier than Si-Si direct bonding. .
  • the CBM0SFET with a dielectric layer does not take certain measures, it is a normally-on device, for the following reasons:
  • Electron-hole pairs are generated at recombination centers in thick depletion layers of semiconductor devices under high reverse bias.
  • the current density generated can be expressed by qniW / (. + T p .), Where ⁇ personallyand ⁇ ⁇ are the lifetimes of small signal electrons and holes, respectively, ni is the intrinsic carrier concentration, and W is the depletion layer. Thickness, q is the electronic charge.
  • holes generated in the p region 24 can be swept to the P + source substrate region 29 by the electric field.
  • the electrons generated in the p region 24 are directly in the p region 24 and the n + drain region 23 When connected, as shown in FIG.
  • the n + drain region 23 can be scanned. However, if a dielectric layer exists between the p region 24, the n + drain region 23, and the n region 25, as shown in FIG. 2 ( As shown in b), the electrons will continue to accumulate at the bottom of p region 24 and adjacent to n region 25. These accumulated electrons will cause an inversion layer, and the negative charge of this inversion layer changes the electric field distribution, thus Reduce the breakdown voltage.
  • FIG. 10 shows an example of a RMOST having a dielectric layer manufactured by the method of the present invention.
  • FIG. 11 shows another example of manufacturing the RM0ST by the method of the present invention. It is required that the first semiconductor wafer has an n + substrate and an n-type epitaxial layer, and the second semiconductor wafer has a p + substrate and a p-type epitaxial layer. It is also required that the bottom of the groove of the first semiconductor wafer and the surface outside the groove have no dielectric layer, and the bottom of the groove of the second semiconductor wafer and the surface outside the groove also have no dielectric layer. After the two semiconductor wafers are bonded, a thickness region of 51 in the figure is formed, and then an n + source region 28 is formed in the p + region 29, and then a groove is formed, and then a gate oxide layer 30 and an electrode are formed.
  • the center of the interface between the p region and the n + substrate tends to generate the largest electric field.
  • the acceptor concentration below the p-region 24 can be made lower than above, and the p-type 24 can be gradually changed from p-type to n-type even at the bottom.
  • An example of the structure is shown in FIG. 12, and it is different from FIG. 8 only in the lowermost part of the p-region into a lightly miscellaneous n-type region 52.
  • the idea of the present invention can also be used to do this, that is, to form an n-type epitaxial layer on top of a semiconductor wafer having a p-type epitaxial layer on a second P + substrate.
  • the n-type impurities are re-diffused so that the surface of the second piece is n-type.
  • the other methods are the same as those of the device of FIG. 8.
  • the above dielectric layer may be a layer S i0 2, and may be another dielectric layer, even if a long oxide layer on the surface S i, the dielectric layer may also cover other .
  • the latter dielectric layer should be made of a material with a high dielectric constant and a good combination of silicon wafers.
  • a high dielectric constant causes the electric flux lines generated by the positive charge of the ionized donor in the n region of the CB layer to be transversely P
  • the effect that is terminated by the flux line generated by the negative charge of the zone ionization acceptor ie, the charge compensation effect does not have an adverse effect.
  • the invention proposes a simple CB layer manufacturing method, which does not require multiple epitaxy, multiple ion implantation, and multiple photolithography, so its manufacturing cost can be reduced.

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Description

一种制造含有复合缓冲层半导体器件的方法 技术领域
本发明涉及一种制造半导体功率器件的方法， 特别涉及一种制造含有复合缓冲 层半导体功率器件的方法。 背景技术
众所周知， 在通常的功率器件中， 加于 n+区和 p+区间的反向电压是由一个轻掺 杂的半导体层来承受的， 以下称此层为耐压层（Voltage Sustaining Layer)。 对于 高压功率器件， 导通电阻 R。„ (或导通压降）也主要由耐压层來决定， 此层掺杂愈轻， 或厚度愈大， 或两者都是， 则击穿电压愈高， 但导通电阻 （或导通压降） 也愈大。 在许多功率器件中， 最重要的问题之一是既要有高的击穿电压又要有低的导通电'阻， 这两者之间的关系成为制造高性能功率器件的障碍。 更有甚者， 所述 R。„是指耐压层 中的导通面积， 而实际上耐压层中总有些区域不参加导电。 例如，垂直型（纵向 型） M0SFET (金属氧化物半导体场效应晶体管） 的源衬底区之下的区域， 双极型晶体 管基区接触层下的区域， 都是不参加导电的区域。
本发明人的中国发明专利 ZL91 101845. X及美国发明专利 5, 216， 275解决了上述 问题， 其解决方法是在 P+区和 n+区间用一个复合缓冲层（Composi te Buffer Layer , 或简称 CB层）来耐压。 在 CB层中含有两种导电类型相反的区域， 这两种区域从平行 于 CB层与 n+层（或 p+层）界面的任一剖面来讲， 都是相间排列的。 而在此之前所用的 耐压层都是单一导电类型的半导体。 在该发明中还公布了用这种耐压层的 M0S 管， 单位面积的导通电阻 R。„正比于击穿电压 1. 3次方， 这代表对通常耐压层关系的 一个突破， 而 M0S管其它的电性能也很好。
在过去几年中， 半导体功率器件的工业界中发生了重大变化。 利用超结（Super Junct ion)器件的结构（即 CB层结构）的 M0S管已能提供高电压及大电流。
图 1 (a)至图 1 (b)表示一个超结功率器件 1的制造方法；其过程是先用一个衬底 2的半导体片生长第一外延层 3。 在该图中衬底 2是一个重惨杂的 n+层， 第一外延层 3是轻掺杂 n层， 在这个层中离子注入一层 p型区 4。 一般而言， 每 50到 100伏的 耐压需要一个外延层。 因此， 对一个 600V的晶体管， 要依次再做图 1 (a)中 5， 7， 9， 11及 13的 n型外延层， 每次外延之后要做图 1 (a)中的 6， 8， 10， 12及 14的 p型 离子注入层。
形成的 P型离子注入层 4， 6， 8， 10， 12与 14经过扩散后形成了图 1 (b)中的 p 区 16， 无离子注入影响的区域是 n区 15， 这就形成了相间棑列的 p区与 n区。 然后 再做器件层或称器件特征层 17。 器件特征层 17中含有离子注入形成的 n+源区 18， 氧化层 19及其上的金属栅或多晶硅栅 20。 在两个 n+源区 18之间还有一个 p+区 21， 其下还有深结的 p+区 22， 深 P +区 22与 p+区 21相联接。
显然， 上述的制造方法很昂贵， 而且由于外延会带来缺陷， 外延次数愈多， 半 导体的质量愈差， 器件的质量也愈差。 此外， 在中国发明专利 ZL91101845. X及美国 发明专利 5, 216, 275中还有一种重要的情形， 即在相间排列的 n区与 p区间有一个 薄的介质层的情形。 上述制造方法显然无法用于此种情形。 发明的公开
本发明的目的， 是提出一种简易的 CB层制造方法， 它不需要多次外延， 多次离 子注入， 多次光刻， 因此成本可以降低。
为实现本发明的目的， 我们给出一种制造含有复合缓冲层半导体器件的方法， 它包括的步骤是： .
在第一种导电类型的第一块半导体片上覆盖第一图案的第一掩膜， 所述第一图 案的第一掩膜使半导体表面有些地方有掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除无掩膜覆盖的半导体部分， 形成第一个镶嵌状的有第一个深度的槽， 它有底部及边墙；
在含有第一个镶嵌状的槽的第一块半导体片上， 在其槽的边墙上形成一个薄的 介质层， 和 /或在其槽的底部形成一个薄的介质层， 和 /或在槽的外部的半导 _体表面形 成一个薄的介质层；
在第二种导电类型的第二块半导体片上用第二图案的第二掩膜覆盖， 所述第二 图案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底 部形成的图案一致；
腐蚀去除第二块半导体片上无掩膜覆盖的半导体部分， 形成第二个镶嵌状的槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
在含有第二个镶嵌状的槽的第二块半导体片上， 在其槽的边墙上形成一个薄的 介质层， 和 /或在其槽的底部形成一个薄的介质层， 和 /或在槽的外部的半导体表面形 成一个薄的介质层； ·
将已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半 导体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部 的半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成 为一块半导体片；
所述合成的一块半导体片中的第一个深度的槽内形成了复合缓冲层。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中制造的介质层是二氧 化硅。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中所述含有第一个镶嵌 状的槽的第一块半导体片以及含有第二个镶嵌状的槽的第二块半导体片上， 在槽的 边墙、 底部及槽的外部的半导体表面都形成一个薄的介质层。
所述的一种制造含有复合缓冲层半导.体器件的方法， 其中所述含有第一个镶嵌 状的槽的第一块半导体片上， 在其槽的边墙上形成一个薄的介质层。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中所述含有第一个镶嵌 状的槽的第一块半导体片上， 在其槽的边墙上及槽的底部形成一个薄的介质层。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中所述含有第二个镶嵌 状的槽的第二块半导体片上， 在其槽的边墙上形成一个薄的介质层。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中所述含有第二个镶嵌 状的槽的第二块半导体片上， 在其槽的边墙上及槽的底部形成一个薄的介质层。
本发明提出的另一种不含介质层的制造含有复合缓冲层半导体器件的方法， 所 包括的步骤是： 在第一种导电类型的第一块半导体片上覆盖第一图案的第一掩膜， 所述第一图 案的第一掩膜使半导体表面有些地方有掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除无掩膜覆盖的半导体部分， 形成第一个镶嵌状的有第一个深度的槽， 它有底部及边墙；
在第二种导电类型的第二块半导体片上用第二图案的第二掩膜覆盖， 所述第二 图案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底 部形成的图案一致；
腐蚀去除第二块半导体片上无掩膜覆盖的半导体部分， 形成第二个镶嵌状的槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
将已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半 导体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部 的半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成 为一块半导体片；
所述合成的一块半导体片中的第一个深度的内槽形成了复合缓冲层。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中形成第一个镶嵌状的 槽的步骤是采用各向异性的腐蚀方法。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中形成第二个镶嵌状的 槽的步骤是采用各向异性的腐蚀方法。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中第一块半导体片及第 二块半导体片材料都是硅材料。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中所述第一种导电类型 的第一块半导体片是含有第一种导电类型的第一外延层以及重掺杂的第一种导电类 型的衬底， 所述第一个镶嵌状的槽是形成于第一外延层内， 所述第一外延层的厚度 接近于所述槽的第一个深度。
所述的一种制造含有复合缓冲层半导体器件的方法， 其中所述第二种导电类型 的第二块半导体片是含有第二种导电类型的第二外延层以及重掺杂的第二种导电类 型的衬底， 所述第二个镶嵌状的槽是形成于第二外延层内， 所述第二外延层的厚度 接近于所述的槽的第一个深度。
本发明还公开了一种含有复合缓冲层的半导体器件， 其中在第一种导电类型的 第一块半导体片上覆盖有第一图案的第一掩膜， 所述第一图案的第一掩膜使半导体 表面有些地方有掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除的无掩膜覆盖的半导体部分， 有第一个镶嵌状的第一个深度的槽， 它 有底部及边墙； ' 在含有第一个镶嵌状的槽的第一块半导体片上， 在其槽的边墙上有一个薄的介 质层， 和 /或在其槽的底部有一个薄的介质层， 和 /或在槽的外部的半导体表面有一个 薄的介质层；
在第二种导电类型的第二块半导体片上覆盖有第二图案的第二掩膜， 所述第二 图案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底 部形成的图案一致； '
腐蚀去除的第二块半导体片上无掩膜覆盖的半导体部分， 具有第二个镶嵌状的 槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
在含有第二个镶嵌状的槽的第二块半导体片上， 在其槽的边墙上有一个薄的介 质层， 和 /或在其槽的底部有一个薄的介质层， 和 /或在槽的外部的半导体表面有一个 薄的介质层；
已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半导 体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部的 半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成为 一块半导体片；
所述合成的一块半导体片中的第一个深度之内具有复合缓冲层。
本发明还公幵了一种含有复合缓冲层的半导体器件， 其中在第一种导电类型的 第一块半导体片上覆盖有第一图案的第一掩膜， 所述第一图案的第一掩膜使半导体 表面有些地方有掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除的无掩膜覆盖的半导体部分， 具有第一个镶嵌状的第一个深度的槽， 它有底部及边墙；
在第二种导电类型的第二块半导体片上覆盖有第二图案的第二掩膜， 所述第二 图案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底 部的图案一致；
腐蚀去除的第二块半导体片上无掩膜覆盖的半导体部分， 具有第二个镶嵌状的 槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半导 体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部的 半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成为 一块半导体片；
所述合成的一块半导体片中的第一个深度之内具有复合缓冲层。
综上所述， 本发明提出一种简易的 CB层制造方法， 它不需要多次外延， 多次离 子注入， 多次光刻， 因此其制造成本可以降低。 附图的简要说明
图 1 (a)和图 1 (b)为制造 CBM0SFET (或超结器件） 的现有技术的示意图； 图 2 (a)和图 2 (b)为本发明涉及的有介质隔开和无介质隔开的两类典型 RM0ST 的示意图；
图 3 (a)至图 3 (d)为图 2 (b)的剖面线 II - II '的剖面的图案安排；
图 4 (a)至图 4 (h)为本发明的制造过程;
图 5为用本发明的方法制造 CB二极管的一个示意图；
图 6为用本发明的方法制造高反压 CB二极管的一个示意图；
图 7为用本发明的方法制造 CB 双极型晶体管的一个示意图；
图 8 为用本发明的方法制造的 p区与 n区没有介质层的 CB耐压层的 VDM0ST 的一个示意图；
图 9 (a)至图 9 ( b ) 为用本发明的方法制造的 p区与 n区之间有介质层且 p区 与 n+漏区之间有介质层的 CB耐压层的 VDM0ST的一个示意图； 图 10 为用本发明的方法制造的 p区与 n区之间有介质层且 p区与 n+漏区之间 有介质层的 RM0ST的一个示意图；
图 11 为用本发明的方法制造的 p区与 n区之间有介质层但 p区与 n+漏区之间 无介质层的 RM0ST的一个示意图；
图 12 为用本发明的方法制造的与图 8相似但 p区下面变成 n区的 CB耐压层的
VDM0ST的一个示意图。 实现本发明的最佳方式
本发明提供制造 CBM0SFET或超结（Super-Junct i on)器件的一种方法。
最近制造出一种新颖的 M0SFET, 称为 C00LM0ST , 由于其优异的电特性， 突破了 传统功率器件中导通电阻与击穿电压间的关系， 被称作是功率器件的里程碑。 实际 上， C00LM0ST 中所用的耐压层是基于中国发明专利 ZL91 101845. X及美国发明专利 5, 216, 275中提出的六角形图案的 CB结构。此种器件也被称为 CBM0SFET或超结器件 (Super-Junction Devi ces)。
用本发明所制造的器件含有一个第一导电类型材料的接触层， 它可以是 n+型半 导体也可以是 P+型半导体， 但在本发明中用 n+型半导体来加以说明。 在这个接触层 上造有许多个多角形元胞， 每一个元胞具有一个含器件特征区域的器件特征层， 器 件特征层起第二种导电类型材料的作用， 它可以起 P+型半导体的作用， 也可以起 n+ 型半导体的作用， 但在本发明中用 p+型半导体来加以说明。 在器件特征层及接触层 之间有一个复合缓冲层（Compos i te Buffer Layer) , 简称 CB层。 CB层中含有第一种 导电类型材料构成的第一半导体区， 此第一种导电类型的材料可以是 n型半导体也 可以是 P型半导体， 但在本发明中用 n型导电材料来说明。 CB层中还含有第二种导 电类型材料构成的第二半导体区， 此第二种导电类型的材料可以是 p型半导体也可 以是 n型半导体， 但在本发明中用 p型导电材料来说明。 CB层中的第一种半导体区 和第二种半导体区是交替排列的。 CB层中第一种半导体区和第二种半导体区之间还 可以有一个薄的介质层（di el ectri c layer)将第一种半导体区和第二种半导体区隔 幵。 CB层中的第二种半导体区与接触层之间也可以有一个薄的介质层将第二种半导 体区与接触层隔开。
本发明提供此种半导体器件的制造方法， 它主要包含下述步骤：
首先， 在一个有第一外延层的第一块半导体片 （wafer ) 上覆盖掩膜， 再用光刻 或其它方法去除掩膜中的某些部分， 形成一定图案的第一掩膜， 称为第一图案的第 一掩膜。 所述第一图案的第一掩膜是指半导体表面有些地方有掩膜覆盖而除这些地 方外无掩膜覆盖。
然后腐蚀去除第一块半导体片上的第一外延层的无掩膜的部分， 形成一个第一 镶嵌图案， 此图案含有槽， 此槽有边墙和底部，槽深为第一深度。在此腐蚀步骤之后， 可以在槽的边墙形成介质层， 也可以在槽的底部也形成介质层。 也可以在第一块半 导体片上的第一外延层无槽的部分 （即未经刻槽的半导体片表面） 也形成介质层。 或者， 也可以全部没有介质层。 在第一块半导体片的槽的底部形成第二个图案。
在第二种导电类型的第二块半导体片上覆盖掩膜， 再用光刻或其它方法去除掩 膜中的某些部分， 形成第二图案的第二掩膜。 所述第二图案的第二掩膜使第二块半 导体片上有掩膜覆盖的地方和第一块半导体片的槽的底部形成的图案一致。
腐蚀去除第二块半导体片上无掩膜覆盖的半导体部分， 形成第二个镶嵌状的槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深。
在含有第二个镶嵌状的槽的第二块半导体片上， 可以在其槽的边墙上形成一个 薄的介质层， 也可以在其槽的底部形成一个薄的介质层， 也可以在槽的外部的半导 体表面形成一个薄的介质层。 或者， 也可以全部没有介质层。
将已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半 导体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部 的半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成 为一块半导体片。 这一块半导体片中在第一个深度之内形成了复合缓冲层。
在中国发明专利 ZL91101845. X及美国发明专利 5， 216, 275中提出， CB结构有许 多种类型， 图 2 (a)和图 2 (b)示出其中的两种含 CB结构的 RM0ST的情形， 一种是 p 型区 24与 n型区 25之间没有介质层隔开， 如图 2 (a)所示。 另一种是 p型区 24与 n 型区 25之间有薄介质层 26隔开， 且 p型区 24与 n+型衬底 23之间有薄介质层 27隔 幵， 如图 2 (b)所示。 图中 28是 n+源区， 29是源衬底区， 30是栅氧化层。
图 3 (a)至图 3 (d)为给出图 2 (b)的断面线 II - II '上 n区及 p区的四种图案安排。 其中， 虚线左面的区域代表有源区， 箭头 48 代表从有源区边界到终端的方向。 24 代表 CB结构中的 p区， 25代表 CB结构中的 n区， 26代表 CB结构中的 p区及 n区 之间的薄介质层。
所述第一图案的第一掩膜是指半导体表面有些地方有掩膜覆盖而除这些地方外 无掩膜覆盖。 对于图 3 (a)至图 3 (d)中的叉指条图案， 方形图案， 镶嵌方格子图案及 六角形密堆积图案的四种 CB结构， 第一掩膜覆盖的区域就分别象图 3 (a)至图 3 (d) 中四个图的 n型区。 换言之， 做哪一种图的 CB结构， 第一图案就如同哪一种图中的 n 型区。
下面结合图 4 (a)至图 4 (h)说明本发明的制造 CB层的方法， 具体如下： 开始是用如图 4 (a)的一块材料， 它是由 n+衬底 23上长了一个 n型外延层 31形 成， 此外延层可以是在衬底上先用 HC1 之类气体在真空下高温清洗表面， 然后在高 温下暴露在硅烷 （可用氢气携带） 之下， 将硅沉积在 n+衬底 23上。
然后在 n型外延层 31上用掩膜进行光刻， 使图 3 (a)至图 3 (d)所示的 p区 24无 掩膜。 再用各向异性的腐蚀方法将 n型外延层 31上无掩膜的部分进行刻蚀， 从而在 n型外延层 31上形成槽， 结果如图 4 (b)所示。 图 4 (b)的槽的边墙为倾斜的。 此边墙 以愈直为愈好。 因此宜采用选择性强的各向异性的腐蚀方法。 槽深可以直到 η+衬底 23， 也可以略高于 η+衬底 23。
在完成刻槽后， 可以在硅片上形成一个薄介质层覆盖， 例如热生长二氧化硅 ( Si02) ， 结果如图 4 (c)所示。 该图中 n区 25边墙上的介质层及无槽区的半导体表 面的介质层用 33表示， 底部的介质层用 32表示。
将另一块 P型半导体片， 它是由 p+衬底 29上长了一个 p型外延层 34构成， 如 图 4 (d)所示， 在 p型外延层 34上用掩膜进行光刻， 使图 3 (a)至图 3 (d)所示的 n区 25无掩膜， 再用各向异性腐蚀的方法将 p型外延层 34上无掩膜的部分进行刻蚀， 从 而在 P型外延层 34上形成槽， 结果如图 4 (e)所示。 这里， 也可像图 4 (c)那样热生 长氧化层， 结果如图 4 (f)所示， 该图中 P区 24边墙上的介质层及无槽区的半导体表 面的介质层用 36表示， 底部的介质层用 35表示。
在上述过程中， 对 p型半导体片所用的掩膜当然应设计得使图 4 (f)的顶部恰好 适合图 4 (c)的槽的底部， 图 4 (c)的顶部恰好适合图 4 (f)的槽的底部， 而且两个槽的 高度也一致。
两个半导体片都准备好后， 把它们图案对准， 如图 4 (g)所示。 然后使图 4 (f)的 顶部与图 4 (c)槽的底部相接， 加热到约 1 100° (：， 使两半导体片直接键合（Wafer Direct Bonding) , 或通过氧化层而键合。
最后，将 P+衬底 29未刻蚀槽的部分经过磨、拋或化机抛光（Chemi cal Mechani cal Pol i shing) , 暴露出如图 3 (a)至图 3 (d)所示的那样的面， 如图 4 (h)所示， 在槽的深 度范围内就是 p区与 n区交替排列的 CB层。
刻槽方法是半导体工业中常用的方法，考虑到化学腐蚀或反应离子刻蚀等方法中常有 的侧向腐蚀， 因此第二块半导体片的掩膜图案可能要略大于第一块半导体片槽底部的图 案， 以使得最后两块半导体片能够处处紧密接合。
所述做 CB层的方法中， 如果两块半导体片均无介质层， 而且第二块 p型半导体 片是 p+衬底 29上有 p型外延层 24的半导体片， 其上的槽深接近于外延层的厚度， 那么再做阳极接触 A及阴极接触 K， 就做成了 CB二极管， 如图 5所示。 这时， 上述 最后一步对半导体片的磨、 抛不需要将图 3的图案露出， 而是留下一部分 p+层 29。
图 6给出用本发明方法做的高反压 CB二极管的另一个例子。 这里第一块半导体 片及第二块半导体片上均没有外延层， 两块半导体片均为非重掺杂的单晶， 两块半 导体片的槽深均应略大于要求的耐压层厚度。 两块半导体片接合后， 将两边有槽部 分之外均经磨、 抛去除， 形成图中 47部分。 然后再在两边淀积 p+区与 n+区， 这种 p+ 区与 n+区可以是采用图中上面淀积 p+多晶半导体 38， 下面淀积 n+多晶半导体 37， 使 两种多晶半导体激光加热再结晶而形成。 p+区与 n+区甚至可以用适当的金属替代， 而 做成肖特基 （Schottky)结。
下面所述制造含 CB耐压层器件的例子中， 导通时均是电子导电， 如果是双极型 晶体管， 则发射极 E联的是 n+发射区， 基极 B联的是 p基区， 集电极 C联的是底部 n+区。 如果是 MOST , 则源极 S联的是 n+源区及 p+源衬底区， 漏极 D联的是 n+衬底， 在各器件结构的示意图中， 只画出一个元胞的截面。
图 7给出用本发明的方法制造含 CB耐压层的双极型晶体管的一个例子。 这里第 一块半导体片是 n+衬底 23上有一个 n型外延层 25， 刻槽到接近外延层的深度， 第二 块半导体片是 P+衬底 29上有一个厚度接近于第一块半导体片槽深的 p型外延层 24， 而且第二块半导体片的槽深也与第一块半导体片的槽深一样。 第二块半导体片没有 介质层。 第一块半导体片的无槽的表面也没有介质层。 两块半导体片结合后， p+衬底 29直接与 n区 25联结。 经磨、 抛后成为图中 40的部分。 再做 n+发射区 39和发射极 E， 基极 B及集电极 C的金属接触及联线。
第一块半导体片顶部没有介质层是很容易做到的。 例如， 在第一块半导体片覆 盖介质时将第一块半导体片的顶部做有掩蔽， 在覆盖介质后又将此掩蔽去除， 又例 如， 在第一块半导体片全部覆盖介质后将其表面磨、 抛， 使顶部介质去除。
图 8给出用本发明制造含 CB耐压层的 VDM0ST的一个例子。 这里第二块半导体 片是 P+衬底 29上有一个厚度小于第一块半导体片槽深的 p型外延层 24。而第二块半 导体片的槽深与第一块半导体片的槽深一样， 两块半导体片均没有介质层。 将结合 后的半导体片的 P+衬底经磨抛去除直到露出第一块半导体片的 n型外延层为止， 形 成如图 8中 41的部分。 然后做器件的有源区， 包括 n+源区 28， 栅氧化层 30， 栅电 极0， 源极 S及漏极 D。
图 9 ( a ) 和图 9 (b)给出用本发明的方法制造有介质层的 CB耐压层做 VDM0ST的 两个例子。 设 p区 24与 n区 25及 n+漏区 23之间都有介质。 至少有两种方法实现器 件特征层： 一种如图 9 (a)所示， 源的电极接触不仅是与 n+源区 28及 p+源衬底区 42 相联接， 而且还必须与 p区 24的顶部相联； 另一种如图 9 (b)所示， 其中每个 n区顶 部被其两旁源衬底的 p+区 42所夹的颈比图 9 (a)为宽， 从而导通电阻可进一步降低。 但是， 对这种情形， 需要首先将 n区 25与 p区 24之间的最上面的介质层去除。 例 如用化学腐蚀的方法。 然后再在去除之处填上多晶半导体， 再用激光加热使这部分 再结晶为单晶， 再结晶的部分 43在图 .9 (b)中是用交叉阴影区來表示的。
下面再对两个半导体片相对键合时有介质层将 CB层中 p区与其旁边的 n区及 p 区与 n+接触层隔幵的晶体管的情形进行讨论。
有介质层的情形相比无介质层的情形具有如下一些特殊的优点： 1)在图 2 (a)的 情形， 当在 C点的横向电场很高时， 击穿电压无法再提高。 其击穿是沿图中虚线 44 所示的电力线。 在有介质层的图 2 (b)的情形， 决定击穿电压的碰撞电离率的积分只 沿其上部的电力线 45 (在 p型区 24内）或其下部的电力线 46 (在 n型区 25内）， 因此 击穿电压可以提高。 或在同样击穿电压下， n区 25及 p区 24的惨杂可以更重， 从而 导通电阻降低。 2)有介质层的情形在制作 CB层时， 可选择介质层来阻挡 CB层中 n 区及 P区中杂质在高温过程中的扩散， 使制造中控制变得容易。 3)半导体如为 S i， 则有介质层（例如 Si02层）的硅片键合是 Si- Si02- S i键合， 这种键合比 Si- Si直接键 合容易做得更好。
但是有介质层的 CBM0SFET 如不釆取一定措施， 则是一个常开型（Normal ly- on) 器件， 理由如下：
半导体器件在高反偏压下的厚耗尽层内的复合中心会产生电子 -空穴对， 按照肖 克莱-里德-霍耳（Shockl ey-Read-Hal 1 )理论， 电子-空穴对产生的电流密度可用 qniW/ ( 。+ T p。）表示， 其中 τ„。及 τ ρ。分别是小讯号电子与空穴的寿命， ni是本征载 流子浓度， W是耗尽层厚度， q是电子电荷。 在器件关断时， p区 24产生的空穴可被 电场扫向 P+源衬底区 29。 而 p区 24产生的电子在 p区 24直接与 n+漏区 23相联时， 如图 2 (a)所示， 则可扫向该 n+漏区 23。 但是如果在 p区 24与 n+漏区 23及 n区 25 之间有介质层存在， 如图 2 (b)所示， 则电子会在 p区 24的最下面与 n区 25相近邻 的地方不断堆积。 这些堆积的电子会造成一个反型层， 此反型层的负电荷改变了电 场分布， 从而使击穿电压下降。
实际上， 所述电子漏电流的作用很容易去除， 措施是将所有的 P区 24相联。 然 后在有源区之外的终端区将 p区 24与 n+漏区 23直接相联。 图 3 (a)至图 3 (d)的箭头 48示出从有源区向终端的方向。
当然， 如果 CB层中 p区底部与 n+漏区的每个元胞中直接相联， 所述漏电子流的 作用就会直接去除。 这不仅要求第二块半导体片无槽区的表面无介质覆盖， 还要求 第一块半导体片槽的底部没有介质。 后一个要求可以用 RIE (反应离子侵蚀法）或其 它方法结合用掩膜来达到。
图 10给出用本发明的方法制造有介质层的 RM0ST的一个例子。 在第一块有 n型 外延层并刻了槽的半导体片与第二块有 p型外延层并刻了槽的半导体片接合后， 第 二块 p+衬底 29并不全部磨去， 而是保留图中 p+区 49的一个厚度。 然后在 n区 25上 方刻出一个槽， 刻槽时将该介质层也刻去。 然后淀积 n 型半导体于槽的底部， 如图 中 50的部分。 这样 n型区 25顶部实际上通过 n区 50与 p+型区 29直接相联。 然后 可用常规方法制造 RM0ST。
图 11给出用本发明的方法制造 RM0ST的又一个例子。 这里要求第一块半导体片 有 n+衬底及 n型外延层， 第二块半导体片有 p+衬底及 p型外延层。 还要求第一块半 导体片的槽的底部及槽外的表面无介质层， 第二块半导体片槽的底部及槽外的表面 也无介质层。 两块半导体片接合后形成图中 51的厚度区域， 然后在 p+区 29形成 n+ 源区 28， 再刻槽， 然后再做栅氧化层 30及电极。
在 CB结构中， p区与 n+衬底界面的中央往往会产生最大的电场。 为了进一步提 高击穿电压， 可使 p区 24下面的受主浓度比上面的低， 甚至在 p区 24最下面从 p 型逐渐转为 n型。 其结构的一个例子如图 12所示， 它和图 8的不同之处只是在 p区 最下面一部分变成轻惨杂 n型区 52。 用本发明的思想也可以这样来做， 即将第二块 P+衬底上有 p型外延层的半导体片的顶部再做 n型外延层。 或者， 再扩散 n型杂质， 使得第二块片的表面是 n型。 其它方法和做图 8的器件一样。
对硅 （Si ) 器件而言， 上面所述的介质层可以是一个 S i02层， 也可以是别的介 质层， 即使是在 S i的表面长了氧化层， 还可以覆盖别的介质层。 后一种介质层宜釆 用介电系数高且能使硅片结合得好的材料， 介电系数高则对 CB层中的 n区电离施主 的正电荷产生的电通量线在横向被 P 区电离受主的负电荷产生的电通量线所终止的 效果（即电荷补偿效应）不会产生不良的影响。
上面对利用本发明制造器件的方法作了许多实例说明。 显然对于本领域的普通 技术人员而言， 还可以在本发明的思想指导下， 作出多种变化及多种器件， 因此， 凡在本发明的精神范围内所作的一些显而易见的变化， 都应包括在本发明的权利要 求的保护范围内。 工业应用性
本发明提出一种简易的 CB层制造方法， 它不需要多次外延， 多次离子注入， 多 次光刻， 因此其制造成本可以降低。

Claims

权 利 要 求
1. 一种制造含有复合缓冲层半导体器件的方法， 所包括的步骤是：
在第一种导电类型的第一块半导体片上覆盖第一图案的第一掩膜， 所述第一图案 的第一掩膜使半导体表面有些地方有掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除无掩膜覆盖的半导体部分， 形成第一个镶嵌状的有第一个深度的槽， 它 有底部及边墙；
在含有第一个镶嵌状的槽的第一块半导体片上， 在其槽的边墙上形成一个薄的介 质层， 和 /或在其槽的底部形成一个薄的介质层， 和 /或在槽的外部的半导体表面形成 一个薄的介质层；
在第二种导电类型的第二块半导体片上用第二图案的第二掩膜覆盖， 所述第二图 案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底部 形成的图案一致；
腐蚀去除第二块半导体片上无掩膜覆盖的半导体部分， 形成第二个镶嵌状的槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
在含有第二个镶嵌状的槽的第二块半导体片上， 在其槽的边墙上形成一个薄的介 质层， 和 /或在其槽的底部形成一个薄的介质层， 和 /或在槽的外部的半导体表面形成 一个薄的介质层；
将已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半 导体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部的 半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成为一 块半导体片；
所述合成的一块半导体片中的第一个深度之内形成了复合缓冲层。
2. 按照权利要求 1所述的一种制造含有复合缓冲层半导体器件的方法， 其中制 造的介质层是二氧化硅。
3. 按照权利要求 1所述的一种制造含有复合缓冲层半导体器件的方法， 其中所 述含有第一个镶嵌状的槽的第一块半导体片以及含有第二个镶嵌状的槽的第二块半 导体片上， 槽的边墙、 底部及槽的外部的半导体表面都形成一个薄的介质层。
4. 按照权利要求 1所述的一种制造含有复合缓冲层半导体器件的方法， 其中所 述含有第一个镶嵌状的槽的第一块半导体片上， 在其槽的边墙上形成一个薄的介质 层。
5. 按照权利要求 1所述的一种制造含有复合缓冲层半导体器件的方法， 其中所 述含有第一个镶嵌状的槽的第一块半导体片上， 在其槽的边墙上及槽的底部形成一个 薄的介质层。
6. 按照权利要求 1所述的一种制造含有复合缓冲层半导体器件的方法， 其中所 述含有第二个镶嵌状的槽的第二块半导体片上， 在其槽的边墙上形成一个薄的介质 层。
7. 按照权利要求 1所述的一种制造含有复合缓冲层半导体器件的方法， 其中所 述含有第二个镶嵌状的槽的第二块半导体片上， 在其槽的边墙上及槽的底部形成一个 薄的介质层。
8. 一种制造含有复合缓冲层半导体器件的方法， 所包括的歩骤是： 在第一种导电类型的第一块半导体片上覆盖第一图案的第一掩膜， 所述第一图案 的第一掩膜使半导体表面有些地方有掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除无掩膜覆盖的半导体部分， 形成第一个镶嵌状的有第一个深度的槽， 它 有底部及边墙；
在第二种导电类型的第二块半导体片上用第二图案的第二掩膜覆盖， 所述第二图 案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底部 形成的图案一致；
腐蚀去除第二块半导体片上无掩膜覆盖的半导体部分， 形成第二个镶嵌状的槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
将已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半 导体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部的 半导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成为一 块半导体片；
所述合成的一块半导体片中的第一个深度之内形成了复合缓冲层。
9. 按照权利要求 1或 8所述的一种制造含有复合缓冲层半导体器件的方法， 其 中形成第一个镶嵌状的槽的歩骤是釆用各向异性的腐蚀方法。
10. 按照权利要求 1或 8所述的一种制造含有复合缓冲层半导体器件的方法， 其 中形成第二个镶嵌状的槽的步骤是采用各向异性的腐蚀方法。
1 1 . 按照权利要求 1或 8所述的一种制造含有复合缓冲层半导体器件的方法， 其 中第一块半导体片及第二块半导体片材料都是硅材料。
12. 按照权利要求 1或 8所述的一种制造含有复合缓冲层半导体器件的方法， 其 中所述第一种导电类型的第一块半导体片是含有第一种导电类型的第一外延层以及 重掺杂的第一种导电类型的衬底， 所述第一个镶嵌状的槽是形成于第一外延层内， 所 述第一外延层的厚度接近于所述槽的第一个深度。
13. 按照权利要求 1或 8所述的一种制造含有复合缓冲层半导体器件的方法， 其 中所述第二种导电类型的第二块半导体片是含有第二种导电类型的第二外延层以及 重惨杂的第二种导电类型的衬底， 所述第二个镶嵌状的槽是形成于第二外延层内， 所 述第二外延层的厚度接近于所述的槽的第一个深度。
14. —种含有复合缓冲层的半导体器件， 其中在第一种导电类型的第一块半导体 片上覆盖有第一图案的第一掩膜， 所述第一图案的第一掩膜使半导体表面有些地方有 掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除的无掩膜覆盖的半导体部分， 有第一个镶嵌状的第一个深度的槽， 它有 底部及边墙；
在含有第一个镶嵌状的槽的第一块半导体片上， 在其槽的边墙上有一个薄的介质 层， 和 /或在其槽的底部有一个薄的介质层， 和 /或在槽的外部的半导体表面有一个薄 的介质层；
在第二种导电类型的第二块半导体片上覆盖有第二图案的第二掩膜， 所述第二图 案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底部 形成的图案一致；
1 腐蚀去除的第二块半导体片上无掩膜覆盖的半导体部分， 具有第二个镶嵌状的 槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
在含有第二个镶嵌状的槽的第二块半导体片上， 在其槽的边墙上有一个薄的介质 层， 和 /或在其槽的底部有一个薄的介质层， 和 /或在槽的外部的半导体表面有一个薄 的介质层；
已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半导 体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部的半 导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成为一块 半导体片；
所述合成的一块半导体片中的第一个深度之内具有复合缓冲层。
15. 一种含有复合缓冲层的半导体器件， 其中在第一种导电类型的第一块半导体 片上覆盖有第一图案的第一掩膜， 所述第一图案的第一掩膜使半导体表面有些地方有 掩膜覆盖而除这些地方外无掩膜覆盖；
腐蚀去除的无掩膜覆盖的半导体部分， 具有第一个镶嵌状的第一个深度的槽， 它 有底部及边墙；
在第二种导电类型的第二块半导体片上覆盖有第二图案的第二掩膜， 所述第二图 案的第二掩膜使第二块半导体片上有掩膜覆盖的地方和第一块半导体片的槽的底部 的图案一致；
腐蚀去除的第二块半导体片上无掩膜覆盖的半导体部分， 具有第二个镶嵌状的 槽， 它有底部、 边墙， 并有一个接近于第一个深度的槽深；
已形成槽的第二块半导体片的槽的外部的半导体表面与已形成槽的第一块半导 体片的槽的底部对接， 第二块半导体片的槽的底部与第一块半导体片的槽的外部的半 导体表面对接， 两块半导体片的槽的边墙与边墙对接， 使两块半导体片接合成为一块 半导体片；
所述合成的一块半导体片中的第一个深度之内具有复合缓冲层。
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US7192872B2 (en) 2007-03-20

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