WO2003010820A1 - Circuit integre hybride analogique/numerique - Google Patents

Circuit integre hybride analogique/numerique Download PDF

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Publication number
WO2003010820A1
WO2003010820A1 PCT/JP2002/006974 JP0206974W WO03010820A1 WO 2003010820 A1 WO2003010820 A1 WO 2003010820A1 JP 0206974 W JP0206974 W JP 0206974W WO 03010820 A1 WO03010820 A1 WO 03010820A1
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WO
WIPO (PCT)
Prior art keywords
circuit
analog
digital
semiconductor chip
integrated circuit
Prior art date
Application number
PCT/JP2002/006974
Other languages
English (en)
Japanese (ja)
Inventor
Munehiro Karasudani
Original Assignee
Niigata Seimitsu Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Publication of WO2003010820A1 publication Critical patent/WO2003010820A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0827—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of electromagnetic or electrostatic field noise, e.g. preventing crosstalk by shielding or optical isolation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Definitions

  • the present invention relates to an analog / digital hybrid integrated circuit in which an analog circuit and a digital circuit are integrated on one semiconductor chip.
  • wireless communication enables "anytime, anywhere, anybody" communication.
  • Means for wireless communication include mobile phone devices and PDAs, as well as short-range wireless data communication technology bluetooth and wireless LAN using the 5 GHz band.
  • wireless communication terminals are assumed to be easily portable. Therefore, small size, light weight and low power consumption are strongly required.
  • wireless communication terminals tend to be multifunctional and highly functional. Nevertheless, the equipment as a whole is required to be small, lightweight and low power consumption. Therefore, the wireless communication function built into the device needs to be even smaller, lighter, thinner and lower power consumption.
  • a radio circuit for transmitting and receiving analog signals
  • a PLL Phase Lock Lock Loop
  • digital circuit digital circuit
  • PLL Phase Lock Lock Loop
  • parasitic capacitances and parasitic inductances are generated between wiring and components, and this causes coupling noise.
  • Wireless communication terminals such as radio receivers, mobile phone devices, bluetooth, and wireless LANs use very high frequency bands. As the frequency increases, any parasitic capacitance components begin to form a path for coupling noise. High-frequency current flowing through the wiring generates a magnetic field. As a result, dielectric coupling noise becomes apparent.
  • the effective impedance increases, making it easier to ride noise.
  • the loss on the transmission path is also very large. For example, in a high-frequency signal receiving unit, if there is a loss in the high-frequency circuit near the radio wave entrance, the receiving sensitivity will decrease, and it will not be possible to recover even if the gain is increased in subsequent circuits. Also, if there is a loss in the high-frequency circuit near the exit of the radio wave that handles high power in the high-frequency signal transmitter, the high-frequency power is not only converted to heat and wasted, but also increases in temperature. In some cases, this can lead to component failure.
  • analog circuits and digital In the case of analog / digital mixed integrated circuits, analog circuits and digital This means that the circuits are arranged closer to each other as compared to a case where the circuit is configured on a separate chip. Therefore, large noise of the digital circuit often enters the highly sensitive analog circuit. In this case, the characteristics of the analog signal are greatly deteriorated. Therefore, it is very important how to reduce the coupling noise between the analog circuit and the digital circuit.
  • the present invention has been made in view of such circumstances, and has been made to be able to suppress noise generated in an analog circuit, particularly a high-frequency circuit portion, and to reduce loss on a transmission line.
  • the purpose is to do.
  • An analog / digital hybrid integrated circuit is an analog / digital hybrid integrated circuit in which an analog circuit for performing processing relating to a signal in a desired frequency band and a digital circuit are mounted on the same semiconductor chip.
  • a circuit that operates in accordance with a clock is arranged at approximately the center of the.
  • the circuit that operates according to the clock is a circuit that operates intermittently according to the clock.
  • the circuit operating according to the clock is any one of a D / A converter, an A / D converter, a PLL circuit, and a baseband signal processing circuit or a combination thereof. I do.
  • an analog circuit for performing processing relating to a signal in a desired frequency band and a digital circuit are mounted on the same semiconductor chip.
  • a digital / digital hybrid integrated circuit in which a circuit which operates according to a clock having a period long enough to operate the analog circuit between edges is arranged substantially at the center of the semiconductor chip. It is characterized by the following.
  • the analog circuit is arranged in a peripheral portion of the semiconductor chip.
  • an analog / digital hybrid integrated circuit in which an analog circuit for performing processing relating to a signal in a desired frequency band and a digital circuit are mounted on the same semiconductor chip, The above-mentioned analog circuit is arranged in the section.
  • the analog circuit disposed in the peripheral portion of the semiconductor chip is a high-frequency circuit that performs processing on a high-frequency signal in a desired frequency band.
  • the wiring length is long from the pad provided at the peripheral portion of the semiconductor chip to the circuit provided at the substantially central portion of the semiconductor chip, but the circuit disposed at the substantially central portion is Since is a digital circuit, it is possible to reduce the problem of coupling noise generated on the wiring and the loss on the wiring, as compared with the case where the wiring length to the analog circuit, particularly to the high-frequency circuit becomes long.
  • the circuit arranged substantially at the center of the semiconductor chip is a circuit that operates intermittently according to a clock, so that, for example, the analog circuit operates when the circuit is not operating. And the coupling noise between the analog circuit and the circuit can be reduced.
  • the circuit disposed substantially at the center of the semiconductor chip is a circuit that operates according to a clock having a long cycle, a transient state change occurs at the edge of the clock. While the mouth is The analog circuit can be operated in a state where the clock is stable without operating the switching circuit, and it is possible to suppress the inconvenience that switching noise due to the clock is superimposed on a signal in the analog circuit.
  • an analog circuit particularly a high-frequency circuit
  • the wiring length from the pad provided in the periphery of the semiconductor chip to the analog circuit is shortened. Therefore, it is possible to reduce the coupling noise generated on the wiring and the loss on the wiring.
  • the connection to the power supply line and the ground line can be reduced in impedance, and power supply with low noise and low loss can be performed.
  • FIG. 1 is a diagram illustrating a configuration example of a wireless communication device.
  • FIG. 2 is a diagram showing a layout configuration example of each block in an analog / digital hybrid IC chip in which the wireless communication device shown in FIG. 1 is integrated.
  • FIG. 1 is a diagram illustrating a configuration example of a wireless communication device.
  • the wireless communication device shown in Fig. 1 has an antenna 1, an antenna switch 2, a high-frequency amplifier 3, a mixer (mixer) 4, a local oscillator (OSC) 5, an intermediate-frequency amplifier 6, an AZD converter 7, It comprises a baseband signal processing circuit 8, a D / A converter 9, an intermediate frequency amplifier circuit 10, a mixing circuit 11, a power amplifier 12, and an audio signal processing circuit 13.
  • the high-frequency amplifier circuit 3 inputs radio waves received by the antenna 1 via the antenna switch 2 and selectively amplifies a high-frequency signal in a specific frequency band.
  • the mixing circuit 4 and the local oscillation circuit 5 constitute a frequency converter, and the carrier signal of the frequency f e output from the high-frequency amplification circuit 3 and the local oscillation signal of the frequency f t output from the local oscillation circuit 5 preparative mixed, and generates and outputs an intermediate frequency signal ft one f c by performing frequency conversion, without changing the modulation content.
  • the intermediate frequency increasing circuit 6 amplifies the intermediate frequency signal that has passed through the mixing circuit 4.
  • the AZD converter 7 converts the analog intermediate frequency signal output from the intermediate frequency increase circuit 6 into digital data, and outputs the result to the baseband signal processing circuit 8.
  • the baseband signal processing circuit 8 includes a voice CODEC (Corder-Decoder), a DSP (Digital Signal Processor), a memory, and the like, and performs digital data processing such as baseband modulation and error correction.
  • the audio signal processing circuit 13 performs various processes related to the audio signal.
  • the DZA converter 9 performs DZA conversion on the digital data generated by the baseband signal processing circuit 8.
  • the intermediate frequency increase circuit 10 amplifies the analog intermediate frequency signal output from the D / A converter 9.
  • the mixing circuit 11 and the local oscillation circuit 5 constitute a frequency converter, and perform frequency conversion on the intermediate frequency signal output from the intermediate frequency circuit 10 without changing the modulation content to generate a high frequency signal. And output.
  • the power amplifier 12 amplifies a high-frequency signal in a specific frequency band that has passed through the mixing circuit 11.
  • the amplified high-frequency signal is transmitted from the antenna 1 via the antenna switch 2.
  • a high frequency circuit (Radio Frequency: RF circuit) is configured by the high frequency amplifier circuit 3, the mixing circuit 4, the local oscillation circuit 5, the mixing circuit 11, and the power amplifier 12.
  • An intermediate frequency circuit (Intermediate Frequency: IF circuit) is constituted by the intermediate frequency amplifier circuits 6 and 10.
  • FIG. 2 is a diagram showing a layout configuration example of each block in an analog / digital hybrid IC chip in which the wireless communication device shown in FIG. 1 is integrated. As shown in FIG. 2, a plurality of pads 23 are provided around the IC chip 20 for data input / output and a power supply.
  • a core unit Inside the plurality of pads 23, there is a core unit on which analog circuits and digital circuits are integrated.
  • An RF circuit 21, an IF circuit 22, an A / D converter 7, a baseband signal processing circuit 8, a D / A converter 9, and an audio signal processing circuit 13 are integrated in the core unit.
  • a power supply line and a ground line 24 are arranged so as to go around the core portion.
  • the RF circuit 21 includes the high-frequency amplifier circuit 3, the mixing circuit 4, the local oscillation circuit 5, the mixing circuit 11, the power amplifier 12, and the like shown in FIG. Further, the IF circuit 22 includes the intermediate frequency amplifier circuits 6 and 10 shown in FIG. Note that the RF circuit 21 does not necessarily need to have all the above-described configurations.
  • the high-frequency amplifier circuit 3, the local oscillator circuit 5, the power amplifier 12, and the like may be provided as separate chips.
  • the A / D converter 7, the baseband signal processing circuit 8, and the D / A converter 9 are arranged at substantially the center of the IC chip 20.
  • the A / D converter 7, the baseband signal processing circuit 8, and the DZA converter 9 are digital circuits that do not always operate according to a high-speed clock, that is, operate intermittently.
  • the digital circuit having less problems of noise and loss is arranged substantially at the center of the IC chip 20, and the analog circuits such as the RF circuit 21 and the IF circuit 22 are mounted on the IC chip 20. It is located at the periphery of.
  • the wiring length from the pad 23 provided around the IC chip 20 to the analog circuit can be shortened, and the coupling noise generated on the wiring and the loss on the wiring can be reduced. it can.
  • the wiring length from the power supply line and the ground line 24 to the analog circuit can be shortened, the connection between the power supply line and the ground line 24 can be reduced in impedance, and low noise Low-loss power supply can be realized.
  • the baseband signal processing circuit 8 is disposed on the opposite side of the RF circuit 21 and the IF circuit 22 with the A / D converter 7 and the DZA converter 9 interposed therebetween.
  • the baseband signal processing circuit 8 is a digital circuit, if the operation speed is high, it is conceivable that the high-speed digital signal leaks to the outside as radio waves and interferes with communication.
  • the baseband signal processing circuit 8 is arranged as far as possible from analog circuits such as the RF circuit 21 and the IF circuit 22. Therefore, the electromagnetic wave generated by the baseband signal processing circuit 8 is the square of the distance Attenuation is sufficient to reach the RF circuit 21 and the IF circuit 22 at a ratio of 1. Therefore, it is possible to prevent large digital noise from the baseband signal processing circuit 8 from being superimposed on the analog signals handled by the RF circuit 21 and the IF circuit 22. The baseband signal processing circuit 8 and the RF circuit 21 And the coupling noise with the IF circuit 22 can also be reduced.
  • the A / D converter 7, the baseband signal processing circuit 8, and the DZA converter 9 have been described as examples of the circuits arranged at the substantially central portion of the IC chip 20, but all of them are substantially omitted. It is not always necessary to place it in the center.
  • any digital circuit that operates according to a clock can be arranged at a substantially central portion of the IC chip 20.
  • the PLL circuit may be arranged substantially at the center.
  • the baseband signal processing circuit 8 is also arranged at a substantially central portion of the IC chip 20.
  • the baseband signal processing circuit 8 may be arranged at a peripheral portion of the IC chip 20.
  • the baseband signal processing circuit 8 there is a logic part that does not need to operate at the highest clock speed. If there are many analog circuits to be placed around the IC chip 20 and it is not possible to place all of the baseband signal processing circuit 8 around the periphery, the above logic section is cut out and the IC chip 20 is cut out. May be arranged substantially at the center.
  • the operation clock is a long-period clock having a sufficient length between edges.
  • the main cause of noise in an analog / digital hybrid circuit is a switch caused by a transient state change of a transistor that occurs when switching is performed in synchronization with a clock edge in a digital circuit such as a CM ⁇ S inverter. This is tuning noise.
  • the digital circuit located at the approximate center of the IC chip 20 has a long cycle If the digital circuit operates according to the clock, do not operate the analog circuit while the transistor has a transient state change at the edge of the clock, and operate the analog circuit while the clock is stable. be able to. By doing so, it is possible to suppress the inconvenience that switching noise in a digital circuit is superimposed on a signal in an analog circuit.
  • the circuit that performs the audio signal processing is described.
  • the present invention can be applied to a circuit that performs the video signal processing.
  • the analog / digital hybrid integrated circuit having both the transmitting function and the receiving function has been described.
  • the present invention is also applied to the analog / digital hybrid integrated circuit having only one of the transmitting function and the receiving function. It is possible to
  • the wiring length from the peripheral portion of the semiconductor chip to the circuit provided in the substantially central portion is long, but since the circuit disposed in the substantially central portion is a digital circuit, As compared with the case where the wiring length to the circuit becomes longer, the problem of coupling noise generated on the wiring and the loss on the wiring can be reduced.
  • the circuit arranged substantially at the center of the semiconductor chip is a digital circuit that operates intermittently according to a clock, for example, when the digital circuit is not operating, The circuit can operate, and the coupling noise between analog and digital circuits is also reduced. I can do it.
  • the circuit arranged substantially in the center of the semiconductor chip operates according to a long-period clock, a transient state change occurs in the transistor at the edge of the clock.
  • the analog circuit can be operated while the clock is stable while the analog circuit is not operating during the occurrence, and the switching noise due to the clock is prevented from being superimposed on the signal in the analog circuit. Can be.
  • an analog circuit particularly a high-frequency circuit
  • the wiring length from the periphery of the semiconductor chip to the analog circuit can be shortened.
  • the coupling noise generated above, and the loss on the wiring can be reduced.
  • the connection with the power supply line and the ground line can be reduced in impedance, and power supply with low noise and low loss can be performed.
  • the present invention is useful for suppressing a noise generated in a high-frequency circuit portion and reducing a loss on a transmission line.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne des circuits numériques, notamment un convertisseur A/N (7) et un convertisseur N/A (9) disposés à proximité au centre d'une puce de circuit intégré (20) afin d'éviter le bruit du couplage sur le câblage ou une perte sur le câblage même si le câblage s'étend depuis des roulements (23) ménagés sur le pourtour de la puce de circuit intégré (20) en direction des circuits numériques à proximité du centre. Des circuits analogiques, dont un circuit RF (21) et un circuit IF (22) sont disposés sur le pourtour de la puce de circuit imprimé (20) afin de supprimer le bruit du couplage sur le câblage ou la perte sur le câblage par la réduction des câbles partant des roulements (23) en direction des circuits analogiques. Une source d'alimentation peut être connectée à un faible bruit et à une faible perte à l'impédance réduite en vue de sa connexion avec une source d'alimentation et une ligne de terre (24).
PCT/JP2002/006974 2001-07-23 2002-07-10 Circuit integre hybride analogique/numerique WO2003010820A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001220881A JP2003037173A (ja) 2001-07-23 2001-07-23 アナログ・デジタル混載集積回路
JP2001-220881 2001-07-23

Publications (1)

Publication Number Publication Date
WO2003010820A1 true WO2003010820A1 (fr) 2003-02-06

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PCT/JP2002/006974 WO2003010820A1 (fr) 2001-07-23 2002-07-10 Circuit integre hybride analogique/numerique

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JP (1) JP2003037173A (fr)
WO (1) WO2003010820A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8365122B2 (en) 2007-04-30 2013-01-29 Innovations Holdings, L.L.C. Method and apparatus for configurable systems

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200701760A (en) * 2005-02-15 2007-01-01 Niigata Seimitsu Co Ltd Semiconductor device
US8902625B2 (en) * 2011-11-22 2014-12-02 Marvell World Trade Ltd. Layouts for memory and logic circuits in a system-on-chip
JP2014076561A (ja) 2012-10-10 2014-05-01 Seiko Epson Corp 液体吐出装置および液体吐出方法
WO2018088410A1 (fr) 2016-11-11 2018-05-17 株式会社村田製作所 Circuit intégré de commutation, module haute fréquence, et dispositif de communication
JP7392465B2 (ja) * 2019-12-26 2023-12-06 セイコーエプソン株式会社 液体吐出装置、駆動回路、及び集積回路
JP7392466B2 (ja) * 2019-12-26 2023-12-06 セイコーエプソン株式会社 液体吐出装置、駆動回路、及び集積回路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248535A (ja) * 1988-03-29 1989-10-04 Nec Corp セミカスタム集積回路
JPH02102571A (ja) * 1988-10-11 1990-04-16 Nec Corp セミカスタム半導体集積回路
JPH04151863A (ja) * 1990-10-16 1992-05-25 Kawasaki Steel Corp 半導体集積回路装置
JPH08264722A (ja) * 1995-03-20 1996-10-11 Hitachi Ltd 半導体集積回路
JPH09181257A (ja) * 1995-12-25 1997-07-11 Hitachi Ltd 半導体集積回路装置
JPH11238846A (ja) * 1998-02-20 1999-08-31 Rohm Co Ltd 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248535A (ja) * 1988-03-29 1989-10-04 Nec Corp セミカスタム集積回路
JPH02102571A (ja) * 1988-10-11 1990-04-16 Nec Corp セミカスタム半導体集積回路
JPH04151863A (ja) * 1990-10-16 1992-05-25 Kawasaki Steel Corp 半導体集積回路装置
JPH08264722A (ja) * 1995-03-20 1996-10-11 Hitachi Ltd 半導体集積回路
JPH09181257A (ja) * 1995-12-25 1997-07-11 Hitachi Ltd 半導体集積回路装置
JPH11238846A (ja) * 1998-02-20 1999-08-31 Rohm Co Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8365122B2 (en) 2007-04-30 2013-01-29 Innovations Holdings, L.L.C. Method and apparatus for configurable systems

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Publication number Publication date
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