WO2003005431A1 - Suspension de polissage chimico-mecanique destinee a un circuit integre a semi-conducteurs, procede de polissage et circuit integre a semi-conducteurs - Google Patents

Suspension de polissage chimico-mecanique destinee a un circuit integre a semi-conducteurs, procede de polissage et circuit integre a semi-conducteurs Download PDF

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Publication number
WO2003005431A1
WO2003005431A1 PCT/JP2002/006590 JP0206590W WO03005431A1 WO 2003005431 A1 WO2003005431 A1 WO 2003005431A1 JP 0206590 W JP0206590 W JP 0206590W WO 03005431 A1 WO03005431 A1 WO 03005431A1
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WO
WIPO (PCT)
Prior art keywords
copper
integrated circuit
semiconductor integrated
polishing
wiring
Prior art date
Application number
PCT/JP2002/006590
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English (en)
Japanese (ja)
Inventor
Katsuyuki Tsugita
Sachie Shinmaru
Original Assignee
Seimi Chemical Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seimi Chemical Co., Ltd. filed Critical Seimi Chemical Co., Ltd.
Priority to JP2003511299A priority Critical patent/JPWO2003005431A1/ja
Publication of WO2003005431A1 publication Critical patent/WO2003005431A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B24B37/044—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor characterised by the composition of the lapping agent
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09G—POLISHING COMPOSITIONS; SKI WAXES
    • C09G1/00—Polishing compositions
    • C09G1/02—Polishing compositions containing abrasives or grinding agents
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives

Definitions

  • the present invention relates to a chemical mechanical polishing slurry used for a flattening step in the manufacture of a semiconductor integrated circuit having copper wiring, a method of polishing a semiconductor integrated circuit having copper wiring using the slurry, and The present invention relates to a semiconductor integrated circuit having a copper wiring in which a multi-layer wiring is formed by flattening using a slurry.
  • a multilayer wiring structure in which a wiring structure in which a wiring pattern is buried on an insulating layer formed on a substrate is multi-layered has been generalized for higher integration and higher performance.
  • a chemical mechanical polishing method (hereinafter, also referred to as CMP) is an essential technology.
  • the method of forming a semiconductor integrated circuit having copper wiring to which the present invention is applied is to form a copper film by sputtering or plating on the surface of a substrate formed in an arbitrary uneven shape, and then forming an excess copper film.
  • the integrated circuit is formed by polishing and removing the wiring to form copper in the recessed part of the substrate, which is called the damascene method.
  • the integrated circuit having such a flattened structure is intended to have a high capacity by increasing the number of layers.
  • a method is generally used in which a layer serving as a base is formed by being stacked on the integrated circuit having the copper wiring, and further copper wiring is applied to this layer by a damascene method.
  • planarization by surface polishing is an important factor that affects the performance of integrated circuits. It is. At this time, the rotating polishing pad is brought into contact with the unevenness of the copper film by CMP to planarize the integrated circuit surface.
  • a problem that has been considered as a problem is a phenomenon called dipping recess in which copper in a wiring portion softer than a substrate is excessively polished in a polishing process.
  • the wiring thickness becomes thinner and the wiring resistance increases, and the designed performance cannot be obtained.
  • it often causes unevenness and distortion on the next lamination surface, and thus often hinders the flat lamination of integrated circuits in multilayering semiconductor integrated circuits.
  • dishing countermeasure there is a method that specifies the particle size and shape of the abrasive grains applied to the CMP slurry, but in addition to the dicing problem, the generation of scratches on the polished surface and the polishing speed ( (Approximately 200 nm / min or more).
  • CMP slurries in which anthranilic acid and quinaldic acid are added to the slurry for the purpose of planarizing the surface of the semiconductor integrated circuit. These are used in polishing a semiconductor integrated circuit wafer having copper wiring. In this method, polishing was inhibited because a strong copper chelate layer of anthranilic acid and quinaldic acid was formed on the surface of the copper film by reacting with the copper film on the substrate, and it was difficult to obtain a sufficient polishing rate. Furthermore, when the copper cleave layer is peeled off by friction with a pad or the like, polishing proceeds.
  • the copper chelate formed as a strong layer must be removed by friction with the polishing pad, and the copper chelate may strongly adhere to the pad and contaminate the polishing pad. there were.
  • the present invention addresses the problem of dishing, which has long been a problem in semiconductor integrated circuits due to planarization by CMP, with respect to semiconductor integrated circuits having high-density copper wiring required by the market. To be solved ⁇ DISCLOSURE OF THE INVENTION
  • the present inventors have found that the problems of the prior art can be overcome by adding a predetermined amount of copper anthranilate chelate and Z or quinalzinate copper chelate to the CMP slurry, and completed the present invention. . That is, the configuration of the present invention has the following features.
  • a surfactant is contained so that ⁇ ⁇ of the slurry becomes 2 to 10
  • the chemical mechanical polishing slurry according to any one of the above (1) to (3).
  • the CMP slurry of the present invention comprises an aqueous solvent slurry containing (a) water, (b) abrasive grains, and (c) copper anthranilate and / or copper quinaldinate chelate. And used for a semiconductor integrated circuit having copper wiring.
  • the aqueous solvent of the CMP slurry of the present invention uses water as a main solvent because it is easy to clean after working environment and polishing. However, methanol, ethanol, n-propyl alcohol, isopropyl alcohol is used as necessary. Organic solvents such as acetone, methyl ethyl ketone, ethyl acetate and ethylene glycol can also be appropriately mixed.
  • the content of water in the mixed solvent is preferably 50% by mass or more, more preferably 80% by mass or more, and particularly preferably 95% by mass or more. % Or more.
  • the abrasive grains used in the CMP slurry of the present invention are not particularly limited. However, in order to more effectively act on the flattening of the semiconductor integrated circuit, the average grain size is 0.05 to 0 in view of the polishing rate. .5 wm ⁇ -alumina and ⁇ -alumina are preferred, especially ⁇ Mono-alumina is preferred, but transitional alumina such as 0-alumina and iron-alumina, and abrasive grains such as fumed silica, colloidal silica, and ceria can also be used. These may be used alone or in combination of two or more.
  • the content of the abrasive grains in the CMP slurry of the present invention is from 0.1 to 30% by mass, preferably from 0.1 to 10% by mass, and more preferably from 0.5 to 5% by mass. .
  • the CMP slurry of the present invention contains a copper chelate of anthranilate and a chelate of copper or quinaldineate.
  • the copper anthranilate chelate and / or quinaldic acid copper chelate is formed by mixing anthranilic acid and / or quinaldic acid with a compound serving as a copper source in an aqueous solution.
  • Compounds that supply copper include compounds that release copper ions such as copper sulfate, copper nitrate, copper acetate, copper chloride or hydrates thereof, and anthranilic acids such as copper hydroxide and ammonia copper complex.
  • copper compounds having a weaker coordinating power than quinaldic acid, copper metal itself, and the like are obtained. These may be used alone or in combination of two or more.
  • glycyl glycine, tartaric acid, succinic acid, ascorbic acid, adipic acid, itaconic acid, formic acid, lactic acid, malonic acid, glycolic acid, maleic acid, citric acid, lingoic acid, etc. are added to the slurry for the purpose of improving the polishing rate.
  • the copper chelate of anthranilic acid and Z or quinaldic acid is formed in the slurry, If the ratio is too high, the copper components with reaction with other chelate agent such as glycylglycine to lose the effect of these optional ingredients, c therefor is that the desired polishing rate can not be obtained, the copper component
  • the amount added should be less than the amount of the copper component remaining after reacting with anthranilic acid and / or quinaldic acid to form a copper chelate with other chelating agents.
  • Preferably is an integer.
  • the ratio of anthranilic acid and / or quinaldic acid is too high, it reacts directly with the copper on the wafer and forms a film of copper anthranilate or copper quinalzinate on the wafer. May be formed, and as a result, the polishing rate may decrease. Therefore, the mixing ratio of the total amount of anthranilic acid and Z or quinaldic acid to the compound serving as the copper supply source is within the above range, and may be formed as a copper chelate before the polishing step and incorporated into the slurry. preferable.
  • the copper chelate anthranilate and the copper chelate quinate may be used alone or in combination of two or more.
  • the content of the copper anthranilate chelate and / or the quinaldic acid copper chelate in the CMP slurry of the present invention is from 0.05 to 10% by mass in terms of anthranilic acid and / or quinaldic acid, and is preferably 0% by mass. It is 1 to 8% by mass, more preferably 0.5 to 5% by mass.
  • the CMP slurry In order for copper anthranilate and / or quinaldic acid chelates to be present in the CMP slurry in a stable form, do not add substances that are more attractive to copper ions than anthranilic acid and Z or quinaldic acid. It is desirable. When it is unavoidable to add a substance that has a strong ability to attract copper ions, the CMP slurry should be used so that anthranilic acid and Z or quinaldic acid supply a sufficient amount of copper ions to form a chelate. It is preferable to appropriately set pH and various polishing environments.
  • the CMP slurry of the present invention may optionally contain a pH adjuster.
  • the pH adjuster is not particularly limited, but generally, the presence of metal ions or the like is not preferable in semiconductor polishing.
  • the following PH adjusters can be used. Examples thereof include quaternary ammonium salts such as ammonia, trishydroxymethylaminoaminomethane, and tetramethylammonium hydroxide, piperazine, other organic amines, and organic substances containing an amino group.
  • PH adjusters that adjust to the acidic side include inorganic acids such as nitric acid, sulfuric acid, and hydrochloric acid, acetic acid, Organic acids such as propionic acid, lactic acid, citric acid, oxalic acid, and succinic acid are listed.
  • inorganic acids such as nitric acid, sulfuric acid, and hydrochloric acid
  • acetic acid Organic acids such as propionic acid, lactic acid, citric acid, oxalic acid, and succinic acid are listed.
  • these pH regulators trishydroxymethylaminoaminomethane, tetramethylammonium hydroxide, which has low reactivity with copper Preferred are quaternary ammonium salts such as, and nitric acid.
  • the content of the pH adjuster varies depending on the type, it is preferable that the pH of the CMP slurry of the present invention is finally adjusted to 2 to 10 and more preferably the pH is adjusted to 3 to 9. In this range, particularly excellent flattening ability can be exhibited because etching and surface oxidation to copper as a wiring material are small.
  • the CMP slurry of the present invention may contain a surfactant, if necessary.
  • a surfactant By containing a surfactant, the dispersibility of the CMP slurry is improved and an antifoaming effect can be expected.
  • the surfactant is not particularly limited, and is appropriately selected from an anionic surfactant, a cationic surfactant, a nonionic surfactant and an amphoteric surfactant.
  • anionic surfactant examples include ammonium lauryl sulfate, polyacrylic acid, alkyl sulfate, and alkylbenzene sulfonate.
  • nonionic surfactant examples include a polyoxyethylene derivative, a polyoxyethylene sorbin fatty acid ester, and a dalyserine fatty acid ester.
  • cationic surfactant examples include an alkylamine salt and a quaternary ammonium salt.
  • amphoteric surfactant examples include alkyl benzoin, aminoxide, and the like.
  • the content of the surfactant in the CMP slurry of the present invention is preferably from 0.001 to 30% by mass, more preferably from 0.05 to 10% by mass, and particularly preferably from 0.05 to 10% by mass. 0.01 to 5% by mass.
  • the CMP slurry of the present invention can be added or applied to a substance conventionally used for a CMP slurry or a composition and conditions applied to the CMP slurry within a range that does not impair the effects of the present invention.
  • benzotriazole or a derivative thereof, glycylglycine, hydrogen peroxide, polyacrylic acid, and the like can be added.
  • Zotriazole or its derivative is 0.0001 to 1.0% by mass
  • glycylglycine is 0.1 to 10.0% by mass
  • hydrogen peroxide is 0.01 to 15% by mass
  • polyacrylic acid is It is preferably from 0.01 to 5.0% by mass.
  • the CMP slurry of the present invention is obtained by mixing abrasive grains, copper anthranilate chelate and copper or quinaldic acid chelate, and, if necessary, a pH adjuster, a surfactant, and other components with an aqueous solvent.
  • the copper chelates of anthranilate and Z or quinaldic acid it is preferable to add the copper chelates of anthranilate and Z or quinaldic acid to the aqueous solvent after forming these copper chelates in advance, but it is preferable to add anthranilic acid and Z or quinaldic acid or a compound that is a supply source of copper. May be separately added to an aqueous solvent to form a chelate in the aqueous solvent. When mixing after forming the chelate, it is preferable to add a pH adjuster when forming the chelate.
  • the CMP slurry of the present invention can achieve excellent planarization performance on the surface of a semiconductor integrated circuit is not clear, but the CMP slurry is special because it contains copper anthranilate chelate and Z or copper quinalzinate chelate. Fluid with high viscosity, so that in the CMP process of the semiconductor integrated circuit surface, the CMP slurry that has entered the concave portion of the pattern does not move and the force is not easily transmitted to the bottom of the concave portion. It seems to be excellent.
  • the reason that the slurry is difficult to move in the concave portion is not only the viscosity but also the chelate particles containing copper, which has an affinity for copper, and is difficult to move in a place where no force is applied.
  • the reason why the CMP slurry of the present invention can provide an excellent polishing rate is that anthranilic acid and / or quinaldic acid are mixed into the CMP slurry as a copper chelate from the beginning. It is considered that the copper chelate is not firmly fixed in the form of a copper chelate film, and it is presumed that the copper chelate can be easily removed by mechanical and physical action due to contact with the polishing pad.
  • the “special viscosity” mentioned above has properties such as yield value under polishing conditions. It is assumed that only a very short distance will transmit the stress when a certain shear stress is applied.
  • the “special viscosity” is also considered to have a rheological property that thickens depending on the time when a shear stress is applied.
  • the convex portion where the slurry changes rapidly is considered. Slurry that has entered the recess with relatively low replacement while the viscosity remains low thickens, and its effect further suppresses the movement of the slurry in the recess, so the slurry flows only mainly at the convex portion. Will be polished. Therefore, it is considered that the protrusions can be selectively polished, and a CMP slurry having excellent flattening ability can be obtained.
  • the portions other than the portions that have been subject to the dicing specifically, the portions that become convex portions on the surface of the semiconductor integrated circuit, can be easily removed by the mechanical and physical action of the polishing pad, and thus have wiring.
  • the surface of the semiconductor integrated circuit can be excellently flattened.
  • the mechanical and physical effects applied to the pad during polishing can be converted into pressure, and it is preferable to be about 0.69 X 10 3 to 3.45 X 10 Pa.
  • a metal component other than copper which is a base material and a wiring material, or a component that is difficult to clean, be contained in the CMP slurry.
  • Copper anthranilate chelate and copper or quinaldinate chelate are preferable and are suitable for forming a semiconductor integrated circuit having copper wiring without contamination of metal components other than copper which may diffuse into a base or an insulating film. CMP slurry.
  • the CMP slurry of the present invention can be widely applied to semiconductor integrated circuits having copper wiring.
  • the high polishing rate (high polishing rate) and the dishing suppressing ability, which are the effects, are exhibited.
  • the wiring density is 10 to 90%, and the wiring width is 0.03.
  • a good polishing rate can be obtained for the wiring pattern of a semiconductor integrated circuit having a copper wiring, which is becoming increasingly finer and more complicated, such as about 100 m. The effect can be exhibited.
  • the semiconductor integrated circuit applied to the present invention exerts the excellent effects of the present invention as long as it has copper wiring, but can also be applied to other elements constituting the semiconductor integrated circuit.
  • it is composed of elements widely known as semiconductor integrated circuit technology, such as those with an organic or inorganic interlayer insulating film formed on the substrate, semiconductor integrated circuits with metal plugs (such as tungsten vias), etc.
  • semiconductor integrated circuit technology such as those with an organic or inorganic interlayer insulating film formed on the substrate, semiconductor integrated circuits with metal plugs (such as tungsten vias), etc.
  • metal plugs such as tungsten vias
  • the semiconductor integrated circuit having a copper wiring to which the present invention is applied is not particularly limited, but may be a semiconductor integrated circuit having an interlayer insulating film formed on a substrate, a semiconductor integrated circuit provided with a metal plug (such as a tungsten via), or the like. It is composed of elements that are widely known as technology.
  • the wiring of these semiconductor integrated circuits is planarized by the CMP slurry of the present invention.
  • the method for flattening the semiconductor integrated circuit of the present invention is not particularly limited, and a low-pressure polishing process in which the pressure applied to the polishing pad is reduced and the rotation speed of the polishing pad is increased, and a conventional semiconductor integrated circuit is used. Methods or conditions that have been used in the CMP process can be applied.
  • the copper anthranilate chelate and / or quinaldic acid chelate contained in the CMP slurry of the present invention has the same metal component as that of the wiring of the integrated circuit and is chelated. There is no need to use special cleaning methods.
  • the semiconductor integrated circuit planarized by the CMP slurry of the present invention is excellently planarized, and is well laminated even in the multilayered integrated circuit.
  • copper wiring with a multilayer wiring structure suitable for high speed It is possible to form a semiconductor integrated circuit having
  • ⁇ Basic composition > ⁇ -alumina (Average particle size: 0.16 im) Daricyldaricin 5%, Benzotriazole 0.005%, Polyacrylic acid 0.2%, Hydrogen peroxide 1.0%, Remainder
  • the semiconductor integrated circuit was polished using the composition formed as shown below using the slurry as the basic composition.
  • An aqueous solution was added to the slurry having the above basic composition to obtain an aqueous solution containing 1.0% of anthranilic acid, 0.88% of copper nitrate trihydrate, and 0.73% of trishydroxymethylaminoaminomethane. What produced copper anthranilate chelate was added to the above basic composition.
  • an amount of anthranilic acid 0.01%, copper nitrate trihydrate 0.088%, and trishydroxymethylaminoaminomethane 0.073% was converted to an aqueous solution. After mixing and producing copper anthranilate chelate, was added.
  • An aqueous solution was added to the slurry having the above basic composition to prepare an aqueous solution containing 11% of anthranilic acid, 9.68% of copper nitrate trihydrate, and 8.03% of trishydroxymethylaminoaminomethane.
  • the product which produced copper anthranilate chelate was added to the above basic composition.
  • Table 9 shows the 50 Aim line dishing value and polishing rate when polishing 9 wafers by CMP using the compositions of Examples 1 and 2 and Comparative Examples 1 to 3 under the following conditions.
  • Figure 1 shows.
  • Table 2 shows the dishing values for each wiring width and density when the 831 CMP 00 wafer was polished by CMP with the composition of Example 1 under the following conditions.
  • Example 1 50 nm 450 nm 'min
  • Example 2 70 nm 500 nm / min Comparative example 1 120 nm SOO nm / min Comparative Example 2 1 200 nm 500 nm / min Comparative Example 3 150 nm 300 nm / min
  • Wiring width (m) (50% density) 2.5 5 2 5 5 0 1 0 0 Dice size (nm) 2 0 2 5 4 5 5 5 7 0 Wiring density (%) (5m pitch) 1 0 3 0 5 0 7 0 9 0 Dish size (nm) 1 8 2 0 2 0 3 0 4 0 Polishing conditions>
  • the use of the CMP slurry of the present invention makes it possible to planarize a semiconductor integrated circuit having copper wiring while minimizing the occurrence of dicing even at a polishing rate that is economically favorable.
  • the slurry component does not easily adhere to the semiconductor integrated circuit, there is no need to use a special cleaning method after the planarization process.
  • the semiconductor integrated circuit planarized by using the CMP slurry of the present invention is excellently planarized, so that it can operate extremely well even when multilayer wiring is formed.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
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  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

L'invention concerne une suspension de polissage chimico-mécanique contenant (a) de l'eau, (b) des grains de polissage dans une quantité de 0,01 à 30 % en masse, et (c) un chélate de cuivre d'acide anthranilique et/ou un chélate de cuivre d'acide quinaldinique dans une quantité de 0,05 à 10 % en masse en termes d'acide anthranilique et/ou d'acide chinaldinique. L'invention concerne également un procédé de polissage d'un circuit intégré à semi-conducteurs comportant un câblage en cuivre, ledit procédé faisant intervenir ladite suspension de polissage chimico-mécanique. Ladite suspension de polissage permet de régler le problème de cambrage associé au traitement d'aplanissage par ledit procédé de polissage chimico-mécanique d'un circuit intégré à semi-conducteurs.
PCT/JP2002/006590 2001-07-04 2002-06-28 Suspension de polissage chimico-mecanique destinee a un circuit integre a semi-conducteurs, procede de polissage et circuit integre a semi-conducteurs WO2003005431A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003511299A JPWO2003005431A1 (ja) 2001-07-04 2002-06-28 半導体集積回路用化学機械的研磨スラリー、研磨方法、及び半導体集積回路

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Application Number Priority Date Filing Date Title
JP2001203716 2001-07-04
JP2001-203716 2001-07-04

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WO2003005431A1 true WO2003005431A1 (fr) 2003-01-16

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Cited By (8)

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Publication number Priority date Publication date Assignee Title
JP2005129822A (ja) * 2003-10-27 2005-05-19 Hitachi Chem Co Ltd 研磨液及び研磨方法
JP2005322670A (ja) * 2004-05-06 2005-11-17 Mitsui Chemicals Inc 研磨用スラリー
EP1642949A1 (fr) * 2004-09-29 2006-04-05 Fuji Photo Film Co., Ltd. Composition de polissage et procédé de polissage utilisant cette composition
JP2007095981A (ja) * 2005-09-29 2007-04-12 Toshiba Corp 半導体装置の製造方法及び研磨方法
JP2008517791A (ja) * 2004-10-28 2008-05-29 キャボット マイクロエレクトロニクス コーポレイション 界面活性剤を含むｃｍｐ組成物
JP2009206240A (ja) * 2008-02-27 2009-09-10 Jsr Corp 化学機械研磨用水系分散体、化学機械研磨用水系分散体の製造方法および化学機械研磨方法
JP2010003732A (ja) * 2008-06-18 2010-01-07 Adeka Corp Ｃｍｐ用研磨組成物
CN102181232A (zh) * 2011-03-17 2011-09-14 清华大学 Ulsi多层铜布线铜的低下压力化学机械抛光的组合物

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US6046110A (en) * 1995-06-08 2000-04-04 Kabushiki Kaisha Toshiba Copper-based metal polishing solution and method for manufacturing a semiconductor device
JP2000183003A (ja) * 1998-10-07 2000-06-30 Toshiba Corp 銅系金属用研磨組成物および半導体装置の製造方法
EP1182242A1 (fr) * 2000-08-24 2002-02-27 Fujimi Incorporated Composition de polissage et procédé de polissage utilisant cette composition
JP2002155268A (ja) * 2000-11-20 2002-05-28 Toshiba Corp 化学的機械的研磨用スラリ及び半導体装置の製造方法
JP2002164307A (ja) * 2000-11-24 2002-06-07 Fujimi Inc 研磨用組成物およびそれを用いた研磨方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046110A (en) * 1995-06-08 2000-04-04 Kabushiki Kaisha Toshiba Copper-based metal polishing solution and method for manufacturing a semiconductor device
JP2000183003A (ja) * 1998-10-07 2000-06-30 Toshiba Corp 銅系金属用研磨組成物および半導体装置の製造方法
EP1182242A1 (fr) * 2000-08-24 2002-02-27 Fujimi Incorporated Composition de polissage et procédé de polissage utilisant cette composition
JP2002155268A (ja) * 2000-11-20 2002-05-28 Toshiba Corp 化学的機械的研磨用スラリ及び半導体装置の製造方法
JP2002164307A (ja) * 2000-11-24 2002-06-07 Fujimi Inc 研磨用組成物およびそれを用いた研磨方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005129822A (ja) * 2003-10-27 2005-05-19 Hitachi Chem Co Ltd 研磨液及び研磨方法
JP2005322670A (ja) * 2004-05-06 2005-11-17 Mitsui Chemicals Inc 研磨用スラリー
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JP2009206240A (ja) * 2008-02-27 2009-09-10 Jsr Corp 化学機械研磨用水系分散体、化学機械研磨用水系分散体の製造方法および化学機械研磨方法
JP2010003732A (ja) * 2008-06-18 2010-01-07 Adeka Corp Ｃｍｐ用研磨組成物
CN102181232A (zh) * 2011-03-17 2011-09-14 清华大学 Ulsi多层铜布线铜的低下压力化学机械抛光的组合物
CN102181232B (zh) * 2011-03-17 2013-12-11 清华大学 Ulsi多层铜布线铜的低下压力化学机械抛光的组合物

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