WO2002099966A1 - Switching amplifier having digital correction and method therefor - Google Patents

Switching amplifier having digital correction and method therefor Download PDF

Info

Publication number
WO2002099966A1
WO2002099966A1 PCT/US2002/013214 US0213214W WO02099966A1 WO 2002099966 A1 WO2002099966 A1 WO 2002099966A1 US 0213214 W US0213214 W US 0213214W WO 02099966 A1 WO02099966 A1 WO 02099966A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
output
input
digital
pulse modulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/013214
Other languages
English (en)
French (fr)
Inventor
Pallab Midya
William J. Roeckner
Poojan A. Wagh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to KR1020037015684A priority Critical patent/KR100890346B1/ko
Priority to JP2003502952A priority patent/JP2005515655A/ja
Publication of WO2002099966A1 publication Critical patent/WO2002099966A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion

Definitions

  • This invention relates generally to digital amplifiers, and more specifically, to error correction in digital amplifiers.
  • Digital audio switching power amplifiers are well known and widely used. Such amplifiers receive a digital audio signal which has been pulse modulated. Most high efficiency digital audio switching power amplifiers are based on Pulse-width modulation (PWM). PWM is widely used in a variety of applications such as digital audio amplifiers and control applications including motor controllers. Many of these applications convert a sampled digital signal to a digital pulse-width modulation signal in order to obtain high efficiency and high accuracy.
  • the PWM signal is presented to a switching amplifier that performs a level shifting function to translate the digital PWM input signal to a digital PWM signal having significantly higher voltage levels. To accomplish the power amplification, a higher voltage power supply is used in which the power supply voltage is directly used as the digital logic one value.
  • FIG. 1 illustrates in block diagram form a switching amplifier having digital correction in accordance with the present invention
  • FIG. 2 illustrates in block diagram form the digital correction of nonlinearity and power supply noise
  • FIG. 3 illustrates in block diagram form an integrating error amplifier of FIG. 2
  • FIG. 4 illustrates in graphical form a root locus plot of the digital correction system of FIG. 2.
  • FIG. 1 illustrates a Switching Amplifier System 10 having digital correction for error created by nonlinearity and power supply noise.
  • a Digital Source 12 has an output for providing digital data to an input of a Digital Signal Processor 14.
  • the digital signal processor function may be implemented either in software or with hardware components. It should be understood that Digital Signal Processor 14 may be any type of signal processing function that processes in some predetermined manner the received digital data. In the illustrated form, an output of Digital Signal Processor 14 is connected to an input of a Digital
  • Digital Correction of Nonlinearity and Power Supply Noise Module 16 functions as a digital correction circuit.
  • An output of Digital Correction of Nonlinearity and Power Supply Noise Module 16 is connected to an input of a Power Stage 18 for providing a corrected digital pulse modulated signal.
  • An output of Power Stage 18 is connected to an input of a Load 19 and to a control input of the Digital Correction of Nonlinearity and Power Supply Noise Module 16.
  • the output of Power Stage 18 provides an amplified pulse modulated output signal.
  • a Power Supply 20 is connected to Power Stage 18 for powering Power Stage 18.
  • the Digital Correction of Nonlinearity and Power Supply Noise Module 16, Power Supply 20 and Power Stage 18 represent a Switching Power Amplifier and Digital Correction Circuitry 15.
  • Digital Source 12 provides digital data to the Digital
  • the digital data may be music or any other form of information, such as a motor control signal.
  • Digital Signal Processor 14 processes the digital data by converting its form.
  • Digital Signal Processor 14 modulates the digital data using pulse modulation.
  • Two forms of pulse modulation include pulse width modulation (PWM) and pulse density modulation (PDM).
  • PWM pulse width modulation
  • PDM pulse density modulation
  • Digital Signal Processor 14 modulates the digital data using PWM. It should be noted that the function of Digital Signal Processor 14 may be implemented using either software code or by performing the modulation in hardware.
  • a digital pulse modulated signal is then presented to the Digital Correction of Nonlinearity and Power Supply Noise Module 16 which functions to correct errors originating from nonlinearity and power supply noise.
  • a corrected digital pulse modulated signal is presented to the Power Stage 18 that amplifies or level shifts the digital pulse modulated signal to provide an amplified pulse modulated signal output.
  • the amplified pulse modulated signal output may be used to drive a load.
  • the Load 19 may be implemented as any type of load, such as a motor or a speaker if the digital data is music or audio information.
  • a low pass filter (not shown) is connected between the Power Stage 18 and the Load 19. The low pass filter prevents the switching frequency and its harmonics from being coupled to the load.
  • Power Supply 20 is used to power the Power Stage 18 and determines the supply voltage rail value that a logic one output value will have.
  • the digital output of Power Stage 18 is also used as a feedback signal to the Digital Correction of Nonlinearity and Power Supply Noise Module 16 to provide digital correction for the digital switching amplifier as will be described further in connection with FIG. 2.
  • FIG. 2 Illustrated in FIG. 2 is a further detail of one implementation of the Switching Power Amplifier and Digital Correction Circuitry 15 of FIG. 1.
  • a digital pulse modulated input is connected to an input of both a Digital Pulse Modulated Input Conditioner 28 and a first input of a Digital Pulse Edge Corrector 34.
  • the digital pulse modulated input is a digital pulse width modulated (PWM) input signal; however other types of digital pulse modulated signals may be used.
  • An output of the Digital Pulse Modulated Input Conditioner 28 is connected to a first input of an Integrating Error Amplifier 30 for providing a digital pulse modulated reference signal.
  • An output of the Integrating Error Amplifier 30 is connected to a first input of an Analog-to-Digital Converter 32 for providing an analog correction signal.
  • An output of Analog-to-Digital Converter 32 is connected to a second input of the Digital Pulse Edge Corrector 34 for providing a digital correction signal.
  • a first Clock signal is connected to a first dock input of Analog-to-Digital Converter 32, to a first clock input of the Digital Pulse Edge Corrector 34, and to a first clock input of the Digital Pulse Modulated Input Conditioner 28 for providing a dock having a frequency of 2 times the switching frequency, Fsw. In one form, the 2 * Fsw frequency is 750kHz.
  • a second Clock signal is connected to a second dock input of Analog-to-Digital Converter 32, to a second clock input of the Digital Pulse Edge Corrector 34, and to a second clock input of the Digital Pulse Modulated Input Conditioner 28 for providing a dock signal labeled Fc
  • the Fc frequency is 48MHz.
  • An output of the Digital Pulse Edge Corrector 34 is connected to an input of a Power Stage 18 and provides a corrected digital pulse modulated signal.
  • An output of the Power Stage 18 is connected to a second input of the Integrating Error Amplifier 30 and provides an amplified pulse modulated signal output signal.
  • Digital Pulse Edge Corrector 34 functions to compensate for power supply noise errors and nonlinearity by adjusting the timing of when one or both edges of each digital pulse occur and thus performs a discrete-time pulse edge correction. Adjustment may occur to a leading edge, a trailing edge or to both edges of the digital pulse modulated input signal.
  • the compensated digital signal is then provided to Power Stage 18 which functions to level shift the digital signal.
  • the output of Power Stage 18 that is connected or coupled to a load is not shown in FIG. 2.
  • the compensation method taught herein uses feedback; therefore, the output of Power Stage 18 is connected to the Integrating Error Amplifier 30 in the form of an amplified pulse modulated signal output.
  • Integrating Error Amplifier 30 uses both the digital output signal provided by Power Stage 18 and a digital reference signal that is provided by the Digital Pulse Modulated Input Conditioner 28. Because the same digital pulse modulated input signal is connected to both the Digital Pulse Modulated Input Conditioner 28 and the Digital Pulse Edge Corrector 34, the digital pulse modulated input conditioner must perform some phase compensation in the form of providing signal delay.
  • Digital Pulse Modulated Input Conditioner 28 is a digital pulse modulated input signal conditioner for adding compensation for power stage delay. Digital Pulse Modulated Input Conditioner 28 also functions to compensate the digital pulse modulated input by reducing any jitter and power supply noise that may have been previously injected into the input.
  • the Integrating Error Amplifier 30 functions to compare the reference signal with the output of the Power Stage 18. Any differences between the two signals will be interpreted as an error. Integrating Error Amplifier 30 further functions to amplify the error while suppressing the switching frequency of the pulse modulation and its harmonics. The amplified error is used to create an analog correction signal for use by the Digital Pulse Edge Corrector 34 to be applied to a subsequent digital input signal edge.
  • the analog correction signal provided by Integrating Error Amplifier 30 is however in analog form. Therefore, a conversion of the correction signal is performed by the Analog-to-Digital Converter 32 to control the Digital Pulse Edge Corrector 34 with a digital control signal. It should be understood that various types of A/D converters may be used to implement Analog-to-Digital Converter 32. Also, the digital pulses provided to the Switching Power Amplifier and Digital Correction Circuitry 15 may represent a digital input signal of any bit width.
  • the Switching Power Amplifier and Digital Correction Circuitry 15 provides a negative feedback system which provides appropriate loop gain to correct for non-idealities that modify the output of Power Stage 18.
  • the Switching Power Amplifier and Digital Correction Circuitry 15 provides a negative feedback system which provides appropriate loop gain to correct for non-idealities that modify the output of Power Stage 18.
  • the Digital Pulse Edge Corrector 34 functions as a tapped delay line or a clocked delay stage that modifies digital pulse widths to compensate for nonlinearity and power supply noise.
  • Digital Pulse Edge Corrector 34 corrects the digital pulse modulated input signal by implementing a predetermined delay or advance based on the digital correction signal.
  • Integrating Error Amplifier 30 generally has a Summer 50 (a summing element), an Integrator 52, an Integrator 54, a Summer 56, an Integrator 58, an Integrator 60 and a Summer 62.
  • the Digital Pulse Modulated Reference signal from the Digital Pulse Modulated Input Conditioner 28 is connected to an add input of Summer 50 and the Amplified Pulse Modulated Signal output from Power Stage 18 is connected to a subtract input of Summer 50.
  • An output of Summer 50 is connected to an input of Integrator 52.
  • An output of Integrator 52 is connected to an input of Integrator 54 and to a first add input of Summer 62.
  • An output of Integrator 54 is connected to an add input of Summer 56, to an input of a Sealer 55 and to a second add input of Summer 62.
  • An output of Sealer 55 is connected to a second subtract input of Summer 50.
  • An output of Summer 56 is connected to an input of an Integrator 58.
  • An output of Integrator 58 is connected to an input of Integrator 60 and to a third add input of Summer 62.
  • An output of Integrator 60 is connected to an input of a Sealer 61 and to a fourth add input of Summer 62.
  • An output of Sealer 61 is connected to a subtract input of Summer 56.
  • the output of Integrator 52 is a term, K-
  • Integrator 54 is a term, K 2 * l 2 -
  • the output of Integrator 58 is a
  • Sealer 55 is a term, ⁇ i * l 2
  • the output of Sealer 61 is a term, 72 * 14.
  • the Integrating Error Amplifier 30 implements a filtering operation to selectively filter error between the reference signal and the amplified pulse modulated signal output. Integrating Error Amplifier 30 implements a band pass filter of nth order, where n is a positive integer.
  • Summer 50 functions to receive the digital pulse modulated reference signal and the amplified pulse modulated signal output from Power Stage 18.
  • a difference signal (i.e. a summation result) is generated from the two inputs and an output of Integrator 54. The sum of the three signals is used to form a signal that is sequentially integrated by Integrators 52 and 54. Integrator 52 provides a first term labeled K-
  • K 2 * l2 that is summed with K-
  • the output of Integrator 54 is provided to Summer 56 that forms a difference signal with an output of Integrator 60.
  • the difference signal is sequentially integrated by both Integrator 58 and Integrator 60 which respectively generate the terms K3I3 and K4I4.
  • the terms I ⁇ 3 * l3 and K4 * U are
  • each of Integrators 52, 54, 58 and 60 may be implemented as a conventional RC (resistor/capacitor) integrating amplifier (either single-ended or differential). The selection of the resistor and capacitor values is important in order to make sure that the integrating Error Amplifier '30 remains stable.
  • the total number of frequency poles that will exist in the closed loop system will be one more than the total number of poles in Integrating Amplifier 30.
  • the number of system poles may not be initially apparent.
  • the transfer function for the analog correction signal is:
  • FIG. 4 Illustrated in FIG. 4 in the s-domain is a root locus plot of the closed loop system containing the fourth order Integrating Error Amplifier 30. Plotted on a two dimensional graph are ideal locations of each of the five poles of the closed loop system, each being designated by an "X".
  • the root locus is plotted as the values of resistance and capacitance in each of the RC integrators of Integrating Error Amplifier 30 are varied.
  • the vertical axis is the imaginary j ⁇ axis designating the complex frequency component.
  • the horizontal axis is the real ( ⁇ ) axis designating the real frequency component.
  • the ideal locations of each of the five poles lies within a circular arc centered at the intersection of the real and complex frequency axes. Additionally, each of the lines around the ideal pole placement illustrates the movement of that pole as the RC values change. In order to design a closed loop system that will have frequency stability, all of the system poles must lie on the left half of the imaginary j ⁇ axis.
  • a corrected digital pulse modulated signal is provided to the input of the Power Stage 18 for correcting for nonlinearity in the amplified pulse modulated output signal during power stage amplification.
  • the present invention allows for use of a low cost power supply and power stage while maintaining high performance.
  • the compensation method and apparatus taught herein is very suitable for integration into a single integrated circuit. Additionally, portions of the illustrated system may be readily implemented with software code rather than using dedicated hardware.
  • the present invention performs multiple bit correction that promotes stability within a high order system. Multiple bit operation further enhances the dynamic range capabilities of the system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
PCT/US2002/013214 2001-05-31 2002-04-24 Switching amplifier having digital correction and method therefor Ceased WO2002099966A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020037015684A KR100890346B1 (ko) 2001-05-31 2002-04-24 디지털 보정 기능을 갖는 스위칭 증폭기 및 그에 대한 방법
JP2003502952A JP2005515655A (ja) 2001-05-31 2002-04-24 デジタル訂正を行うスイッチング増幅器およびデジタル訂正の方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/872,283 US6504427B2 (en) 2001-05-31 2001-05-31 Switching amplifier having digital correction and method therefor
US09/872,283 2001-05-31

Publications (1)

Publication Number Publication Date
WO2002099966A1 true WO2002099966A1 (en) 2002-12-12

Family

ID=25359252

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/013214 Ceased WO2002099966A1 (en) 2001-05-31 2002-04-24 Switching amplifier having digital correction and method therefor

Country Status (5)

Country Link
US (1) US6504427B2 (https=)
JP (1) JP2005515655A (https=)
KR (1) KR100890346B1 (https=)
TW (1) TWI256189B (https=)
WO (1) WO2002099966A1 (https=)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030058973A1 (en) * 2001-06-01 2003-03-27 Tsecouras Michael J. Adaptive pulse frame rate frequency control for digital amplifier systems
US7005917B2 (en) * 2002-04-02 2006-02-28 Jam Technologies, Inc. Power supply rejection technique for switching amplifier
WO2004088843A2 (en) 2003-03-28 2004-10-14 Ess Technology, Inc. System and method for compensating for error in a sigma delta circuit
TWI226148B (en) * 2003-07-04 2005-01-01 Delta Electronics Inc Phase and pulse width modulation fan speed control circuit
US7058464B2 (en) * 2003-07-17 2006-06-06 Ess Technology, Inc. Device and method for signal processing
US6922100B2 (en) * 2003-07-29 2005-07-26 Freescale Semiconductor, Inc. Method and apparatus for switching amplification having variable sample point and variable order correction
US7551022B2 (en) * 2003-10-10 2009-06-23 Tc Electronic A/S Power supply compensation
TWI322561B (en) * 2003-11-19 2010-03-21 Delta Electronics Inc Motor control circuit
US7161819B2 (en) * 2004-07-22 2007-01-09 Valeo Electrical Systems, Inc. Zero-crossing correction in sinusoidally commutated motors
US7276963B2 (en) * 2004-10-28 2007-10-02 Cameo Produktions-Und Vertriebs Gmbh Fuer Beschallungs Und Beleuchtungsanlagen Switching power amplifier and method for amplifying a digital input signal
WO2006051478A1 (en) * 2004-11-12 2006-05-18 Koninklijke Philips Electronics N.V. Arrangement for amplifying a pwm input signal
US7728659B2 (en) * 2005-01-28 2010-06-01 Nxp B.V. Arrangement for amplifying a PWM input signal
JP4802765B2 (ja) * 2005-03-18 2011-10-26 ヤマハ株式会社 Ｄ級増幅器
JP4675138B2 (ja) * 2005-04-14 2011-04-20 シャープ株式会社 スイッチング増幅器
US7116257B1 (en) 2005-09-26 2006-10-03 Ess Technology, Inc. Low noise digital to analog converter with audio applications
US7570693B2 (en) * 2005-09-26 2009-08-04 Ess Technology, Inc. Low noise digital to pulse width modulated converter with audio applications
US7138935B1 (en) 2005-09-26 2006-11-21 Ess Technology, Inc. Low noise digital to signal interval converter with audio applications
US7312654B2 (en) * 2005-12-20 2007-12-25 Freescale Semiconductor, Inc. Quiet power up and power down of a digital audio amplifier
EP1804374A3 (en) * 2005-12-27 2008-05-28 Sharp Kabushiki Kaisha Switching amplifier
KR100765792B1 (ko) * 2006-07-28 2007-10-12 삼성전자주식회사 스위칭 파워 앰프에서 에러 보정 방법 및 장치
US7839211B2 (en) * 2006-12-21 2010-11-23 Bang & Olufsen Icepower A/S Error correction system for a class-D power stage
US7629840B2 (en) * 2007-10-22 2009-12-08 Freescale Semiconductor, Inc. Digital pulse width modulated feedback system for a switching amplifier and method therefor
US7777562B2 (en) * 2007-12-20 2010-08-17 Asahi Kasei Emd Corporation Distortion suppression circuit for digital class-D audio amplifier
US20090261902A1 (en) * 2008-04-17 2009-10-22 Freescale Semiconductor, Inc. Asynchronous Error Correction Circuit for Switching Amplifier
US7821439B2 (en) * 2008-04-22 2010-10-26 International Truck Intellectual Property Company, Llc Programmable CAN bus to analogue signal converter
DE112009001227T5 (de) * 2008-05-21 2011-04-07 Silicon Laboratories, Inc., Austin Prädiktive Rückkopplungskompensation für PWM-Schaltverstärker
KR20100008749A (ko) 2008-07-16 2010-01-26 삼성전자주식회사 스위칭 파워 증폭 장치 및 그 제어 방법
ATE532269T1 (de) * 2008-12-24 2011-11-15 St Microelectronics Srl Regelvorrichtung für lastspeisungsgerät
GB2504361B (en) * 2012-07-27 2020-04-01 Nidec Control Techniques Ltd Control system and method
KR20140097874A (ko) * 2013-01-30 2014-08-07 삼성전자주식회사 오디오장치 및 그 제어방법
KR102480913B1 (ko) 2016-07-11 2022-12-26 삼성전자주식회사 데이터를 전송하기 위한 방법 및 그 전자 장치
KR20190106273A (ko) 2018-03-06 2019-09-18 바리아크주식회사 화재 이전에 전류 차단을 위한 센서(sense)기능을 갖는 전열선
CN109314491B (zh) * 2018-03-16 2022-08-16 深圳市汇顶科技股份有限公司 功率放大器及平衡数字输出信号的上升和下降时间的方法
WO2019237115A1 (en) * 2018-06-08 2019-12-12 Cohen Seth D Clockless time-to-digital converter
US11381224B2 (en) 2018-06-08 2022-07-05 Southern Research Institute Clockless programmable pulse width generation using an inverse chaotic map
US11265178B1 (en) 2018-06-08 2022-03-01 Southern Research Institute Physically unclonable functions using pulse width chaotic maps
US11164551B2 (en) * 2019-02-28 2021-11-02 Clifford W. Chase Amplifier matching in a digital amplifier modeling system
US11733364B2 (en) 2020-05-21 2023-08-22 Kratos Sre, Inc. Target ranging with subsampled noise correlation
CN114691437B (zh) * 2022-04-07 2025-02-18 珠海市运泰利自动化设备有限公司 一种测试校正装置及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044626A2 (en) * 1997-04-02 1998-10-08 Karsten Nielsen Pulse referenced control method for enhanced power amplification of a pulse modulated signal
WO2001010016A1 (en) * 1999-07-29 2001-02-08 Tripath Technology, Inc. Dynamic switching frequency control for a digital switching amplifier
WO2001022585A1 (en) * 1999-09-23 2001-03-29 Cirrus Logic, Inc. Adaptive dead time control for pushing-pull switching circuits

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818804B2 (ja) * 1974-12-18 1983-04-14 ソニー株式会社 パルス幅変調増巾回路
US5077539A (en) 1990-12-26 1991-12-31 Apogee Technology, Inc. Switching amplifier
JP3185257B2 (ja) * 1991-07-23 2001-07-09 株式会社明電舎 電力変換ユニットの並列運転装置
US6150969A (en) 1996-06-12 2000-11-21 Audiologic, Incorporated Correction of nonlinear output distortion in a Delta Sigma DAC
US5777512A (en) * 1996-06-20 1998-07-07 Tripath Technology, Inc. Method and apparatus for oversampled, noise-shaping, mixed-signal processing
US5974089A (en) * 1997-07-22 1999-10-26 Tripath Technology, Inc. Method and apparatus for performance improvement by qualifying pulses in an oversampled noise-shaping signal processor
DK28398A (da) 1998-03-03 1999-09-04 Toccata Technology Aps Fremgangsmåde ved kompensering af ulineariteter i en forstærker, en forstærker, samt anvendelser af fremgangsmåden og forst
CA2347991A1 (en) 1998-11-30 2000-06-08 Bang & Olufsen Powerhouse A/S A pulse width modulation power converter
US6362683B1 (en) * 1999-07-29 2002-03-26 Tripath Technology, Inc. Break-before-make distortion compensation for a digital amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044626A2 (en) * 1997-04-02 1998-10-08 Karsten Nielsen Pulse referenced control method for enhanced power amplification of a pulse modulated signal
WO2001010016A1 (en) * 1999-07-29 2001-02-08 Tripath Technology, Inc. Dynamic switching frequency control for a digital switching amplifier
WO2001022585A1 (en) * 1999-09-23 2001-03-29 Cirrus Logic, Inc. Adaptive dead time control for pushing-pull switching circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NIELSEN K: "PEDEC-a novel pulse referenced control method for high quality digital PWM switching power amplification", POWER ELECTRONICS SPECIALISTS CONFERENCE, 1998. PESC 98 RECORD. 29TH ANNUAL IEEE FUKUOKA, JAPAN 17-22 MAY 1998, NEW YORK, NY, USA,IEEE, US, PAGE(S) 200-207, ISBN: 0-7803-4489-8, XP010294870 *

Also Published As

Publication number Publication date
TWI256189B (en) 2006-06-01
JP2005515655A (ja) 2005-05-26
US20020180518A1 (en) 2002-12-05
KR100890346B1 (ko) 2009-03-25
US6504427B2 (en) 2003-01-07
KR20040003038A (ko) 2004-01-07

Similar Documents

Publication Publication Date Title
US6504427B2 (en) Switching amplifier having digital correction and method therefor
EP3229371B1 (en) Audio amplifier system
EP1227579B1 (en) Method and apparatus for providing digital error correction for a class D power stage
US7728658B2 (en) Low-noise, low-distortion digital PWM amplifier
US7576606B2 (en) Digital PWM amplifier having a low delay corrector
US7286009B2 (en) Digital PWM amplifier with simulation-based feedback
US7058464B2 (en) Device and method for signal processing
US6924700B2 (en) Class D amplifier
US7800437B2 (en) Closed loop timing feedback for PWM switching amplifiers using predictive feedback compensation
US7482865B2 (en) Systems and methods for correcting errors resulting from component mismatch in a feedback path
US7649935B2 (en) Digital adaptive feedforward harmonic distortion compensation for digitally controlled power stage
JPH0654877B2 (ja) 線形送信装置
US20050024133A1 (en) Method and apparatus for switching amplification having variable sample point and variable order correction
US6430220B1 (en) Distortion reduction method and apparatus for linearization of digital pulse width modulation by efficient calculation
US7170360B2 (en) Device and method for digital pulse width modulation
JP2003110376A (ja) 信号増幅装置
JP3706187B2 (ja) ビデオ無線周波又は中間周波信号のａ／ｄ変換用回路
US20080024210A1 (en) Method and apparatus to correct an error in a switching power amplifier
WO2004086629A1 (en) Digital pulse width controlled oscillation modulator
US20090261902A1 (en) Asynchronous Error Correction Circuit for Switching Amplifier
JPH08204770A (ja) Ｑｐｓｋ変調信号の周波数特性補正装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2003502952

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020037015684

Country of ref document: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase