WO2002099729A2 - Circuit electronique destine a des interfaces de cartes a puces et procede de communication avec des interfaces de cartes a puces - Google Patents

Circuit electronique destine a des interfaces de cartes a puces et procede de communication avec des interfaces de cartes a puces Download PDF

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Publication number
WO2002099729A2
WO2002099729A2 PCT/DE2002/001864 DE0201864W WO02099729A2 WO 2002099729 A2 WO2002099729 A2 WO 2002099729A2 DE 0201864 W DE0201864 W DE 0201864W WO 02099729 A2 WO02099729 A2 WO 02099729A2
Authority
WO
WIPO (PCT)
Prior art keywords
chip card
pointer
electronic circuit
interface
communication
Prior art date
Application number
PCT/DE2002/001864
Other languages
German (de)
English (en)
Other versions
WO2002099729A3 (fr
Inventor
Andreas BRÄUTIGAM
Jürgen VELSEN
Hans-Gerd Gross
Original Assignee
Sc Itec Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sc Itec Gmbh filed Critical Sc Itec Gmbh
Publication of WO2002099729A2 publication Critical patent/WO2002099729A2/fr
Publication of WO2002099729A3 publication Critical patent/WO2002099729A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0008—General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Definitions

  • the invention relates to an electronic circuit for communication via chip card interfaces, for example a chip card terminal, and a method for communication via chip card interfaces.
  • DE 197 42 459 C2 discloses a device for operating a chip card and exchanging data between a chip card and a microprocessor-based system. This one
  • the data transmission takes place over a two-wire line, one channel being used to transmit the data bits and one channel being used to transmit a synchronized clock signal for each data bit (cf. EP 00 51 332 B1 and WO 98 / 34376).
  • the interface circuit consists of a circuit arrangement provided on the devices to be connected to one another, which has a separating device for separating the data signal on the data line and the clock signal on the clock line in each case into a transmitting and a receiving branch and, moreover, each for the data line and the clock line has a differential bus and transmitter driver and receiver.
  • So-called chip card terminals are used for communication with chip cards, which are also referred to as IFD (Interface Device), CAD (Chip Accepting Device), CCR (Chip Card Reader), Smart Card Reader or Smart Card Adapter.
  • IFD Interface Device
  • CAD Chip Accepting Device
  • CCR Chip Card Reader
  • Smart Card Reader Smart Card Adapter
  • a common feature of chip card terminals known from the prior art is an analog interface for supplying the chip card with which communication is to take place with electrical energy and a communication interface for establishing a data-technical connection, for example for a writing device. and / or read access to the chip card.
  • the analog interface can be implemented by electrical contacting or contactless.
  • the chip card requires a design-dependent time before communication can be started, for example with a host microprocessor. For example, an oscillator on the chip card needs a certain time to oscillate; Furthermore, an activation sequence used depending on the transmission protocol used can take a certain amount of time.
  • the invention is therefore based on the object of providing an improved electronic circuit and an improved chip card terminal and an improved method for communication via chip card interfaces.
  • the invention makes it possible to create a chip card terminal which has a plurality of chip card interfaces via which communication with a master, for example a host microprocessor system, can take place.
  • a master for example a host microprocessor system
  • Such multiple cut parts are advantageous, for example, for the realization of electronic wallets, in particular in connection with so-called Secure Application Modules (SAM) of the DSf 1546 standard.
  • SAM Secure Application Modules
  • the invention allows authentication to be carried out essentially simultaneously via the dealer card and the user card.
  • a so-called Universal Synchronous / Asynchronous Receiver / Transmitter can be used for communication via the chip card interfaces.
  • USART Universal Synchronous / Asynchronous Receiver / Transmitter
  • different synchronous and asynchronous transmission protocols can be implemented in terms of hardware.
  • the transmission protocol desired by the master can be selected and activated via a so-called mode register.
  • This is then processed via a state machine implemented in hardware in the USART module, without the need for further actions on the master side.
  • the USART module is linked to a chip card interface selected by the master to establish a communication connection. This can be done, for example, by means of a port switch controlled by the master, to which the USART is connected.
  • chip cards are introduced into different chip card interfaces
  • these chip cards are supplied with a supply voltage and activated via the corresponding analog interfaces. After the chip cards have been fully activated, communication with the master can be started within a very short time.
  • the master can link the USART module with one of the chip card interfaces in order to communicate with the chip card of this chip card interface.
  • the communication connection can be established very quickly, since the chip card is already fully activated via the analog interface.
  • the other chip cards that do not participate in the communication connection remain activated via the analog interface. If, for example, the master interrupts the communication connection with the first-mentioned interface in order to establish a communication connection with another chip card, this can be done by switching the USART module over the port switch to another chip card interface. Since the chip card in question is in turn already activated via the analog interface, the communication connection between the different chip card interfaces can be switched over in very short time intervals.
  • the electronic circuit for communication via the chip card interfaces is controlled via one or more registers, in particular a so-called command register, which the master can access. This results in a maximum relief for the master with regard to the processing effort for communication with the chip cards.
  • a buffer memory is provided, which is used both for buffering data to be sent to and received from the chip cards.
  • different areas for data to be sent and received are formed in the buffer memory, which are each marked by pointers. It is particularly advantageous that the data in question, in order to send them to the chip card, only have to be stored in the buffer memory by the host microprocessor system. From there, the data are then automatically sent from the control of the electronic circuit according to the invention to the card in question, in compliance with the time limits according to the transmission protocol used.
  • the electronic circuit takes over the complete receive control as a master and automatically stores the received data completely in the buffer memory. This does not require any support from the host microprocessor system.
  • the complete reception of the data is reported to the host microprocessor system so that it can then call up the data.
  • Fig. 1 is a block diagram of an embodiment of an electronic according to the invention
  • FIGS. 1 and 2 shows a diagram to clarify the organization of the buffer memory of the electronic circuit of FIGS. 1 and
  • FIG. 3 shows a flowchart of an embodiment of the communication method according to the invention.
  • FIG. 1 shows an electronic circuit 1, which can be used, for example, to implement a chip card terminal.
  • the electronic circuit 1 has a bus interface 2 for communication with a master system, for example a host microprocessor system.
  • the host microprocessor system can be, for example, a computer, e.g. B. act a personal computer or a laptop computer, a system of electronic payments or another microprocessor-based system.
  • the bus interface 2 is connected to a register array 3 for controlling the electronic circuit 1 in master-slave operation, the microprocessor-based host system acting as the master and the electronic circuit 1 or the chip cards controlled via it as slaves.
  • One or more registers in the register array 3, for example a command register, can be accessed via the bus interface 2; by writing certain register addresses in the register array 3, the master can specify specific requirements for the electronic circuit 1 or for the chip cards to be controlled via the electronic circuit 1 via the bus interface 2.
  • Register array 3 is connected to USART module 4.
  • the USART module 4 is used for write and / or read access to a chip card according to a synchronous or asynchronous communication protocol.
  • the protocol to be used can be specified, for example, via a register in the register array 3 US ART MODE.
  • Another register USART_MODE 2 can be provided in register array 3 for rapid switching from one transmission protocol to another.
  • additional registers e.g. B. can be linked in the form of a register bankj, so that when a different transmission protocol is selected, the registers of the corresponding register bank can be accessed without having to regenerate or specify them when the transmission protocol changes.
  • the register array 3 is also connected to a buffer memory 5, which is used for buffering data to be sent to one of the chip cards and for buffering received data.
  • the buffer memory 5 can also be used for the transfer of data from one chip card to another chip card without the data first having to be transferred to the host system.
  • the control of the buffer memory 5 is again carried out via registers in the register array 3.
  • the control of the buffer memory 5 via register is explained in more detail with reference to FIG. 2.
  • the register array 3 is also connected to the port switch 6.
  • the port switch 6 connects the USART module 4 either with a chip card interface 7 or with a chip card ten interface 8. The selection of the chip card interface 7 or chip card interface 8 takes place by writing a certain register in the register array 3 by the host system.
  • the chip card interfaces 7 and 8 are each connected to an analog interface 9.
  • the analog interface 9 serves to supply voltage to the chip cards inserted into the card readers of the chip card interfaces 7 and 8.
  • the analog interface 9 can have a so-called step-up controller 10.
  • the step-up controller provides various supply voltages, for example of 3.2 V, 5.2 V and 5.4 V.
  • the output voltage of the step-up controller can be programmed via the so-called device control register of register array 3.
  • the current supplied by the step-up controller is dependent on the selected current of the respective chip card interface 7 or 8, so that a maximum current limit is not exceeded.
  • the step-up controller only builds up the supply voltage with a current of 10 mA plus the supply current of the analog interface 9 during the switch-on time. Only when the supply voltage has reached a valid value or the internal switch-on time has been exceeded will the step-up controller be operated without current limitation.
  • the electronic circuit 1 can be used, for example, as a peripheral chip for contact-type chip card interfaces.
  • the electronic circuit 1 relieves the host processor of the need to control the lower transport protocols directly.
  • the most common and most important actions can be triggered by the host processor via the command register CMD_REG.
  • the electronic circuit can also be operated via control registers. Actions are initiated via entered values via the command register. These actions concern, for example, the setting of individual card signals or the execution of complex command sequences.
  • the USART module 4 can only be connected to one of the chip card interfaces 7 or 8 via the port switch 6. It is of particular advantage that both chip card interfaces 7 and 8 continue to be supplied with voltage by the analog interface 9, regardless of the assignment of the USART module 4, and are thus still active, so that the assignment of the USART module changes quickly 4 from one of the chip card interfaces 7 or 8 to another chip card interface is possible.
  • the assignment of the USART module 4 is preferably controlled by commands to the CMD REG register or it is set by the card register. As a result, data can be transferred simultaneously to one of the chip card interfaces 7 or 8, while activation, deactivation sequences or changes to the interface parameters (voltage level, synchronous communication, etc.) can take place on the other chip card interface ,
  • a particular advantage of the electronic circuit 1 can be seen in the fact that it can work together with a wide variety of host systems without any problems. This applies equally to complex host systems with corresponding host resources, in particular storage space, which work under operating systems such as Windows and UNIX. Such host systems are characterized by relatively long reaction times, which are not suitable for the implementation of a time-critical transmission protocol.
  • the electronic circuit 1 in particular the USART module 4, completely processes the selected transmission protocol with the associated timing.
  • the host system only has to trigger a corresponding action by writing the relevant register in the register array 3 and can then continue to work in parallel and independently of the electronic circuit 1, in particular also independently of the timing specifications of the transmission protocol used.
  • the electronic circuit 1 also works in an advantageous manner with small host systems.
  • Such small host systems are generally characterized by fast response times, but only have small system resources, in particular a small storage space.
  • the buffer memory 5 with a size of at least 1 KB provides a remedy for such small host systems.
  • the buffer memory 5 preferably has a so-called dual port structure. Access to the buffer memory 5 is then possible on the one hand from the bus interface 2 via pointer and data registers. On the other hand, the USART module can read data from the buffer memory 5 in transmit mode and enter received data into the buffer memory 5.
  • FIG. 2 shows a schematic representation of the organization of the buffer memory 5 of FIG. 1.
  • the buffer memory 5 has an address range from 0000 to 03FF. This address area is divided into a first area "RX-Buffer” and a second area “TX-Buffer” for receiving or sending data.
  • a complete data block can be transferred to the chip card under hardware control.
  • the data block is written into the buffer memory 5 by the host system via the read / write pointer RW_PTR.
  • RW_PTR read / write pointer
  • the send pointer TX PTR and the end pointer TX END the content of the memory is sent according to the selected transmission protocol after the TX buffer has been released in a control register or via the CMD REG register.
  • the USART module reads from the memory cell of the buffer memory 5 to which the TX_PTR transmit pointer points, and increments the transmit pointer TX_PTR after the character has been sent to the specified chip card without errors when the relevant data block is sent.
  • the USART module 4 automatically sends the byte reported as incorrect TX_PTR initially unchanged; however, the retry counter is decremented. If the byte in question was correctly received by the chip card during the repeated transmission attempt, ie if the chip card did not signal any further parity errors, the retry counter is automatically reloaded with its initial value.
  • the receive pointer RXJPTR and the end pointer RXJEND reserve an area for data reception.
  • End pointer RX END specifies the maximum accepted length of one to be received
  • the receive pointer RX PTR is incremented and compared with the end pointer RX_END. If there is a match, a flag is set and an interrupt is triggered.
  • the pointer RW PTR is an address pointer that points to the memory cell to be written or read in the buffer memory 5.
  • RWJDATA is a data register of buffer memory 5, via which the memory cell addressed with the RW_PTR pointer is accessed. With every access to the RWJDATA register, the address pointer RWJPTR is automatically incremented.
  • the buffer memory 5 can be written or read by the host system via the RW_PTR address pointer.
  • the address pointer RW PTR is loaded from the host system.
  • the data value is entered into the relevant memory cell to which the RW_PTR address pointer points; then the value of the RW_PTR address pointer is increased.
  • the value of the address pointer RW_PTR can be written into the TX_END pointer - for example for a subsequent send action of the data previously written in the buffer memory 5 - are taken over to one of the chip cards.
  • the pointer TX_PTR contains the start address of the block to be sent or the address of a remainder block, if the send operation has already started.
  • the pointer TXJPTR points to the next byte to be sent.
  • the TX END pointer marks the end of the data block to be sent. If the pointers TX PTR and TX END match, a complete data block has been sent and a corresponding flag is set.
  • the pointer RXJPTR points to an address of the buffer memory 5, from which received bytes are entered in the buffer memory 5. For this purpose, a received byte is entered at the current address of the pointer RXJPTR and the pointer RXJPTR is then increased. The size of the reception area in the buffer memory 5 is determined by the pointer RX_END. As long as the pointers RX_PRT and RXJEND are different, a received byte is entered in the corresponding position in the buffer memory 5. If the available memory area overflows, an interrupt may be triggered.
  • FIG. 3 shows an example of the operation of the electronic circuit 1 of FIG. 1.
  • the chip cards are inserted into the interfaces of the card reader.
  • Step 31 then activates the analog interfaces for supplying power to the chip cards.
  • step 32 communication between a host system and one of the cards (card i) is started. This communication is ended in step 33 in order to begin communication with another card j in step 34, which in turn is ended in step 35.
  • steps 32 to 35 all analog interfaces remain active in step 36, so that the communication can be switched from card i to card j in the shortest possible time.
  • the chip cards are then pulled out of the card reader again. LIST OF REFERENCE NUMBERS

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  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

L'invention concerne un circuit électronique et un procédé de communication avec au moins deux cartes à puces par l'intermédiaire de deux interfaces de cartes à puce (7, 8) et respectivement d'une interface analogique (9) comportant un module USART (4) destiné à la communication par l'intermédiaire d'une des deux interfaces de cartes à puce, ledit module pouvant être relié sélectivement à une desdites interfaces (7, 8) par l'intermédiaire d'un commutateur de port (6). Les deux interfaces sont alimentées en tension par l'intermédiaire de l'interface analogique (9) indépendamment de la sélection effectuée par le commutateur de port (6), de manière à permettre une commutation de la communication d'une interface vers l'autre en un temps réduit.
PCT/DE2002/001864 2001-06-05 2002-05-22 Circuit electronique destine a des interfaces de cartes a puces et procede de communication avec des interfaces de cartes a puces WO2002099729A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2001127124 DE10127124A1 (de) 2001-06-05 2001-06-05 Elektronischer Schaltkreis für Chipkarten-Schnittstellen und Verfahren zur Kommunikation mit Chipkarten-Schnittstellen
DE10127124.7 2001-06-05

Publications (2)

Publication Number Publication Date
WO2002099729A2 true WO2002099729A2 (fr) 2002-12-12
WO2002099729A3 WO2002099729A3 (fr) 2003-05-30

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PCT/DE2002/001864 WO2002099729A2 (fr) 2001-06-05 2002-05-22 Circuit electronique destine a des interfaces de cartes a puces et procede de communication avec des interfaces de cartes a puces

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WO (1) WO2002099729A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1511314B1 (fr) * 2003-08-29 2009-01-07 Thomson Licensing Système et méthode d'activation de lecteur de carte à puce
EP1511313A1 (fr) * 2003-08-29 2005-03-02 Thomson Licensing S.A. Appareil de contrôle, appareil d'activation de lecture de carte à puce et produits associés
DE102004009349A1 (de) * 2004-02-26 2005-09-15 Giesecke & Devrient Gmbh System mit einem mobilen Datenträger und einem Endgerät
DE102004049671B4 (de) * 2004-10-12 2007-08-02 Mühlbauer Ag Elektronisches Modul für die Herstellung, Programmierung und das Testen von Chipkarten und zugehöriges Verfahren
DE102005017300A1 (de) * 2005-04-14 2006-11-02 Siemens Ag Vorrichtung zum Auslesen von mindestens einem Chip einer Smartkarte

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136467A (en) * 1989-02-27 1992-08-04 Mips Co., Ltd. IC card adapter with card receptors in the sides of the housing
EP0562295A1 (fr) * 1992-03-04 1993-09-29 THOMSON multimedia Méthode et appareil pour contrôler plusieurs cartes à mémoire
EP1239400A1 (fr) * 2001-03-09 2002-09-11 Semiconductor Components Industries, LLC Lecteur pour deux cartes à puce

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0125095B1 (ko) * 1991-12-13 1997-12-15 다니이 아끼오 전자자산데이터이전방법
DE19731379A1 (de) * 1997-07-22 1999-01-28 Wolfgang Neifer Chipkarten-Lesemodul für zwei Chipkarten
GB9722551D0 (en) * 1997-10-25 1997-12-24 Ncr Int Inc Card reader
DE19830526A1 (de) * 1998-07-08 2000-01-13 Orga Kartensysteme Gmbh Verfahren und Vorrichtung zur Steuerung einer Kommunikation zwischen einem Terminal und einer Anzahl von Chipkarten

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136467A (en) * 1989-02-27 1992-08-04 Mips Co., Ltd. IC card adapter with card receptors in the sides of the housing
EP0562295A1 (fr) * 1992-03-04 1993-09-29 THOMSON multimedia Méthode et appareil pour contrôler plusieurs cartes à mémoire
EP1239400A1 (fr) * 2001-03-09 2002-09-11 Semiconductor Components Industries, LLC Lecteur pour deux cartes à puce

Also Published As

Publication number Publication date
DE10127124A1 (de) 2002-12-19
WO2002099729A3 (fr) 2003-05-30

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