WO2002080203A1 - Element d'inductance - Google Patents

Element d'inductance Download PDF

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Publication number
WO2002080203A1
WO2002080203A1 PCT/JP2002/002236 JP0202236W WO02080203A1 WO 2002080203 A1 WO2002080203 A1 WO 2002080203A1 JP 0202236 W JP0202236 W JP 0202236W WO 02080203 A1 WO02080203 A1 WO 02080203A1
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WO
WIPO (PCT)
Prior art keywords
conductor
layer
inductance element
wiring layer
coil
Prior art date
Application number
PCT/JP2002/002236
Other languages
English (en)
Japanese (ja)
Inventor
Takeshi Ikeda
Hiroshi Miyagi
Akira Okamoto
Original Assignee
Niigata Seimitsu Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Publication of WO2002080203A1 publication Critical patent/WO2002080203A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0033—Printed inductances with the coil helically wound around a magnetic core

Definitions

  • the present invention relates to an inductance element, and is particularly suitable for use as an inductance element that can be integrated on a semiconductor chip.
  • Inductors with high quality factor (Q) and inductance (L) values that represent performance indices such as SN such as phase noise, linearity of input / output characteristics, and power consumption. It is.
  • various amplifiers such as an LNA (Low Noise Amplifier), an IF (Intermediate Frequency) amplifier, a power amplifier, and a VC (voltage-controlled oscillator) are used.
  • LNA Low Noise Amplifier
  • IF Intermediate Frequency
  • VC voltage-controlled oscillator
  • inductors are roughly classified into three types: wire wound type, laminated type, and planar type.
  • the wire wound type forms an inductor by winding a conductive wire around a magnetic core made of a magnetic material.
  • an inductor having a high Q value or L value can be relatively easily formed by appropriately selecting the shape and size of the magnetic core, the material and length of the conductive wire, the cross-sectional area, the number of turns, and the like. It is possible to form.
  • it is necessary to wrap the conductive wire around the magnetic core there is a limit to miniaturization, and it is not suitable for integration on a semiconductor chip (surface mounting parts).
  • a coiled inductor is formed in a direction perpendicular to the lamination surface by alternately stacking and stacking a magnetic layer corresponding to a magnetic core and a conductor layer corresponding to a winding. It is.
  • the stacked type can be applied to surface mounting technology, and it is relatively easy to integrate an inductor on a semiconductor chip.
  • this laminated inductor has an open magnetic path structure in which the magnetic flux at the center of the coil having the highest magnetic flux density is opened to the outside as it is.
  • magnetic flux leaks to the outside of the inductor, which interferes with the external circuit and generates noise, or causes eddy current loss in the external conductor, resulting in high Q and L values.
  • a coil-shaped inductor is formed by forming a conductor pattern such as a broken type or a spiral type on a planar substrate.
  • This planar inductor can also be applied to surface mounting technology, and can be relatively easily integrated on a semiconductor chip.
  • this also has an open magnetic circuit structure like the stacked type, so that the magnetic flux leaks outside the inductor. Therefore, high Q and L values could not be obtained because the leakage magnetic flux interfered with external circuits to generate noise and caused eddy current loss in external conductors. Even when obtaining a high Q or L value with a planar structure, it is necessary to increase the number of turns of the coil.
  • the present invention has been made to solve such a problem, and is applicable to a wireless communication terminal that operates in a very high frequency range in the GHz band, and has good Q and L values. It is an object of the present invention to provide an inductance element having excellent electrical characteristics, little magnetic influence on an external circuit, and suitable for high integration and miniaturization in a semiconductor chip. Disclosure of the invention
  • the inductance element of the present invention includes a first conductor formed in an upper layer and a second conductor formed in a lower layer, the third conductor formed in an intermediate layer between the upper layer and the lower layer.
  • a closed magnetic circuit is formed by connecting the conductors in a coil shape.
  • a first conductor formed in a direction parallel to a lamination surface in an upper wiring layer and a first conductor formed in a direction parallel to a lamination surface in a lower wiring layer.
  • a second conductor, and a third conductor formed in a direction perpendicular to a lamination plane in an intermediate layer between the upper wiring layer and the lower wiring layer, wherein the first to third conductors are provided.
  • a closed magnetic circuit is formed by connecting the conductor in a toroidal coil shape.
  • Another embodiment of the present invention is characterized in that the intermediate layer is formed of an insulating material or a dielectric material.
  • Another embodiment of the present invention is characterized in that a magnetic path is formed in the intermediate layer in a direction parallel to the lamination surface.
  • the magnetic path is formed by a magnetic material deposited in the intermediate layer.
  • the magnetic path is formed of a magnetic material applied to a surface, a back surface, or both surfaces of the intermediate layer.
  • the magnetic path is a circle, an ellipse, or a ring shape thereof.
  • the magnetic path has a polygonal shape or a ring shape thereof.
  • the shapes of the first conductor and the second conductor are linear strips.
  • the shapes of the first conductor and the second conductor are substantially trapezoidal or substantially sectorial.
  • At least one of the first conductor and the second conductor has a hook shape.
  • At least one of the shape, size, and arrangement of the first conductor and the second conductor is a laminate of the first conductor and the second conductor.
  • the first conductor and the second conductor are formed so that the areas facing each other in a direction perpendicular to the plane are larger than a predetermined value.
  • a contact portion that connects the first conductor and the second conductor with the third conductor interposed therebetween is formed by a contact portion that connects the first conductor and the second conductor. It is characterized in that at least two connection points are formed at the connection points with the conductor.
  • the closed magnetic circuit including the first conductor, the second conductor, and the third conductor is formed by using a layer other than the uppermost layer of a semiconductor device having a multilayer structure. It is characterized by comprising.
  • an inductance element formed in a semiconductor device having a multilayer structure wherein the inductance element is formed in a first layer of the multilayer structure in a direction parallel to a stacking surface.
  • an inductance element formed in a semiconductor device having a multilayer structure comprising: a first conductor formed in an upper layer; and a second conductor formed in a lower layer.
  • a closed magnetic circuit is formed by connecting the third conductor formed in the intermediate layer between the upper layer and the lower layer in a coil shape with the third conductor interposed therebetween, and the closed magnetic circuit is formed using a plurality of layers of the semiconductor device. It is characterized by comprising a plurality of.
  • a plurality of first conductors formed in the upper layer in a direction parallel to the laminating surface, and a plurality of sets formed in the lower layer in a direction parallel to the laminating surface.
  • a second conductor, and a plurality of third conductors formed in a middle layer between the upper layer and the lower layer in a direction perpendicular to a lamination surface;
  • a plurality of closed magnetic paths are formed concentrically by connecting the third conductor in a coil shape for each set.
  • the upper conductor and the lower conductor are connected in a coil shape with the intermediate layer conductor interposed therebetween, thereby providing a coiled conductor.
  • the magnetic flux generated by the body itself becomes a closed magnetic circuit, and the generation of magnetic flux leakage can be suppressed.
  • the direction of the generated magnetic flux is parallel to the lamination surface, it is possible to reduce the loss due to the eddy current generated when the leakage magnetic flux penetrates the semiconductor laminated substrate.
  • the magnetic path formed in the intermediate layer strengthens the coupling of the magnetic flux generated by the coil-shaped conductor, and further suppresses the leakage of the magnetic flux to the outside of the coil. It is possible to do.
  • the first conductor and the second conductor are formed such that their opposing areas are larger than a predetermined value, thereby reducing the area of the contact portion. This makes it possible to increase the contact resistance, which is a factor for lowering the Q value, as much as possible.
  • FIG. 1 is a diagram illustrating a configuration example of each layer of the inductance element according to the first embodiment.
  • FIG. 2 is a top view showing a coil state of the inductance element according to the first embodiment.
  • FIG. 3 is a cross-sectional view passing through a certain axis of the inductance element according to the first embodiment.
  • FIG. 4 is a diagram illustrating the method for manufacturing the inductance element according to the first embodiment.
  • FIG. 5 is a diagram illustrating a method for manufacturing the inductance element according to the first embodiment.
  • FIG. 6 is a top view showing another configuration example of the inductance element according to the first embodiment.
  • FIG. 7 is a top view showing another configuration example of the inductance element according to the first embodiment.
  • FIG. 8 is a top view showing another configuration example of the inductance element according to the first embodiment.
  • FIG. 9 is a top view showing another configuration example of the inductance element according to the first embodiment.
  • FIG. 10 is a top view showing a coil state of the inductance element according to the second embodiment.
  • FIG. 11 is a cross-sectional view passing through a certain axis of the inductance element according to the second embodiment.
  • FIG. 12 is a top view showing another configuration example of the inductance element according to the second embodiment.
  • FIG. 13 is a top view showing a coil state of the inductance element according to the third embodiment.
  • FIG. 14 is a diagram illustrating another configuration example of the inductance element according to the third embodiment.
  • FIG. 15 is a diagram illustrating another configuration example of the inductance element according to the third embodiment.
  • FIG. 1 is a diagram showing a configuration example of each layer of the inductance element according to the first embodiment
  • FIG. 2 is a top view showing a coil state of the inductance element
  • FIG. 3 is a cross-sectional view passing through a certain axis of the inductance element
  • FIG. 4 and 5 are views showing a method of manufacturing the inductance element.
  • the inductance element of the present embodiment includes an upper wiring layer 100 shown in FIG. 1 (a), an intermediate layer 200 shown in FIG. 1 (b), and a lower wiring layer 300 shown in FIG. 1 (c). It has a laminated structure.
  • a plurality of conductor patterns 1 to 9 corresponding to the first conductor of the present invention are formed.
  • the two conductor patterns 1 and 2 constitute a lead conductor pattern for connection to a terminal electrode (not shown).
  • the remaining conductor patterns 3 to 9 constitute a coil conductor pattern for forming a toroidal (annular solenoid) coil.
  • the coil conductor patterns 3 to 9 have a linear strip shape.
  • a plurality of conductor patterns 11 to 18 corresponding to the second conductor of the present invention are formed. These conductor patterns 11 to 18 together with the conductor patterns 1 to 9 formed on the upper wiring layer 100 constitute a coil conductor pattern for forming a toroidal coil. These coil conductor patterns 11 to 18 also have a linear strip shape, and each have the same wiring length as the coil conductor patterns 3 to 9 of the upper wiring layer 100.
  • a plurality of contact portions 21 to 36 corresponding to the third conductor of the present invention are formed in the intermediate layer 200.
  • These contact portions 21 to 36 are made of, for example, a through hole and a conductive material filled therein.
  • the positions of the contact portions 21 to 36 are also shown in the upper wiring layer 100 and the lower wiring layer 300.
  • the upper wiring layer 100, the intermediate layer 200, and the lower wiring layer 300 are laminated in order from the bottom, and the conductor patterns 1 to 9 on the upper wiring layer 100, the lower wiring layer
  • the toroidal coil is connected to one multilayer board by spirally connecting the conductor patterns 11 1 to 18 on 300 via the contact portions 21 to 36 of the intermediate layer 200.
  • the lead conductor pattern 2 of the upper wiring layer 100 is connected to the coil conductor pattern 11 of the lower wiring layer 300 through the contact portion 21 at one end, and the coil conductor pattern 11 is connected to the coil conductor pattern 11 at the other end. It is connected to the coil conductor pattern 3 of the upper wiring layer 100 through the contact part 22.
  • the coil conductor patterns 12 to 18 of the lower wiring layer 300 and the coil conductor patterns 4 to 9 of the upper wiring layer 100 are spirally formed through the contact portions 23 to 35.
  • the connection is made, and another lead-out conductor pattern 1 is connected through the contact portion 36. This forms one toroidal coil.
  • FIG. 2 shows the inductance element formed in a toroidal shape when viewed from the upper wiring layer 100 side (the dotted conductor patterns 11 to 18 are formed on the lower wiring layer 300). To indicate that).
  • This inductance element constitutes a closed magnetic circuit having a closed core (magnetic core) by itself.
  • FIG. 3 shows a cross section taken along the line AA shown in FIG. In FIG. 3, the upper wiring layer 100, the intermediate layer 200, and the lower wiring layer 300 are as described above.
  • Reference numeral 400 denotes an insulating film
  • 500 denotes a semiconductor substrate.
  • the semiconductor substrate 500 is made of a semiconductor material 37 such as Si, GaAs, or the like.
  • the insulating film 400 is made of an insulating material 38 such as Si 2 and NiO.
  • the same insulation as the insulating film 400 is also provided. It is composed of material 38 or a different material. In order to simplify the manufacturing process, it is preferable to use the same insulating material 38 as the insulating film 400.
  • each layer is made of an insulating material 38 in order to realize an air core, but may be made of a dielectric material.
  • FIG. 4 mainly shows a manufacturing process of the lower wiring layer 300, and the intermediate layer 200 and the upper wiring layer 100 are formed by the same process as that of the lower wiring layer 300.
  • the manufacturing steps of the intermediate layer 200 and the upper wiring layer 100 are not shown because they can be formed.
  • an insulating film 400 made of an insulating material 38 such as SiO 2 or NiO is formed on a semiconductor substrate 500 by CVD (Chemical Vapor Deposition).
  • A1 (aluminum), Au (gold), and Ag used for the conductor patterns 11 to 18 of the lower wiring layer 300 are formed on the insulating film 400 by, for example, a vapor deposition method or a plating method.
  • Deposit conductive materials such as (silver), Cu (copper), Pd (palladium), Pt (platinum) or their alloys (Fig. 4 (a)).
  • the area of the lower wiring layer 300 where the conductor patterns 11 to 18 are to be formed is covered with the resist pattern 41 (FIG. 4B). Then, after the conductor of the lower wiring layer 300 is partially removed using the resist pattern 41 as a mask, the resist pattern 41 is also removed. As a result, the conductor patterns 11 to 18 of the lower wiring layer 300 remain in the region where the resist pattern 41 is formed (FIG. 4 (c)).
  • the insulating material 38 is deposited thicker than the film thickness of the conductor patterns 11 to 18 left in the mesa shape (FIG. 4 (d)). Then, the whole surface is etched back or CMP (Chemical Mechanical Polishing). Therefore, by removing the insulating material 38 in the portion deposited thicker than the film thickness of the conductor patterns 11 to 18, the area other than the conductor patterns 11 to 18 was filled with the insulating material 38.
  • the lower wiring layer 300 is formed (FIG. 4E).
  • the intermediate layer 200 is then formed on the lower wiring layer 300 thus formed by, for example, a vapor deposition method or a plating method.
  • the insulating material 38 is deposited to be thicker than the contact portions 21 to 36 left in the mesa shape. Then, by removing the insulating material 38 in a portion deposited thicker than the contact portions 21 to 36 by, for example, whole-surface etch back or CMP, the region other than the contact portions 21 to 36 is removed. Form an intermediate layer 200 filled with an insulating material 38.
  • the lower wiring layer 300 and the intermediate layer 200 are formed by repeating the same process twice, but may be formed as shown in FIG. 5, for example. . That is, as shown in FIG. 4 (c), when depositing the insulating material 38 thicker than the film thickness of the conductor patterns 11 to 18 left in the mesa shape, the lower wiring layer 300 and the intermediate layer 2 An insulating material 38 is deposited by a thickness corresponding to the sum of 0 and 0 (FIG. 5 (a)). Thus, the lower wiring layer 300 in which the region other than the conductor patterns 11 to 18 is filled with the insulating material 38 is formed, and at the same time, the insulating material 38 of the intermediate layer 200 is deposited.
  • a resist pattern (not shown) is formed in a portion other than the region where the contact portions 2 :! to 36 are to be formed.
  • the resist pattern is also removed. As a result, through holes 43 are formed in the contact portions 21 to 36 where no resist pattern is formed (FIG. 5B).
  • a conductive member made of Al, Au, Ag, Cu, Pd, Pt, or an alloy thereof is filled and deposited on the through hole 43 and the intermediate layer 200 (see FIG. 5 (c)). Then, by removing the portion of the conductive member having a thickness greater than the thickness of the contact portions 21 to 36 by etch back or CMP, the contact portion 2 made of a conductive member is removed. An intermediate layer 200 in which the region other than 1 to 36 is filled with the insulating material 38 is formed (FIG. 5 (d)). By forming the lower wiring layer 300 and the intermediate layer 200 in such steps, the manufacturing process can be simplified.
  • the conductor patterns 1 to 9 used for the upper wiring layer 100 are subjected to A, Cu, Au, by, for example, a vapor deposition method or a plating method.
  • a conductive member made of Ag, Pd, Pt or an alloy thereof is deposited.
  • a region where the conductor patterns 1 to 9 of the upper wiring layer 100 are to be formed is covered with a resist pattern, and the conductor of the upper wiring layer 100 is partially removed using the resist pattern as a mask.
  • the resist pattern is also removed.
  • the conductor patterns 1 to 9 of the upper wiring layer 100 remain in the region where the resist pattern is formed.
  • the insulating material 38 is deposited to be thicker than the film thickness of the conductor patterns 1 to 9 left in the mesa shape. Then, the insulating material 3 of the portion deposited thicker than the film thickness of the conductor patterns 1 to 9 by the whole surface etch back or CMP or the like is used. By removing 8, an upper wiring layer 100 in which regions other than the conductor patterns 1 to 9 are filled with the insulating material 38 is formed. Through the above steps, a toroidal coil-shaped inductance element having the cross-sectional structure shown in FIG. 3 is formed.
  • the toroidal coil itself constitutes a closed magnetic circuit, the occurrence of leakage flux is extremely small. Therefore, a large L value can be realized, and interference with an external circuit (not shown) can be reduced to reduce adverse effects on the external circuit. Moreover, since the direction of the magnetic flux generated by the toroidal coil is parallel to the lamination surface, eddy current loss due to the leakage magnetic flux applied to the semiconductor substrate 500 does not occur. Very high Q values can also be achieved.
  • the inductance element according to the present embodiment when used in a very high frequency range in the GHz band, a very high Q value or L value can be obtained by using the core of the toroidal coil as an air core. Obtainable. At this time, sufficiently high Q and L values can be obtained without increasing the number of turns of the coil (the number of conductor patterns formed). Even if the number of windings is increased, it is not necessary to increase the number of laminations or increase the area occupied by the coil, and it is possible to respond by simply increasing the number of conductor patterns. Therefore, the inductance element of this embodiment is very suitable for miniaturization and integration on a semiconductor chip.
  • the conductive patterns 3 to 9 of the upper wiring layer 100 and the conductive patterns 11 to 18 of the lower wiring layer 300 are formed.
  • the wiring pattern of the layer 300 can be substantially the same, and a substantially uniform winding can be realized. As a result, a larger L value can be obtained by suppressing the generation of the leakage magnetic flux from between the individual windings.
  • the winding state of the coil (the arrangement state of the conductor patterns 1 to 9 and 11 to 18 and the like) shown in FIG. 2 is merely an example, and is not limited to this. For example, as shown in FIG.
  • the coil conductor patterns 3 to 9 of the upper wiring layer 100 are arranged radially so that the angle between the patterns is 45 degrees, and the lower wiring layer 300 is formed.
  • the coil conductor patterns 11 to 18 may be arranged so as to be connected at both ends of the conductor patterns 1 to 9.
  • the conductor patterns 3 to 9 of the upper wiring layer 100 and the conductor patterns 11 to 18 of the lower wiring layer 300 do not have a similar shape, and are different from the conductor patterns 3 to 9.
  • the wiring lengths of the conductor patterns 11 to 18 are not the same.
  • the area occupied by the entire coil can be reduced as compared with the case of FIG.
  • the conductor patterns 1 to 9 of the upper wiring layer 100 and the conductor patterns 11 to 18 of the lower wiring layer 300 are formed at almost the same position on each laminated surface, the lead conductor patterns 1 and It is possible to form a winding state with high accuracy even at the connection part with the second, and it is possible to suppress leakage of magnetic flux from here.
  • the number of conductor patterns formed in the upper wiring layer 100 and the lower wiring layer 300 is not limited to the examples shown in FIGS.
  • the coil may be formed by a smaller number of conductor patterns than in FIGS. 2 and 6.
  • the coil may be formed by a larger number of conductor patterns than in FIGS. 2 and 6 (not shown).
  • various types of coils can be formed by changing the arrangement and number of the conductor patterns formed on the upper wiring layer 100 and the lower wiring layer 300, the wiring length, the thickness, the material, and the like. Is possible. In this case, the area occupied by the coil, the L value, the Q value, and the like differ from each other, so that an appropriate form may be selected according to the terminal to be applied, the operating frequency, and the like.
  • the lead conductor patterns 1 and 2 are formed on the upper wiring layer 100, but may be formed on the lower wiring layer 300.
  • the position is not limited to the position shown in FIG. 2 and can be formed at an arbitrary position.
  • FIG. 8 is a diagram showing a configuration example in a case where two sets of lead conductor patterns are provided.
  • two sets of lead conductor patterns (51, 52) and (61, 62) are formed in the upper wiring layer, and two sets of coil conductor patterns (53, 53) are formed.
  • -55), (63 to 65) are formed.
  • two sets of coil conductor patterns (56 to 58) and (66-68) are formed in the lower wiring layer.
  • the lead conductor pattern 51 of the upper wiring layer is connected to the coil conductor pattern 56 of the lower wiring layer through a contact part at one end, and the coil conductor pattern 56 is connected to the upper part through the contact part at the other end. Connected to coil conductor pattern 53 of the wiring layer. Similarly, the coil conductor patterns 57 and 58 of the lower wiring layer and the coil conductor patterns 54 and 55 of the upper wiring layer are alternately connected, and further the lead conductor pattern 52 is connected. This forms one solenoid coil.
  • the lead conductor pattern 61 of the upper wiring layer is connected to the coil conductor pattern 63.
  • the coil conductor pattern 63 is connected to the coil conductor pattern 66 of the lower wiring layer through a contact part at one end, and the coil conductor pattern 66 is connected to the coil conductor pattern 64 of the upper wiring layer through the contact part at the other end.
  • the coil conductor patterns 67 and 68 of the lower wiring layer and the coil conductor patterns 65 of the upper wiring layer are alternately connected, and further the lead conductor pattern 62 is connected.
  • the two solenoid coils formed in this way have the same number of turns and the same size, respectively, and face each other in a direction parallel to the lamination surface. As a result, a 1: 1 air-core transformer having a large mutual inductance value and a high Q value can be obtained.
  • the present invention can be applied to a semiconductor chip having four or more layers.
  • Elements and integrated circuits other than inductance elements can be formed in one or more layers of a multilayer device, and the laminated structure may be four or more layers.
  • the contact portions 21 to 36 are formed by using a plurality of layers as the intermediate layer 200, thereby occupying the coil in a direction parallel to the lamination surface.
  • the coil itself can be enlarged without increasing the area, and a larger L value can be obtained.
  • the inductance element of the present embodiment has a small amount of leakage magnetic flux and the direction of the magnetic flux is also horizontal to the lamination surface, the inductance element and other elements or integrated circuits are perpendicular to the lamination surface. It is also possible to arrange them on top of each other, which can contribute to miniaturization.
  • one toroidal coil is configured by using three layers of the upper wiring layer 100, the intermediate layer 200, and the lower wiring layer 300. However, three more layers may be formed on this to form another toroidal coil.
  • the two toroidal coils are opposed to each other in a direction perpendicular to the laminating plane, and an air-core transformer having a large mutual inductance value and a high Q value can be obtained.
  • an air-core transformer having a large mutual inductance value and a high Q value can be obtained.
  • a coil having a larger number of turns can be obtained, and the Q value and the L value can be further increased.
  • the conductor pattern of the upper wiring layer 100, the intermediate layer It is also possible to form two sets of contact portions of 200 and two sets of conductor patterns of the lower wiring layer 300, respectively, and use these two sets of conductors to form two toroidal coils concentrically. .
  • the formed two toroidal coils have the same number of turns but different sizes, and face each other in a direction horizontal to the lamination surface.
  • a 1: n air-core transformer having a large mutual inductance value and a high Q value can be obtained. If two toroidal coils are connected, a coil with more turns can be obtained, and the Q value and L value can be further increased. Note that the number of turns may be different between the two coils.
  • the upper wiring layer 100, the intermediate layer 200, and the lower wiring layer 300 are formed in this order from the uppermost layer of the multilayer structure.
  • the coil is exposed on the surface of the multilayer structure.
  • a coil may be embedded in the multilayer structure by laminating another layer on the upper wiring layer 100.
  • magnetic flux is sealed by this magnetic layer and leakage magnetic flux can be further reduced.
  • the leakage magnetic flux can be further reduced.
  • the toroidal coil-shaped inductance element may be formed by individually generating sheets of the lower wiring layer 300 on which the layers 8 are formed and laminating them in order.
  • FIG. 10 is a top view showing a coil state of the inductance element according to the second embodiment
  • FIG. 11 is a cross-sectional view passing through a certain axis of the inductance element.
  • FIGS. 10 and 11 the same components as those shown in FIGS. 2 and 3 are denoted by the same reference numerals.
  • a ring-shaped magnetic path 71 is formed in the intermediate layer 200 in a direction parallel to the lamination plane.
  • This magnetic path 71 is preferably formed at a position passing through the center axis in the magnetic flux direction of the toroidal coil.
  • the ring shape of the magnetic path 71 is preferably circular in accordance with the magnetic flux generated along the central axis of the toroidal coil.
  • the magnetic path 71 can be formed, for example, by the following process.
  • the portions other than the region where the magnetic path 71 is to be formed on the intermediate layer 200 are formed.
  • the resist pattern is also removed. Thereby, a through hole is formed in the region of the magnetic path 71 where the resist pattern is not formed.
  • a magnetic material such as ferrite is filled and deposited on the through hole and the intermediate layer 200. Then, by removing the magnetic material in a portion deposited thicker than the thickness of the magnetic path 71 by etch back or CMP or the like, the magnetic path 71 composed of the magnetic material and the conductive member are formed.
  • the magnetic path 71 is formed after the contact portions 21 to 36 are formed has been described, but the order of formation may be reversed.
  • Ferrites of magnetic materials include Co (cobalt), Mn (manganese), Ca (calcium), Si (silicon), Bi (bismuth), V (vanadium), Pb (lead), C (carbon), B (boron), P (lin), Nb (diob), Hf (hafnium), Zr (zirconium), Ti (titanium), Ta (tantalum), W ( Any one or more of tungsten), Y (yttrium), Ce (cerium), O (oxygen), N (nitrogen) and the like may be contained. Further, instead of ferrite, a ferromagnetic material such as Mo (molybdenum), Cr (chromium), or Ni (nickel) may be used.
  • the magnetic path 71 by depositing the magnetic material on the intermediate layer 200, the coupling of the magnetic flux generated in the intermediate layer 200 is strengthened, and the leakage of the magnetic flux to the outside of the coil is reduced. can do. As a result, the L value can be increased, and the Q value can be increased by suppressing the occurrence of eddy current loss due to leakage magnetic flux.
  • the intermediate layer 200 itself (excluding the contact portions 21 to 36) may be made of a magnetic material. However, as in the present embodiment, the intermediate layer 200 is made of an insulating material and has a toroidal shape.
  • the ring shape of the magnetic path 71 is circular, but is not limited to this.
  • the shape may be an ellipse or a polygon, preferably a regular polygon, and more preferably a regular octagon.
  • the point is that the shape of the coil to be formed is determined by the arrangement of the conductor patterns 1 to 9 and 11 to 18 formed on the upper wiring layer 100 and the lower wiring layer 300.
  • the magnetic path 71 may be formed according to the shape of the coil. Although the magnetic path 71 has a ring shape, a circular, elliptical, or polygonal magnetic path may be formed in a region inside the outer periphery of the toroidal coil.
  • FIG. 12 is a top view showing an inductance element in a case where a ring-shaped magnetic path 72 having a regular octagonal outer shape is formed in the intermediate layer 200.
  • a regular octagonal magnetic path 72 in which the fragments are composed only of straight lines has an advantage that it can be easily formed in a semiconductor manufacturing process.
  • the above-described magnetic paths 71 and 72 may be formed by applying a magnetic material to the front surface, the back surface, or both surfaces of the intermediate layer 200. Specifically, when the lamination of the lower wiring layer 300 is completed, the magnetic paths 71 and 72 are formed on the surface of the lower wiring layer 300 (which corresponds to the back surface of the intermediate layer 200). A magnetic material is applied to the region to be formed. Further, when the lamination of the intermediate layer 200 is completed, a magnetic material is applied to a region where the magnetic paths 71 and 72 are formed on the surface of the intermediate layer 200.
  • the thickness of the magnetic paths 71 and 72 is smaller than that in the case where a magnetic material is deposited on the intermediate layer 200 as shown in Fig. 11, but it is not enough as a magnetic path for strengthening magnetic flux binding. Things. Further, since it is sufficient to simply apply the magnetic material, the manufacturing process can be simplified. Furthermore, even a circular magnetic path 71 can be easily formed.
  • a magnetic path may be formed.
  • a magnetic path may be formed for each inductance element.
  • FIG. 13 is a top view showing a coil state of the inductance element according to the third embodiment.
  • a plurality of conductor patterns 81 to 89 corresponding to the first conductor of the present invention are formed in an upper wiring layer indicated by a solid line.
  • the two conductor patterns 81 and 82 constitute a lead conductor pattern for connection to a terminal electrode (not shown).
  • the remaining conductor patterns 83 to 89 constitute a coil conductor pattern for forming a toroidal coil.
  • the coil conductor patterns 83 to 89 have a trapezoidal shape.
  • Each of the coil conductor patterns 83 to 89 is formed such that the upper side (short side) of the trapezoid faces inward and the lower side (long side) faces outward.
  • the trapezoid does not have to be geometrically strict. For example, it may be a fan shape with a curved upper or lower side.
  • a plurality of conductor patterns 91 to 98 corresponding to the second conductor of the present invention are formed in the lower wiring layer indicated by the dotted line.
  • These conductor patterns 91 to 98 also constitute coil conductor patterns for forming a toroidal coil.
  • the coil conductor patterns 91 to 98 also have a trapezoidal shape, and are formed so that the upper side (short side) of the trapezoid faces outward and the lower side (long side) faces inward.
  • a plurality of contact portions 101 to 116 corresponding to the third conductor of the present invention are formed. These contact portions 101 to 116 are made of, for example, through holes and a conductive material filled therein.
  • the connection point between the coil conductor patterns 83 to 89 of the upper wiring layer and the coil conductor patterns 91 to 98 of the lower wiring layer In addition, four contact parts are formed (two on each side of the conductor pattern).
  • the upper wiring layer, the intermediate layer, and the lower wiring layer are sequentially stacked from the bottom, and the conductor patterns 81 to 89 on the upper wiring layer, and the lower wiring layer
  • the toroidal coil is formed in one multilayer substrate by connecting the upper conductor patterns 91 to 98 spirally through the contact portions 101 to 116 of the intermediate layer. I do.
  • the inductance element thus formed constitutes a closed magnetic circuit having a closed core (magnetic core) by itself.
  • the shapes of the conductor patterns 83 to 89 and 91 to 98 are substantially trapezoidal or substantially sector-shaped, so that the spacing between adjacent conductor patterns can be narrowed even with a small number of turns.
  • the magnetic coupling can be strengthened, and the generation of magnetic flux leakage can be further suppressed. Therefore, an extremely large L value can be realized, and at the same time, interference with an external circuit (not shown) can be reduced and adverse effects on the external circuit can be reduced.
  • the inductance element of the present embodiment when used in a very high frequency range in the GHz band, a very high Q value or L value can be obtained by using the core of the toroidal coil as an air core. it can. At this time, sufficiently high Q and L values can be obtained without increasing the number of turns of the coil (the number of conductor patterns formed). Even if the number of turns is large, the number of There is no need to reduce the size of the coil or increase the area occupied by the coil, and this can be achieved simply by increasing the number of conductor patterns. Therefore, the inductance element of the present embodiment is very suitable for miniaturization and integration on a semiconductor chip.
  • the contact portions 101 to 116 are used to connect the conductor patterns 81 to 89 of the upper wiring layer and the conductor patterns 91 to 98 of the lower wiring layer.
  • a contact resistance of several ⁇ is generated in the contact portions 101 to 116. Therefore, the Q value can be increased by forming a toroidal closed magnetic circuit, but the presence of the contact resistance also causes the Q value to decrease.
  • the contact resistance can be minimized, and the Q value can be increased efficiently.
  • the Q value can be increased by reducing the contact resistance by increasing the cross-sectional area of the contact portion as much as possible, instead of increasing the number of contact portions. It is also an effective means to use a material having low electric resistance such as Au as a material of the contact part.
  • FIG. 14 is a diagram illustrating another configuration example of the inductance element according to the third embodiment.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals.
  • FIG. 14 in the upper wiring layer 100, a plurality of conductor patterns 1 to 9 corresponding to the first conductor of the present invention are formed.
  • the conductor patterns 12 1 to 12 8 of the lower wiring layer 300 have a hook-shaped (L-shaped) shape.
  • the conductor patterns 1 2 1 to 1 2 8 of the lower wiring layer 300 The long sides of the hook and the conductor patterns 3 to 9 of the upper wiring layer 100 are formed at substantially the same position on each laminated surface.
  • the intermediate layer 200 includes a plurality of contact portions 21, 22-36 (excluding odd numbers) and 133-145 (excluding even numbers) corresponding to the third conductor of the present invention. Excluding) is formed. These contact portions are made of, for example, a through hole and a conductive material filled therein. In the present embodiment, contact portions are provided at connection points between the coil conductor patterns 3 to 9 of the upper wiring layer 100 and the coil conductor patterns 122 to 128 of the lower wiring layer 300. Four pieces (one piece on one side of the conductor pattern and 3 mm on the other side) are formed.
  • the upper wiring layer 100, the intermediate layer 200, and the lower wiring layer 300 are laminated in order from the bottom. Then, the conductor patterns 1 to 9 on the upper wiring layer 100 and the conductor patterns 12 1 to 12 on the lower wiring layer 300 are connected to the contact portions 21 1, 22 2 to 22 A toroidal coil is formed in one multi-layer substrate by helically connecting through 36, 133 to 145.
  • the toroidal inductance element thus formed constitutes a closed magnetic circuit having a closed core (magnetic core) by itself.
  • the coil conductor patterns 3 to 9 of the upper wiring layer 100 and the coil conductor patterns of the lower wiring layer 300 are different. By arranging the long sides of the layers 121 to 128 at substantially the same position on each lamination surface, the number of contact portions can be increased. Therefore, the contact resistance can be reduced as much as possible, and the Q value can be increased efficiently.
  • the conductor patterns 83 to 89, 91 in trapezoidal or sector shape as shown in FIG. there is an advantage that the area of the portions facing each other is smaller than that of 998, and the generation of the line capacitance can be suppressed.
  • four contact portions were provided at the connection points between the coil conductor patterns 3 to 9 of the upper wiring layer 100 and the coil conductor patterns 122 to 128 of the lower wiring layer 300. But this number is just an example.
  • the arrangement in which one of the four contact portions is provided on one side of the conductor pattern and three on the other side is merely an example. Also, it is not necessary to provide four contact portions in every conductor pattern.
  • the contact resistance was reduced by increasing the number of contact sections.However, by increasing the area of one contact section, or by using a material with a low electrical resistance such as Au, The contact resistance may be reduced.
  • FIG. 15 is a diagram illustrating another configuration example of the inductance element according to the third embodiment.
  • the same components as those shown in FIG. 1 are denoted by the same reference numerals.
  • a plurality of conductor patterns 151-159 corresponding to the first conductor of the present invention are formed.
  • the two conductor patterns 15 1 and 15 2 constitute lead conductor patterns for connection to terminal electrodes (not shown).
  • the remaining conductor patterns 153 to 159 correspond to coil conductors for forming a toroidal coil.
  • the coil conductor patterns 153-159 have a hook shape (an inverted L-shape).
  • a plurality of conductor patterns 161 to 168 corresponding to the second conductor of the present invention are formed. These conductor patterns 161 to 168 constitute a coil conductor pattern for forming a toroidal coil.
  • the coil conductor patterns 162 to 1668 have a hook-shaped (L-shaped) shape. The folding direction of the hooks of this coil conductor pattern 16 2 to 16 8 is opposite to the folding direction of the coil conductor pattern 15 3 to 15 9 of the upper wiring layer 100, and the short side of the hook is They are formed at substantially the same position on each lamination surface.
  • the intermediate layer 200 includes a plurality of contact portions 21, 22 to 36 (excluding odd numbers), 17 3 to 18 5 (even numbers) corresponding to the third conductor of the present invention. Are formed). These contact portions are made of, for example, a through hole and a conductive material filled therein.
  • the connection points between the coil conductor patterns 15 3 to 15 9 of the upper wiring layer 100 and the coil conductor patterns 16 2 to 16 8 of the lower wiring layer 300 are: Four contact parts are formed (one on one side of the conductor pattern and three on the other side).
  • the upper wiring layer 100, the intermediate layer 200, and the lower wiring layer 300 are laminated in order from the bottom. Then, the conductor patterns 15 1 to 15 9 on the upper wiring layer 100 and the conductor patterns 16 1 to 16 8 on the lower wiring layer 300 are connected to the contact part 2 1 of the intermediate layer. , 22 to 36, 173 to 185, and spirally connected to form a toroidal coil in one multilayer substrate.
  • the toroidal inductance element thus formed constitutes a closed magnetic path having a closed core (magnetic core) by itself. Since the direction of the magnetic flux generated by the toroidal coil is parallel to the lamination surface, eddy current loss due to the leakage magnetic flux applied to the semiconductor substrate does not occur.
  • the short sides of the coil conductor patterns 150 3 to 159 of the upper wiring layer 100 and the short sides of the coil conductor patterns 16 2 to 168 of the lower wiring layer 300 By arranging them at almost the same position on each lamination surface, the number of contact parts can be increased. Therefore, the contact resistance can be reduced as much as possible, and the Q value can be increased efficiently. In addition, it is possible to suppress the generation of line capacitance.
  • four contact portions are provided at the connection points between the coil conductor patterns 1503 to 159 of the upper wiring layer 100 and the coil conductor patterns 162 to 168 of the lower wiring layer 300.
  • this number is just an example.
  • the arrangement in which one of the four contact portions is provided on one side of the conductor pattern and three on the other side is merely an example. Also, it is not necessary to provide four contact parts in every conductor pattern.
  • the contact resistance was reduced by increasing the number of contact sections.However, by increasing the area of one contact section, or by using a material with a low electrical resistance such as Au, The contact resistance may be reduced.
  • FIGS. 13 to 15 shown here are merely examples, and the present invention is not limited thereto.
  • Figures 13 to 15 are all shapes of the conductor pattern deformed into a hook shape based on Fig. 1, but the shapes of the conductor pattern are changed into a hook shape based on Figs. 6 to 9 etc. It may be deformed.
  • the conductor pattern may not be trapezoidal or key-shaped, but may be made thicker in a strip shape so that the area of the connector portion can be increased.
  • the point is that at least one of the shape, size and arrangement of the conductor pattern of the upper wiring layer and the conductor pattern of the lower wiring layer is Any configuration that makes the areas of the opposing portions larger than a predetermined value is included in the present invention.
  • the predetermined value here refers to, for example, an area value for one contact portion described in the first and second embodiments.
  • the area value is such that the contact resistance can be sufficiently reduced to satisfy the standard level of the Q value and the L value of the wireless communication terminal to which the inductance element of the present embodiment is applied.
  • each inductance element may be formed as shown in FIGS. 13 to 15. .
  • a magnetic path is formed in the intermediate layer 200 of the toroidal coil formed using the conductor pattern as shown in FIGS. It may be formed. Further, the contents described in the first to third embodiments can be applied in any combination.
  • the upper conductor and the lower conductor are connected in a coil shape with the intermediate conductor interposed therebetween, so that the formed coil itself forms a closed magnetic circuit having a closed core, and It is possible to suppress the generation of magnetic flux.
  • a large inductance (L) value can be realized, and adverse effects on external circuits can be significantly reduced.
  • the eddy current loss generated by the leakage magnetic flux applied to the semiconductor laminated substrate can be significantly reduced, and the GHz Extremely high even in the ultra-high frequency range Quality factor (Q) value can be realized.
  • the magnetic path since the magnetic path is formed in the intermediate layer in a direction parallel to the lamination surface, the magnetic path thus formed couples the magnetic flux generated by the coil-shaped conductor.
  • the leakage of magnetic flux to the outside of the coil can be further suppressed.
  • the L value can be increased, and the Q value can be increased by suppressing the occurrence of eddy current loss due to leakage magnetic flux.
  • At least one of the shape, size, and arrangement of the first conductor formed in the upper layer and the second conductor formed in the lower layer Since the first and second conductors are formed so that the area of the opposing parts of the body becomes larger than a predetermined value, the number and area of the contact parts can be increased, and the contact can be increased.
  • the Q value can be increased efficiently by keeping the resistance low.
  • the present invention is applicable to a wireless communication terminal that operates in a very high frequency range in the GHz band, has good electrical characteristics such as a high Q value and an L value, has little magnetic influence on external circuits, It is also useful for providing an inductance element suitable for high integration and miniaturization on a semiconductor chip.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Selon la présente invention, des premiers conducteurs (1-9) formés sur une couche de câblage supérieure (100) et des seconds conducteurs (11-18) formés sur une couche de câblage inférieure (300) sont connectés sous forme de bobine à des troisièmes conducteurs (parties de contact) (21-36) formés sur une couche intermédiaire (200) située entre lesdites couches. Des lignes de force fermées sont ainsi créées, afin d'obtenir une grande valeur d'inductance (L) par suppression d'un flux magnétique de fuite et afin de réduire des interférences magnétiques avec un circuit externe. Une perte de courants de Foucault engendrée par l'application d'un flux magnétique de fuite sur un panneau laminé semi-conducteur est réduite afin d'obtenir une valeur de coefficient (Q) de très haute qualité.
PCT/JP2002/002236 2001-03-28 2002-03-11 Element d'inductance WO2002080203A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001091886A JP2002289436A (ja) 2001-03-28 2001-03-28 インダクタンス素子
JP2001-91886 2001-03-28

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WO2002080203A1 true WO2002080203A1 (fr) 2002-10-10

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JP4324952B2 (ja) * 2003-02-26 2009-09-02 Ｔｄｋラムダ株式会社 インダクタンス素子の製造方法
US7196607B2 (en) * 2004-03-26 2007-03-27 Harris Corporation Embedded toroidal transformers in ceramic substrates
US7158005B2 (en) * 2005-02-10 2007-01-02 Harris Corporation Embedded toroidal inductor
US8378777B2 (en) * 2008-07-29 2013-02-19 Cooper Technologies Company Magnetic electrical device
WO2008088682A2 (fr) * 2007-01-11 2008-07-24 Keyeye Communications Transformateur planaire à large bande
US7304558B1 (en) * 2007-01-18 2007-12-04 Harris Corporation Toroidal inductor design for improved Q
JP4987893B2 (ja) * 2009-02-27 2012-07-25 東光株式会社 高周波結合器およびそれを用いた非接触伝送通信システム
WO2016068067A1 (fr) * 2014-10-31 2016-05-06 株式会社村田製作所 Composant de bobine
JP6447090B2 (ja) * 2014-12-18 2019-01-09 株式会社村田製作所 コイル部品
JP6520130B2 (ja) * 2015-01-13 2019-05-29 株式会社村田製作所 コイル部品
US11640968B2 (en) * 2018-11-06 2023-05-02 Texas Instruments Incorporated Inductor on microelectronic die
TWI723343B (zh) 2019-02-19 2021-04-01 頎邦科技股份有限公司 具立體電感之半導體結構及其製造方法

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JPH10189338A (ja) * 1996-12-26 1998-07-21 Citizen Electron Co Ltd Ｓｍｄ型コイル及びその製造方法
JPH10214724A (ja) * 1997-01-29 1998-08-11 Murata Mfg Co Ltd インダクタおよびトランス
JP2000040620A (ja) * 1998-07-24 2000-02-08 Toshiba Corp インダクタ及び該インダクタを使用した回路装置

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JPS62190825A (ja) * 1986-02-18 1987-08-21 Matsushita Electric Ind Co Ltd 高周波コイル
JPH0442905A (ja) * 1990-06-06 1992-02-13 Murata Mfg Co Ltd チップ型ｌｃ複合部品とその製造方法
JPH10189338A (ja) * 1996-12-26 1998-07-21 Citizen Electron Co Ltd Ｓｍｄ型コイル及びその製造方法
JPH10214724A (ja) * 1997-01-29 1998-08-11 Murata Mfg Co Ltd インダクタおよびトランス
JP2000040620A (ja) * 1998-07-24 2000-02-08 Toshiba Corp インダクタ及び該インダクタを使用した回路装置

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TW587259B (en) 2004-05-11

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