Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
  • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/962—Quantum dots and lines

Definitions

• the present invention relates to a memory film and a method for manufacturing the same, a memory element, a semiconductor storage device, a semiconductor integrated circuit, and a portable electronic device. More specifically, the present invention relates to a memory film including fine particles of a conductor, a method for manufacturing the same, and a memory element having such a memory film. In addition, the present invention relates to a semiconductor storage device having such a memory element, a semiconductor integrated circuit, and a portable electronic device. Background art
• a flash memory As a conventional technique using a field effect transistor having a memory film for storing charges in a gut insulating film as a memory element, there is a flash memory.
• a flash memory there is a conductive film called a floating gate in an insulating film between a control gate and a channel region.
• the amount of charge in the floating gate is changed by injecting or emitting electrons from the channel / layer region to the floating gate by Fowler-Nordheim (FN) tunneling, and the amount of charge is stored as stored information. Hold.
• FN Fowler-Nordheim
• the above conventional technique has a problem that the operating voltage is high.
• flash memory operation for example, apply 18 V to the selected word line and 6 V to the selected bit line during writing, and apply 1 OV to the selected word line and 18 V to the bit line during erasing. Because of such a high operating voltage, power consumption at the time of writing and erasing was large, which hindered low power consumption.
• a high electric field is applied to the gate insulating film, deterioration of the device has been a problem. Disclosure of the invention
• the present invention has been made to solve the above problems, and an object of the present invention is to provide a memory film operable at a low voltage and a method of manufacturing the same. Another object of the present invention is to provide a memory element having such a memory film. Still another object of the present invention is to provide a semiconductor memory device having such a memory element, a semiconductor integrated circuit, and a portable electronic device.
• a method for manufacturing a memory film according to a first aspect of the present invention includes:
• fine particles refers to particles having dimensions on the order of nanometers (nm).
• the first conductor film is formed on the semiconductor substrate via the first insulating film, and the first conductor film is formed on the first conductor film.
• a third insulating film containing conductive fine particles is formed via the second insulating film, and a second conductive film is formed on the third insulating film. Therefore, the semiconductor substrate and the second conductive film serve as electrodes, respectively, and the first conductive film and the second conductive film containing the conductive fine particles are included.
• the third insulating film serves as a charge storage portion to form a memory film.
• the memory film thus formed can perform writing / erasing and non-destructive reading at a low voltage.
• the step of forming a third insulating film containing fine conductive particles on the second insulating film includes the steps of forming fine conductive particles on the second insulating film; A series of steps including a step of forming a third insulating film on the surfaces of the fine particles of the conductor are performed at least once.
• the above-described embodiment by performing the above-described series of steps at least once, a memory effect that has not been observed when the above-described series of steps is not performed can be achieved.
• One embodiment is characterized in that the above series of steps is performed twice or three times. According to the above-described embodiment, a remarkable memory effect can be obtained, and at the same time, the short channel effect is suppressed, and miniaturization of the device is facilitated.
• the first conductive film is made of a semiconductor
• the fine particles of the conductive material are made of a semiconductor
• a step of forming a first insulating film on the semiconductor substrate The step of forming the second insulating film on the surface of the body film and the step of forming the third insulating film on the surface of the conductive fine particles are both thermal oxidation steps.
• the step of forming a first conductor film thereon and the step of forming fine particles of a conductor on the second insulating film are both characterized by chemical vapor deposition.
• the first conductive film and the fine particles of the conductive material are both made of a semiconductor, and forming a first insulating film, a second insulating film, and a third insulating film.
• the first conductive film is a polycrystalline semiconductor or an amorphous semiconductor.
• the conditions for forming the first conductor film can be the same as those used for forming a floating gate of a widely manufactured flash memory. Further, the conditions for forming the first conductive film can be used as they are in the step of forming fine conductive particles on the second insulating film. Therefore, it is possible to simplify the process and condition setting of the process.
• the semiconductor substrate is made of a silicon substrate
• the first conductive film is made of silicon
• the first to third insulating films are made of a silicon oxide film.
• Each of the fine particles is made of silicon.
• the method for manufacturing a memory film according to the second invention is characterized in that:
• the step of opening to the atmosphere and cleaning the amorphous semiconductor film After the step of forming the amorphous semiconductor film, the step of opening to the atmosphere and cleaning the amorphous semiconductor film;
• Forming a first oxide film by thermally oxidizing a part of the amorphous semiconductor film and a part of the semiconductor nucleus, and forming fine particles of the first semiconductor;
• a memory film having the same structure as the memory film formed by the method of manufacturing a memory film of the first invention can be formed. Therefore, the same operation and effect as in the case of the method for manufacturing a memory film according to the first invention are exerted.
• the density of silicon fine particles can be reduced only by changing the gas supply time. Can be controlled. Therefore, it is easy to control the characteristics of the memory film.
• the method for manufacturing a memory film according to the third invention is characterized in that:
• the step of opening to the atmosphere and cleaning the amorphous semiconductor film After the step of forming the amorphous semiconductor film, the step of opening to the atmosphere and cleaning the amorphous semiconductor film;
• the method of manufacturing a memory film according to the third aspect of the invention also provides the same operation and effect as those of the method of manufacturing a memory film of the second aspect of the invention. Furthermore, since the fine particles of the second conductor are formed in addition to the fine particles of the first semiconductor, it is similar to the case where the series of steps is performed twice in the first embodiment of the first invention. A memory film having a simple structure is formed. Therefore, a memory film having a remarkable memory effect can be obtained.
• the method for manufacturing a memory film according to the fourth invention is characterized in that:
• a gas containing one or both of Si 2 H 6 gas and Si H 4 gas is introduced onto the amorphous semiconductor film without opening to the atmosphere, so Generating a conductor core;
• the same operation and effect as those of the method of manufacturing a memory film of the second invention can be obtained. Furthermore, after the step of forming the amorphous semiconductor film, a gas containing one or both of a Si 2 H 6 gas and a Si H 4 gas is provided on the amorphous semiconductor film without opening to the atmosphere. Since the introduction is performed, the amorphous semiconductor film is not contaminated, and the generation of semiconductor nuclei is stabilized. Therefore, variations in the characteristics of the memory film can be reduced.
• the method for manufacturing a memory film according to the fifth invention is characterized in that:
• a gas containing one or both of Si 2 H 6 gas and Si H 4 gas is introduced onto the amorphous semiconductor film without opening to the atmosphere, so Generating a conductor core;
• Forming a first oxide film by oxidizing a part of the amorphous semiconductor film and a part of the semiconductor nucleus by thermal oxidation, and forming fine particles of the first semiconductor;
• the method of manufacturing a memory film according to the fifth aspect of the invention also has the same operation and effect as those of the method of manufacturing a memory film of the fourth aspect of the invention. Furthermore, since the fine particles of the second conductor are formed in addition to the fine particles of the first semiconductor, it is similar to the case where the series of steps is performed twice in the first embodiment of the first invention. A memory film having a simple structure is formed. Therefore, a memory film having a remarkable memory effect can be obtained.
• the semiconductor nucleus can be controlled to an appropriate size, and the characteristics of the memory film can be optimized.
• the semiconductor substrate and the second conductive film each serve as an electrode, and the first conductive film and the third insulating film containing fine particles of the conductive material serve as a charge storage unit.
• This memory film is written and erased at low voltage (for example, ⁇ 3 V) and has hysteresis characteristics.
• the memory is not destroyed, so non-destructive readout is possible. Therefore, significantly lower voltage operation is possible as compared with the memory film of the conventional flash memory.
• since low-voltage operation is possible, deterioration of the memory film can be suppressed. Therefore, according to the memory film of the sixth invention, a low-voltage and highly reliable memory film is provided.
• the position of the conductive fine particles contained in the third insulating film is substantially random.
• the memory characteristics appear with good reproducibility, and it is not necessary to control the position of the conductive fine particles contained in the third insulating film. Therefore, a memory film can be manufactured with a simple process with high reproducibility.
• the conductive fine particles included in the third insulating film include a first conductive fine particle close to the first conductive fine film and a slant of the first semiconductor fine particles. And fine particles of the first conductive material projected upward on a plane formed by the first conductive film, wherein the positions of the fine particles of the first conductive material are substantially random.
• a memory film having a remarkable memory effect can be obtained, and it is not necessary to control the position of the conductive fine particles contained in the third insulating film. Therefore, a memory film having a remarkable memory effect can be manufactured by a simple process.
• the diameter or height of the conductive fine particles is H
• the distance between the first conductive film and the fine particles of the first conductive is S1
• the third insulating When the average of the film thickness is W,
• the capacitance can be increased by reducing the thickness of the memory film.
• this memory film is introduced into the gate insulating film of a field effect transistor, the effective gate The thickness of the insulating film can be reduced, the short channel effect can be suppressed, and the memory element can be miniaturized.
• the semiconductor substrate is a silicon substrate
• the first conductor film is made of silicon
• the first and third insulating films are both made of a silicon oxide film
• the fine particles are characterized by being made of silicon.
• the thickness of the first insulating film is 2 nm to 5 nm, and the diameter of the conductive fine particles is 3 ⁇ ! ⁇ 7 nm.
• the thickness of the first insulating film is set to 2 nm to 5 nm, the probability that charges penetrate the silicon oxide film due to the tunnel phenomenon increases, and the memory retention time decreases.
• the diameter of the fine particles of the above conductor is 3 nm to 7 nm, the quantum size effect increases and a large voltage is required for charge transfer, and the short channel effect increases, making it difficult to miniaturize the device. Can be prevented. Therefore, a memory element that has a long storage retention time, operates at a low voltage, and can be easily miniaturized is provided.
• the gate insulating film of the field-effect transistor is formed of the memory film according to the sixth aspect.
• the memory element of the seventh invention is a field-effect transistor memory element using the memory film of the sixth invention as a gate insulating film. This allows, for example, writing and erasing at ⁇ 3 V and non-destructive reading at IV. Therefore, remarkably low voltage operation is possible as compared with the conventional flash memory, low power consumption is possible, and the reliability of the device is improved.
• the first embodiment is characterized in that it is formed on a SOI substrate.
• the junction capacitance between the source region and the drain region and the body The amount can be very small. Furthermore, when an SOI substrate is used, the depth of the source region and the drain region can be easily reduced, the short channel effect can be suppressed, and the memory element can be further miniaturized.
• a semiconductor integrated circuit according to an eighth aspect of the present invention includes:
• the memory device according to the seventh aspect is integrated.
• a memory integrated circuit operable at a low power supply voltage and consuming low power is provided.
• the semiconductor memory device according to the ninth invention is a semiconductor memory device.
• element isolation regions extending in a meandering direction in the first direction are formed side by side in a second direction perpendicular to the first direction, and are respectively formed between adjacent element isolation regions.
• An active area extending meandering in the first direction is defined,
• An impurity diffusion region serving as a source region or a drain region is formed at each of the meandering folded portions in each active region, and a channel region is formed between the impurity diffusion regions adjacent to each other in the same active region. Determined,
• a plurality of lead lines extending straight in a second direction perpendicular to the first direction are formed on the channel region in each active region via the memory film of the sixth invention. Is provided to pass through,
• a first bit line extending straight in the first direction is provided so as to pass over the impurity diffusion region provided at a folded portion on one side of the meandering in the same active region.
• a second bit line extending straight in the first direction is provided so as to pass over the impurity diffusion region provided at the folded portion on the other side of the meandering in the same active region;
• the first bit line, the second bit line, and the second bit line are connected to the impurity diffusion region located immediately below via a contact hole, respectively.
• the semiconductor substrate has an eno-HI region on the front surface side, and the well region is divided by the element isolation region and constitutes a third bit line.
• the memory film of the sixth invention is used as the memory film of each memory cell, low-voltage driving is possible.
• the area of one cell is 4 F 2 (F Is the minimum processing pitch), which is smaller than the conventional AND-type memory cell array. Therefore, low power consumption, high reliability, and high integration are possible.
• a semiconductor storage device includes:
• element isolation regions extending in a meandering direction in the first direction are formed side by side in a second direction perpendicular to the first direction, and are respectively formed between adjacent element isolation regions.
• An active area extending meandering in the first direction is defined,
• An impurity diffusion region serving as a source region or a drain region is formed at each of the meandering folded portions in each of the active regions, and a channel region is defined between the adjacent impurity diffusion regions in the same active region.
• a plurality of lead lines extending straight in a second direction perpendicular to the first direction are respectively formed on channel regions in each active region via the memory film of the sixth invention.
• a first bit line extending straight in the first direction is provided so as to pass over the impurity diffusion region provided at a folded portion on one side of the meandering in the same active region.
• a second bit line extending straight in the one direction is provided so as to pass over the impurity diffusion region provided at the folded portion on the other side of the meandering in the same active region;
• the first bit line and the second bit line are connected to the impurity diffusion region located immediately below via a contact hole, respectively.
• the semiconductor substrate includes an SOI substrate having a body made of silicon on an insulator, and the body of the SOI substrate constitutes the active region.
• the same operation and effect as those of the semiconductor storage device of the ninth aspect can be obtained.
• the capacitance between the body and the substrate can be very small due to the presence of the thick buried oxide.
• the junction capacitance between the source and drain regions and the body can be significantly reduced. Therefore, current consumption for charging the capacity can be reduced.
• One embodiment is characterized in that a part of the lead wire on the channel region constitutes a gate electrode.
• a part of the word line is used as the gate electrode, and there is no need to use the contact and the upper wiring for connecting the gate electrode and the word line. Therefore, the structure of the memory cell is simplified, and the number of manufacturing steps can be reduced. Therefore, manufacturing costs can be reduced.
• V DD V DD in the selected memory cell
• a semiconductor integrated circuit according to a eleventh aspect of the present invention is characterized in that the semiconductor memory device according to the ninth or tenth aspect of the present invention and a logic circuit are mixedly mounted.
• the cell area of the semiconductor memory device of the ninth or tenth aspect is 4 F 2, which is larger than the memory cell area of a normal one-transistor nonvolatile memory. Since it is small, the area occupied by memory can be reduced. To that extent, the area of the logic circuit and other memories can be increased, and the functions can be improved. Alternatively, the storage capacity of the memory can be increased. In this case, for example, if a large-scale program is temporarily read, the program is retained even after the power is turned off, and the program is executed even after the power is turned on again, and it becomes possible to execute the program, and However, the program can be replaced with another program. Therefore, the degree of integration of the integrated circuit can be improved and the function can be improved.
• a portable electronic device is characterized by including the semiconductor integrated circuit according to the eighth or eleventh invention.
• a high-performance and long battery life! / ⁇ portable electronic device is provided because the LSI section can have high functionality and low power consumption.
• FIG. 1A to 1D are diagrams showing a method for manufacturing a memory film according to the first embodiment of the present invention.
• 2E and 2F are diagrams showing a method for manufacturing a memory film according to the first embodiment of the present invention.
• FIG. 3 is a graph showing a change in capacitance when scanning a voltage applied to the memory film according to the first embodiment of the present invention.
• FIG. 4 is a graph showing a change in capacitance when scanning a voltage applied to the memory film according to the first embodiment of the present invention.
• 5A and 5B are cross-sectional views of the memory film according to the first embodiment of the present invention.
• 6A and 6B are cross-sectional views of the memory film according to the first embodiment of the present invention.
• FIG. 7 is a graph showing a change in capacitance when a voltage applied to the memory film is scanned when silicon growth is performed once by the LPC VD method at the time of forming the memory film.
• FIG. 8 is a graph showing a change in capacitance when a voltage applied to the memory film is scanned when silicon growth is performed twice by the LPC VD method during the formation of the memory film.
• FIG. 9 is a graph showing a change in capacitance when a voltage applied to the memory film is scanned when silicon is grown three times by the LPC VD method during the formation of the memory film.
• 1A to 1C are diagrams showing a method for manufacturing a memory film according to a third embodiment of the present invention.
• FIG. 11 is a cross-sectional view of a memory element according to Embodiment 4 of the present invention.
• FIG. 12 is a graph showing a relationship between a drain current and a gate voltage at the time of writing and erasing of the memory element according to the fourth embodiment of the present invention.
• FIG. 13 is a sectional view of a memory element according to the fifth embodiment of the present invention.
• FIG. 14 is a plan view of a memory cell array according to the sixth embodiment of the present invention.
• FIG. 15 is a cross-sectional view taken along line XV-XV in FIG.
• FIG. 16 is a cross-sectional view as seen from the cut surface spring XVI-XVI of FIG.
• FIG. 17 is a cross-sectional view taken along the line XVII—XVII of FIG.
• FIG. 18 is a circuit diagram of a memory cell array according to the sixth embodiment of the present invention.
• FIG. 19 is a sectional view of a memory cell of a memory cell array according to the eighth embodiment of the present invention. is there.
• FIG. 20 is a configuration diagram of a portable information device according to Embodiment 9 of the present invention.
• a silicon substrate is used as a semiconductor substrate, but the present invention is not particularly limited to this as long as it is a semiconductor.
• a P-channel element described in the case where an N-channel element is used as a memory may be used as a memory.
• the conductivity types of the impurities may be all reversed.
• Embodiment 1 of the present invention will be described with reference to FIGS.
• This embodiment relates to a memory film capable of holding a charge and a manufacturing method thereof.
• the silicon oxide film 112 can be formed by a chemical vapor deposition method (CVD method). Note that when a field-effect transistor is formed as a gate oxide film, it is preferable to use a thermal oxidation method with few interface states.
• the polysilicon film 113 was oxidized in an N 20 atmosphere at 900 ° C. to form a silicon oxide film 112 B having a thickness of 2 nm. Then, when the silicon grown by LP CVD method in S i H 4 Kiri ⁇ air of 620 ° C, silicon does not growth is in layers, and found that the silicon particles are formed on the unevenness distribution . That is, a polysilicon film grows in a layer on an oxide film formed by thermally oxidizing a silicon single crystal substrate, but an oxide film formed by thermally oxidizing the polysilicon film under the same silicon growth conditions. Above, silicon fine particles were formed in a scattered shape.
• the first silicon fine particles 114 were formed on the surface of the film 112B (FIG. 1B). Note that, in a plane along the surface of the silicon oxide film 112B, the formation positions of the first silicon fine particles 114 were substantially random.
• the diameter of the remaining first silicon fine particles 114 was about 5 nm.
• a second silicon particles 115 were formed (FIG. 1D).
• the second silicon fine particles 115 were formed diagonally above the first silicon fine particles 114 via a silicon oxide film.
• the formation positions of the second silicon fine particles 115 were substantially random, similarly to the formation positions of the first silicon fine particles 114.
• a polysilicon film serving as an electrode was formed by LPCVD (FIG. 2F).
• a memory film 130 sandwiched between the silicon substrate 111 serving as an electrode and the electrode polysilicon film 116 was completed.
• the number density of the silicon particles and the first silicon microparticles 1 14 combined second silicon down particles 1 15, 3 X 10 11 cm - was 2.
• the oxide film thickness S 1 separating the polysilicon film 113 from the first silicon fine particles 114 is almost constant.
• the oxide film thickness separating the first silicon fine particle 114 and the second silicon fine particle 1 15 (the closest distance between the first silicon fine particle and the second silicon fine particle) S 2 is independent of the location.
• the oxide film thickness S 3 separating the second silicon fine particles 115 and the electrode polysilicon film 116 is substantially constant. Therefore, it is possible to form the memory film 130 having stable electric characteristics by a simple process. Thus, the oxide film thickness is kept constant.
• the oxide film thickness can be easily controlled.
• the oxidation of the polysilicon film 113, the oxidation of the first silicon fine particles 114, and the oxidation of the second silicon fine particles 115 can be replaced by deposition of an oxide film by a CVD method.
• FIGS. 3 and 4 are graphs showing the relationship between the capacity of the memory film 130 and the voltage.
• FIG. 3 shows the characteristic when scanning Vg from +3 V to 13 V and then scanning again to +3 V.
• FIG. 4 shows the scanning of Vg from +1 V to 11 V, After that, it is the characteristic when scanning again to +1 V.
• Vg is the voltage applied to the silicon substrate 111 by the force B applied to the electrode polysilicon film 116
• C is the voltage per unit area. shows the electrostatic capacity.
• the voltage at which the writing / erasing starts to be performed varies depending on the oxidation amount of the polysilicon film 113.
• the oxidation amount of the polysilicon film 113 was 2 nm.
• FIGS. 5 and 6 are detailed cross-sectional views of the memory film 130 according to the present embodiment.
• FIG. 5 is a cross-sectional view when the first silicon fine particles 114 and the second silicon fine particles 115 are thermally oxidized to produce the memory film 130.
• FIG. 6 is a cross-sectional view of a case where a memory film 130 'is formed by depositing an oxide film by a CVD method instead of thermally oxidizing the first silicon fine particles 114 and the second silicon fine particles 115.
• FIGS. 5B and 6B are enlarged views of FIGS. 5A and 6A, respectively. As can be seen by comparing FIG. 5B and FIG.
• the interface between the electrode polysilicon film 116 and the oxide film 112B is obtained by thermally oxidizing the first silicon fine particles 114 and the second silicon fine particles 115.
• the irregularities are more remarkable than when an oxide film is deposited on the first silicon fine particles 114 and the second silicon fine particles 115 by the CVD method.
• a silicon substrate is used as the substrate, but this is not limited to a semiconductor.
• the material of the electrode polysilicon film 116 is not limited to this, but may be a semiconductor such as germanium or gallium arsenide, or a metal such as aluminum, copper, silver, or gold, as long as it has conductivity. .
• a polysilicon film 113 is formed via a silicon oxide film 112.
• a silicon oxide film 112B between the polysilicon film 113 and the electrode polysilicon film 116, and silicon fine particles are formed in the silicon oxide film 112B.
• These polysilicon fine particles can be classified into two types according to their positions. One is the first silicon fine particles 114 located near the polysilicon film 113. The other is a second silicon fine particle 115 positioned diagonally above the silicon fine particle 114.
• the material of the polysilicon film 113, the first silicon fine particles 114, and the second silicon fine particles 115 is not limited to this, and semiconductors such as germanium and gallium arsenide, aluminum, copper, A metal such as silver or gold may be used, as long as it is a conductive substance.
• the material of the silicon oxide film 112, 112B is not limited to this, and any material having an electrical insulation property such as a silicon nitride film, a laminated film of a silicon oxide film and a silicon nitride film, and a metal oxide film can be used. good.
• the thickness of the silicon oxide film 112 sandwiched between the silicon substrate 111 and the polysilicon film 113 is preferably, for example, 1 nm to 6 nm, and the thickness of the polysilicon film 113 is preferably , For example, 0.5 ⁇ ⁇ !
• the diameter of the first silicon fine particles 114 and the second silicon fine particles 115 is, for example, 2 nn! It is preferable to set the thickness to ⁇ 10 nm, but not limited to this. However, if the thickness of the silicon oxide film 112 sandwiched between the silicon substrate 111 and the polysilicon film 113 is too small, the probability that charges penetrate through the silicon oxide film due to the tunnel phenomenon increases, and the memory is stored.
• the retention time decreases, and if it is too thick, the short channel effect increases, making it difficult to miniaturize the element. More preferably, it is set to about 5 nm. Furthermore, if the diameters of the first silicon fine particles 114 and the second silicon fine particles 115 are too small, the quantum size effect becomes large, and a large voltage is required for the movement of charges. If it is too large, the short channel effect will occur and it will be difficult to miniaturize the device. More preferably, it is set to about 7 nm.
• the thickness of the silicon oxide film containing the silicon fine particles that is, the interface between the electrode polysilicon film 116 and the silicon oxide film 112B containing the silicon fine particles, the polysilicon silicon film 113 and the silicon oxide film 112B containing the silicon fine particles, It is desirable that W should satisfy the following equation.
• H is the average diameter or average height of the silicon fine particles
• S is the silicon oxide film thickness separating the first silicon fine particles 114 and the polysilicon film 113.
• H is 5 nm
• W is equal to or less than 12 nm
• the expression (1) is satisfied when most of the second silicon fine particles 115 are located obliquely above the first silicon fine particles 114.
• a cross-sectional TEM (transmission electron microscope) photograph in which about 10 or more silicon fine particles are photographed is shown in the cross-sectional TEM photograph.
• the diameter or height of the silicon fine particles may be averaged.
• W of the silicon oxide film 112 B containing silicon fine particles when the unevenness of the interface between the electrode polysilicon film 116 and the oxide film 1 12 B severe uses the average I ITW AV .
• W AV a cross-sectional TEM photograph in which about 10 or more silicon microparticles are photographed is used, and the average film thickness in this cross-sectional TEM photograph may be used.
• the above analysis was performed using TEM photographs of the cross sections of the memory films 130 and 130 'formed in the above embodiment.
• the average height H of the silicon fine particles was 5 nm.
• the thickness S AV of the silicon oxide film 112B containing silicon fine particles was 8 nm, which satisfied the equation (1).
• the method of manufacturing a memory film of the present embodiment no control of the formation position of the silicon fine particles is required, and the memory film can be formed by repeating the thermal oxidation process and the LPC VD process.
• each node polysilicon film 113, first silicon fine particles It is possible to precisely control the oxide film thicknesses S 2 and S 3 that separate the element 114, the second silicon fine particles 115 and the electrode polysilicon film 116), respectively. Therefore, it is possible to form a memory film with stable electric characteristics in a simple process.
• the measurement of the memory characteristics shows that, for example, writing and erasing at ⁇ 3 V and non-skinned reading at IV are possible. It has been found that extremely low voltage operation is possible. In addition, since low-voltage operation is possible, deterioration of the memory film due to high-energy charges, which has been a problem in the flash memory of the related art, can be suppressed, and reliability can be improved.
• the memory films 13 0 and 13 0 ′ manufactured in this embodiment are silicon fine particles 11 1
• the thickness of the memory films 130, 130 ' can be reduced, and the capacitance can be increased. Therefore, for example, when the memory films 130, 130 / are introduced into the gate insulating film of the field effect transistor, the effective gate insulating film thickness can be reduced, and the short channel effect can be suppressed. Memory devices can be miniaturized.
• Embodiment 2 of the present invention will be described with reference to FIGS.
• the present embodiment relates to a memory film 1 "produced by changing the number of times of silicon growth by the LPC VD method (three times in the first embodiment) in the first embodiment.
• the oxidation of the substrate, the oxidation of the polysilicon film, and the oxidation of the silicon fine particles are all thermal oxidation.
• FIG. 7 is a graph showing the relationship between the capacity of the memory film and the voltage when silicon is grown once by the LPC VD method.
• the potential V g of the electrode polysilicon film with respect to the silicon substrate was scanned from +3 V to 13 V, and then scanned again to +3 V. No memory effect is apparent.
• the structure of the memory film was an electrode polysilicon film Z oxide film Z polysilicon film / oxide film Z silicon substrate.
• FIG. 8 is a graph showing the relationship between the capacity of the memory film and the voltage when silicon is grown twice by the LPC VD method. Hysteresis appears and a memory effect is observed. At this time, the structure of the memory film is shown in FIG. In other words, the thickness of the silicon oxide film 112 containing silicon fine particles was reduced accordingly.
• FIG. 9 is a graph showing the relationship between the capacity of the memory film and the voltage when silicon is grown three times by the LPCVD method. Compared to Fig. 8, the memory effect is very remarkable. Although not shown, the characteristics when silicon growth was performed four times by the LPCVD method were close to those when silicon growth was performed three times.
• silicon growth by the LPCVD method needs to be performed at least twice, and it is more preferable to perform silicon growth three times or more.
• the effective film thickness of the memory film is further increased (the capacitance is reduced) when the operation is performed five times or more.
• Silicon growth by the method is most preferably performed three to four times.
• the polysilicon film is formed at the first time of the silicon growth by the LPCVD method, it is necessary to perform the silicon growth by the LPCVD method for forming the silicon fine particles at least once. Is most preferred.
• Embodiment 3 of the present invention will be described with reference to FIG.
• the present embodiment relates to another method for forming the same memory film as that of the first embodiment.
• FIG. 10 is a diagram showing another manufacturing procedure for forming the same film as the memory film 130 shown in FIG.
• a silicon oxide film 112 having a thickness of 2 was formed on a silicon substrate 111 in an N 20 atmosphere at 900 ° C.
• the silicon oxide film 112 can be formed by a CVD method.
• a thermal oxidation method with a small interface state is preferable.
• MBE method molecular beam epitaxy method
• LPCVD method molecular beam epitaxy method
• a 6-nm amorphous silicon film 121 was formed (Fig. 10A). After that, the surface is cleaned with hydrofluoric acid and then put into an ultra-high vacuum CVD system to supply Si 2 H 6 (the first method). And the method of supplying Si 2 H 6 (the second method). First, the first method will be described. After the formation of the amorphous silicon film 121, the substrate in that state is immersed in a cleaning solution (60 ° C) in which NH 4 OH, H 2 O 2 and H 2 O are mixed at a ratio of 1: 6: 20 to contaminate the surface. Was removed and immersed in a 5% aqueous hydrofluoric acid solution for 30 seconds to remove a natural oxide film.
• a cleaning solution 60 ° C
• NH 4 OH, H 2 O 2 and H 2 O are mixed at a ratio of 1: 6: 20 to contaminate the surface.
• the substrate in that state is dried by a centrifugal separator or dry nitrogen gas, and a chamber for forming an ultra-high vacuum CVD device equipped with a nozzle for supplying Si 2 H 6 and a substrate heating device using a graphite heater. Put in.
• the degree of vacuum in the formation chamber is maintained at 10 to 9 Torr.
• the substrate is heated at a certain temperature, preferably at a low temperature of 500 ° C to 620 ° C, so that nucleation by heating alone does not occur rapidly, and then Si 2 H 6 for nucleation is formed.
• Si 2 H 6 for nucleation is formed.
• was irradiated at a flow rate of 13 cccm, and crystal nuclei 122 were generated on the surface of the amorphous silicon film 121 (FIG. 10B).
• the formation positions of the crystal nuclei 122 were substantially random within a plane along the surface of the amorphous silicon film 121.
• the density of crystal nuclei increased almost in proportion to the irradiation time of Si 2 H 6 .
• the diameter of the crystal nucleus was almost constant regardless of the irradiation time of Si 2 H 6 .
• high vacuum was applied and heating was continued to grow crystal nuclei 122. The heating in the high vacuum is for adjusting the size of the crystal nuclei and can be omitted.
• Si H 4 gas may be used, or a mixture of Si 2 H 6 gas and Si H 4 gas may be used. Thereafter, a thermal oxidation step described later was performed.
• the substrate temperature is set to 500 ° C. to 620 ° C. without opening to the atmosphere, and then Si 2 H 6 for nucleation is irradiated at a flow rate of 13 cc cm.
• crystal nuclei 122 were generated on the surface of the amorphous silicon film 121 (FIG. 10B).
• the formation density of crystal nuclei increased almost in proportion to the irradiation time of Si 2 H 6 .
• the diameter of the crystal nuclei was almost constant regardless of the irradiation time of Si 2 H 6 .
• S i 2 H 6 gas After being exposed to Si 2 H 6 gas for a certain period of time, heating was continued under high vacuum to grow crystal nuclei 122.
• the heating in the high vacuum is for adjusting the size of the crystal nucleus, and can be omitted.
• S i 2 H 6 gas may be a mixture of S iH 4 gas may have use of, or S i 2 ⁇ ⁇ gas and S i H 4 gas. After this, The thermal oxidation step described below was performed.
• thermal oxidation was performed in a N 2 O atmosphere at 900 ° C.
• a part of the amorphous silicon film 121 and a part of the crystal nucleus 122 were oxidized to form a silicon oxide film 124.
• a part of the amorphous silicon film 121 was not oxidized to become a polysilicon film 123.
• the central part of the crystal nucleus 122 was not oxidized, and became the first silicon fine particles 125.
• the method of manufacturing a memory film according to the present embodiment does not require any control of the formation position of silicon fine particles, and can be formed by repeating a thermal oxidation step and an LPCVD step or an MBE step.
• the thickness of the oxide film separating each node can be precisely controlled. It is. Therefore, it is possible to form a memory film with stable electric characteristics in a simple process.
• the formation density of silicon fine particles can be controlled only by changing the supply time of Si 2 H 6 . Therefore, it is easy to control the characteristics of the memory film.
• Embodiment 4 of the present invention will be described with reference to FIG. 11 and FIG.
• the memory element of the present embodiment is configured by incorporating the memory film 130 or 130 ′ of the first embodiment into a gate insulating film of a field-effect transistor.
• FIG. 11 is a cross-sectional view of the memory element according to the present embodiment.
• an electrode polysilicon 116 (gate electrode) is formed via a memory film 130 'shown in FIG. Further, a source region 117 and a drain region 118 are formed.
• the silicon substrate 111 has a P-type conductivity
• the gate electrode, the source region, and the drain region have an N-type conductivity.
• Field effect transistor is not limited to this, and may be a P-channel type field effect transistor (having an N-type silicon substrate and a P-type source region and a drain region).
• the gate electrode is not limited to polysilicon, but may be a metal. It may be.
• the memory element shown in FIG. 11 uses the memory film 130 'shown in FIG. 6, the memory film 130 shown in FIG. 5 may be used.
• the memory element of the present embodiment uses the memory film 130 or 130 ′ of the first embodiment, the effective gate insulating film thickness can be reduced. Therefore, the short channel effect can be suppressed and the device can be miniaturized.
• the memory element of the present embodiment uses the memory film 130 or 130 ′ of the first embodiment, writing and erasing at a low voltage and non-destructive reading can be performed. Specifically, for example, when the oxidation amount of the polysilicon film 113 is 2 nm, writing / erasing at 3 V on the earth and nondestructive reading at 1 V are possible. Further, when the oxidation amount of the polysilicon film 113 is 1.5 nm, writing and erasing at ⁇ 1.5 V and non-destructive reading at 0.5 V are possible. Therefore, low-voltage operation is possible, low power consumption is possible, and device reliability is improved.
• the procedure for manufacturing the memory element of the present embodiment is almost the same as the known procedure for manufacturing a field-effect transistor.
• the difference from the known procedure is only in the formation of the memory film, and the procedure for forming the memory film is as described in any of Embodiments 1 to 3.
• Embodiment 1 or 2 According to the manufacturing procedure of Embodiment 1 or 2, only four thermal oxidation steps and three LPC VD steps were repeated in forming the memory film portion, and the control of the formation position of the silicon particles was not at all. do not need.
• the polysilicon film 1 1 3 and the oxide film thickness S 2 that separates the first silicon microparticles 1 1 4 and the oxide thickness S physician first silicon microparticles 1 1 4 separating the second silicon microparticles 1 1 5
• control of the formation position of the silicon fine particles is not required at all, and the formation is performed by repeating the thermal oxidation step and the LPCVD step or the MBE step. be able to.
• the formation density of silicon fine particles can be controlled only by changing the supply time of Si 2 H 6 . Therefore, it becomes easy to control the characteristics of the memory film.
• FIG. 12 is a graph showing the relationship between the drain current (Id) and the gate voltage (Vg) of the memory element. After applying 13 V to the gate electrode, the threshold value has been increased (write), indicating that a memory effect is exhibited. On the other hand, when +3 V was applied to the gate electrode, the threshold value was lowered, indicating that erasure was performed.
• the memory element of the present embodiment uses the memory film 130 or 130 'of the first embodiment, the effective gate insulating film thickness can be reduced. Therefore, the short channel effect can be suppressed and the device can be miniaturized.
• the memory element of the present embodiment uses the memory film 130 or 130 ′ of the first embodiment, it is possible to perform writing and erasing at ⁇ 3 V, and to read non-peeled lime at IV. is there. Therefore, operation at a significantly lower voltage than that of the conventional flash memory is possible, power consumption is reduced, and the reliability of the device is improved.
• the procedure described in Embodiment 1 or 2 may be used for forming the memory film, control of the formation position of the silicon fine particles is not required at all, and the thermal oxidation step and the LPCVD It can be formed by repeating the process (or MBE process). However, it is possible to precisely control the oxide film thickness separating each node (polysilicon film, first silicon fine particles, second silicon fine particles and electrode polysilicon film). Therefore, it is possible to form a memory element having stable electric characteristics by a simple process.
• FIG. 13 is a cross-sectional view of a memory element in the semiconductor device of the present embodiment. 1 19 is a body, and 120 is a buried oxide film. Although the memory element shown in FIG. 13 uses the memory film 130 ′ shown in FIG. 6, the memory film 130 shown in FIG. 5 may be used. Although FIG. 13 shows the case of a fully depleted type, it may be a partially depleted type.
• the procedure for manufacturing the memory element according to the present embodiment is almost the same as the known procedure for manufacturing a field-effect transistor on an SOI substrate.
• the difference from the known procedure is only in the formation of the memory film. As described in any one of (1) to (3).
• the following effects are obtained in addition to the effects obtained by the memory element of the fourth embodiment.
• the junction capacitance between the body region 119 and the source region 117 and the drain region 118 can be extremely reduced. Furthermore, when an SOI substrate is used, it is easy to make the depths of the source region 117 and the drain region 118 shallow, the short channel effect can be suppressed, and the element can be further miniaturized.
• Embodiment 6 of the present invention will be described below with reference to FIGS. 14 to 18.
• FIGS. 14 to 17 are schematic diagrams of a memory cell array according to the sixth embodiment of the present invention.
• FIG. 14 is a schematic plan view.
• FIG. 15 is a sectional view taken along the section line XV—XV in FIG. 14
• FIG. 16 is a sectional view taken along the section line XV I -XVI in FIG. 14
• FIG. 14 is a cross-sectional view taken along the line XV II—XV II in FIG.
• FIG. 18 is a circuit diagram of the memory cell array.
• a silicon type deep region 25 and a silicon shallow region 26 are formed in the silicon substrate 17. Further, a plurality of element isolation regions 16 are formed so as to extend in a meandering manner in the lateral direction in FIG. 14 (in FIG. 14, each of the meandering belt-like regions is hatched).
• the vertical pitch of the element isolation region 16 is set to 2 F (F is the minimum force [! Pitch]). to this
• F is the minimum force [! Pitch]
• the N + diffusion layer 19 as an impurity diffusion region is formed at each turn of the meandering in each silicon active region.
• Each N + diffusion layer 19 acts as a source region or a drain region according to the selection by the bit line when using this memory. At that time, a region between adjacent N + diffusion layers 19 in the same active region becomes a channel region.
• a plurality of polysilicon word lines 11 are formed so as to extend straight in a direction perpendicular to the direction in which the element isolation regions 16 extend (the vertical direction in FIG. 14).
• the horizontal pitch of the word lines 11 is set to 2F.
• the silicon active region (above the well region 26) covered by the word line 11 serves as a channel region.
• the channel region and the lead line 11 are separated by the memory film 21 having the same configuration as the memory film shown in FIG. 5 or FIG. 6 of the first embodiment. In this channel area, the word line 11 serves as a control gate.
• a plurality of first bit lines 12 made of a first-layer metal are formed so as to extend straight in a direction perpendicular to the word lines 11 (the horizontal direction in FIG. 14).
• the vertical pitch of the first bit line 12 is set to 2 F, and the N + diffusion layer 19 is provided at the turn-back point on one side of the meander (the peak side in Fig. 14) in the same silicon active region. It is provided to pass over.
• the first bit line 12 and the N + diffusion layer 19 immediately below the first bit line 12 are connected by a first bit line contact 14 at a pitch of 4 F in the horizontal direction.
• a plurality of second bit lines 13 made of the second layer metal are straightly arranged in the same direction as the first bit lines 12 so as to be gaps between the first bit lines, in parallel with the first bit lines. It is formed to extend.
• the vertical pitch of the second bit line 13 is set to 2F, and the N + diffusion provided at the turn-back point on the other side (the valley side in Fig. 14) of the meandering in the same silicon active region is set. It is provided so as to pass over the layer 19.
• the second bit line 13 and the N + diffusion layer 19 immediately below the second bit line 13 are connected by a second bit line contact 15 at a pitch of 4F in the horizontal direction.
• the second bit lines 12 and 13 are separated from each other by the interlayer insulating film 20 and connected to the N + diffusion layer 19 via the contacts 14 and 15 where necessary as described above. ing. Also, the P-type shallow Ueno area 26 with respect to the silicon substrate is divided by the element isolation area 16 into a slender column running in the same direction as the first bit line and the second bit line. This constitutes the third bit line.
• one memory cell is represented by a parallelogram 22 indicated by a two-dot chain line in FIG. 14, and its area is 4 F 2 .
• the memory film 21 is formed of the silicon oxide film 112, the silicon oxide film 112B, the polysilicon film 113, the first silicon fine particles 114, and the second This is a film composed of silicon fine particles 115.
• This memory cell array is arranged in a so-called AND type. That is, one first bit line and one second bit line form a pair, and n memory cells are connected in parallel between these bit lines.
• the first bit line of the first bit line pair is denoted by B a1
• the second bit line of the first bit line pair is denoted by B b1.
• the n-th memory cell connected to the first bit line pair is denoted by Mln.
• Each bit line is provided with a selection transistor.
• the first bit line selection transistor of the first bit line pair is denoted as STBa1.
• a feature of the memory cell array according to the present embodiment is that a P-type shallow shell region forms a third bit line.
• the third bit line connects a shallow Ueno area of a memory cell connected in parallel to a pair of bit lines including a first bit line and a second bit line.
• a selection transistor is connected to this third bit line.
• the first third bit line is described as B wl
• the corresponding selection transistor is described as S T B w l.
• n word lines run in a direction perpendicular to the bit lines and connect the gates of the memory cells.
• each word line is represented by Wl to Wn.
• an electrically insulating element isolation region 16 is formed in the silicon substrate 17 shown in FIGS. 15 to 17, followed by an N-type deep ueno region 25 and a P-type shallow well region 2. 6
• the depth of the junction between the deep N-type Ueno region and the shallow P-type Ueno region is determined by the impurity implantation conditions (implantation energy and implantation amount) and the subsequent thermal process (anneal process, thermal oxidation process, etc.). .
• impurity implantation conditions and thermal process conditions, and the depth of the element isolation region are set so that the element isolation region 16 electrically isolates the P-type shallow p-type region 26.
• the memory film 21 is formed by the procedure described in any of Embodiments 1 to 3, and is patterned by photolithography and etching. After the pattern processing, the polysilicon film in the memory film is exposed, and there is a possibility that the polysilicon film may be short-circuited with a later formed wire. Therefore, it is preferable to perform thermal oxidation. Thereafter, a polysilicon film is formed by chemical vapor deposition (CVD), and the polysilicon film and the memory film 21 are patterned by photolithography and etching to form word lines 11.
• CVD chemical vapor deposition
• the N + diffusion layer 19 is formed in a self-aligned manner.
• the deposition of the inter-glove insulating film, the contact step, and the metal step are repeated to form the first bit line 12 and the second bit line 13.
• the memory cell array of the present embodiment uses the memory film described in any of Embodiments 1 to 3. Therefore, high integration is realized because the element can be miniaturized. Furthermore, since low voltage driving is possible, low power consumption is possible, and the reliability of the memory cell array is improved.
• one cell has an area of 4 F 2 , which is smaller than a conventional AND-type memory cell array (the area of a cell is 8 F 2 3 ⁇ 4!). Therefore, high integration can be achieved, product yield can be improved, and manufacturing costs can be reduced.
• the memory which is the semiconductor device of the present embodiment is mixed with a logic circuit and other memories (DRAM, SRAM, etc.), the integration degree of the integrated circuit can be improved and the function can be improved. it can.
• This embodiment is different from the memory cell array of Embodiment 6 in that the voltage applied to the memory film of the selected memory cell and the voltage applied to the memory film of the non-selected memory cell To a memory cell array with a random access ratio as large as possible.
• the maximum voltage is applied to the memory film of the selected memory cell. Then, a certain voltage is applied to the memory film of the unselected memory cell. Therefore, in order to prevent malfunction, it is preferable to increase the ratio of the voltage applied to the memory film of the selected memory cell to the maximum value of the voltage applied to the memory film of the non-selected memory cell as much as possible.
• the potential of the selected word line is set to V DD
• the potential of the selected bit line is set to the ground potential
• the potentials of other word lines and bit lines are set to V DD Z 2. I do.
• the voltage V D is applied to the memory film of the selected memory cell.
• the voltage 0 or VDDZ 2 is applied to the memory film of the non-selected memory cell.
• the ratio of the voltage applied to the memory film of the selected memory cell to the maximum value of the voltage applied to the memory film of the unselected memory cell is 1/2.
• Table 1 shows the voltages applied to the read lines and the bit lines during writing and erasing in the memory cell array according to the present embodiment.
• the same potential is applied to each bit line (first to third bit lines).
• the potential is 0 on the selected word line, XV DD on the unselected word line, V DD on the selected bit line, and AXV D on the unselected bit line. Is applied.
• DD 1/3 A / 1/2
• the memory of the selected memory cell The ratio between the voltage applied to the film and the maximum value of the voltage applied to the memory film of the unselected memory cell is large, so that random access is possible and a memory with a large operation margin can be realized.
• Embodiment 8 of the present invention will be described below with reference to FIG.
• the memory cell array of the present embodiment is manufactured by using the SOI substrate 160 in the memory cell array of any of the sixth and seventh embodiments, and has the same plan view as FIG. 36 is a body, and 35 is a buried oxide film.
• FIG. 19 is a schematic diagram of a cross section of a memory cell of the memory cell array according to the present embodiment. An independent potential is applied to each column of the body 36 separated by the element isolation region 16 and the buried oxide film 35, and the column is used as a third bit line.
• FIG. 19 shows the case of a fully depleted type, a partially depleted type may be used. In that case, the speed of the element can be increased by reducing the resistance of the body serving as the third bit line.
• the element isolation region 16 is formed on the SOI substrate 160. Thereafter, impurities are implanted into the body 36 so that the memory element has an appropriate threshold. Subsequent formation of the upper structure is the same as the procedure described in the fifth embodiment.
• the following effects are obtained in addition to the effects obtained by the memory cell array of the sixth or seventh embodiment.
• the capacitance between the body and the silicon substrate can be extremely reduced due to the presence of the thick buried oxide film.
• the capacitance between the shallow and deep gall regions is considerably large.
• the use of the SOI substrate makes it possible to extremely reduce the junction capacitance between the N + active layer and the body. Therefore, in the memory cell array of the present embodiment, the current consumption for charging the capacitance can be reduced.
• the depth of the N + active layer can be easily reduced, the short channel effect can be suppressed, and the element can be further miniaturized. For the above reasons, low power consumption and miniaturization can be achieved by using the SOI substrate.
• the integrated circuit can be operated at a low power supply voltage, and the power consumption of the integrated circuit can be reduced.
• the memory element or the semiconductor memory device according to the eighth embodiment and the logic circuit may be mixedly mounted on one integrated circuit.
• other memories DRAM, SRAM, etc.
• the cell area is 4 F 2, which is smaller than the memory cell area of a normal one-transistor nonvolatile memory. Therefore, as the area occupied by the memory can be reduced, the area of the logic circuit and other memories can be increased, and the function can be improved.
• the storage capacity of the memory which is the semiconductor device of this embodiment can be increased.
• control circuit 911 incorporates the semiconductor integrated circuit of the present invention.
• the control circuit 911 may be composed of an LSI in which a memory circuit comprising the semiconductor device of the present invention and a logic circuit are mixed.
• 9 12 is a battery
• 9 13 is an RF circuit section
• 9 14 is a display section
• 9 15 is an antenna section
• 9 16 is a signal line
• 9 17 is a power line.

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