WO2002049251A1 - Dispositif et procédé de réception - Google Patents
Dispositif et procédé de réception Download PDFInfo
- Publication number
- WO2002049251A1 WO2002049251A1 PCT/JP2001/010947 JP0110947W WO0249251A1 WO 2002049251 A1 WO2002049251 A1 WO 2002049251A1 JP 0110947 W JP0110947 W JP 0110947W WO 0249251 A1 WO0249251 A1 WO 0249251A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- bit width
- reference phase
- output
- weighting coefficient
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
- H04B7/0865—Independent weighting, i.e. weights based on own antenna reception parameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
- H04B7/0848—Joint weighting
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
- H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70701—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation featuring pilot assisted reception
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
- H04B7/0848—Joint weighting
- H04B7/0857—Joint weighting using maximum ratio combining techniques, e.g. signal-to- interference ratio [SIR], received signal strenght indication [RSS]
Definitions
- the present invention relates to a receiving apparatus and a method used for a mobile communication system and the like, and particularly to a receiving apparatus and a method for performing coherent demodulation using reference phase information.
- a pilot signal serving as a phase reference for coherent demodulation is used. Is used. This pilot signal is transmitted by a dedicated pilot channel separately from a channel for transmitting data such as audio information.
- the reference phase information and the data are transmitted simultaneously, and the receiving apparatus separates the reference phase information to perform coherent reception.
- FIG. 2 is a block diagram showing an example of a receiving apparatus for performing such coherent reception, and shows an example having two coherent receiving sections 201 and 221.
- a coherent receiving unit 201 includes a receiving antenna 202, an RF (Radio Frequency) receiving unit 203 to which a signal received by the antenna 202 is supplied, and an RF receiving unit.
- a quadrature modulator 204 that quadrature-modulates the signal from 203
- an AD converter 205 that performs AD (analog-to-digital) conversion of the signal from the quadrature modulator 204, and this AD converter 2
- the output from the reference phase despreading unit 206 and the data despreading unit 207 to which the output from the reference signal is supplied, respectively, and the signal from the reference phase despreading unit 206 are supplied.
- the internal configuration of the coherent receiving unit 221 is the same as the internal configuration of the coherent receiving unit 201, and a description thereof will be omitted.
- Outputs from these two coherent receivers 201 and 221 are added by an adder 210 and sent to a frame buffer 211 for storage.
- the outputs from the coherent receivers 201 and 221 are collected in a predetermined unit in the frame buffer 211, for example, one unit, which is a unit for performing a soft decision error correction described later, the output is sent to the multiplier 216.
- Each output from the section is sent to an SNR calculation section 2 12 to calculate an SNR (Signal to Noise Ratio), and the calculated SNR is sent to a weighting coefficient calculation section 2 13 .
- the weighting coefficient from the weighting coefficient calculation unit 211 is sent to the multiplier 214 and multiplied by the output from the frame buffer 211.
- the multiplied output from the multiplier 216 is sent to the bit width limiting section 216.
- the output from the SNR calculator 2 12 is sent to the bit width calculator 2 15 to calculate the bit width, and sent to the bit width limiter 2 16, so that the output from the multiplier 2 14 Bit width is limited.
- the output from the bit width limiting section 216 is sent to the dinning leaver 217 to be interleaved, and then sent to the soft decision input error correcting section 218.
- the reason why the output data from the frame buffer 211 is multiplied by the weighting coefficient from the weighting coefficient calculator 213 is to improve the reception characteristics. This improvement in reception characteristics is due to the following reasons.
- the data of one block or the above one unit is convolutionally coded, interleaved and transmitted, and received by the receiving device as shown in FIG. It is assumed that the data is released, decoded, and restored to the original data. At this time, paying attention to one bit of the original data, this one bit is converted into a code of ((constraint length + 1) / coding rate) by convolutional coding. The information is included in the encoded bit, but these bits are scattered in one cycle during transmission and reception by the interleave.
- the data in the division with a high SNR has a better transmission condition and fewer errors.
- the data in the divided blocks with low SNR has more errors due to poor transmission conditions.
- the received intensity value of the received data is multiplied by the weight calculated for each divided block, and a large weight value is used when the SNR is high, and a small weight value is used when the SNR is small.
- the received data is multiplied by the phase correction information, buffering is performed by a frame buffer and the like, and then the soft-decision input value is obtained using a value based on the SNR of the received data. Weighting multiplication is performed before the weighting coefficient is calculated and input to the soft-decision input error correction unit.
- a multiplier 209 for phase correction and a multiplier for weighting are used in the receiving system that combines the data of the two coherent receiving units 201 and 221.
- the multiplication is performed twice in the adder 214, and the bit width of the adder 210 for frame addition and the frame buffer 211 is large, increasing the circuit scale. .
- a receiving apparatus and a method include: When receiving a signal in which information and data are sent simultaneously, data and reference phase information are separated and received from the received signal, and a phase correction value is calculated based on the separated reference phase information. Calculating a weighting factor based on the phase correction value and the weighting factor, multiplying the separated data by the correction factor, limiting a bit width of the multiplied output, It is characterized in that data of a predetermined unit of output of which bit width is controlled is stored in a storage means, and an error correction is performed on an output from the storage means.
- phase correction value based on the reference phase information is multiplied in advance by a weighting coefficient calculated based on the SNR (signal-to-noise ratio) of the received signal, and the correction coefficient obtained by the multiplication is divided by the separation coefficient.
- SNR signal-to-noise ratio
- FIG. 1 is a block diagram illustrating a schematic configuration of a receiving device according to an embodiment of the present invention.
- FIG. 2 is a block diagram showing a schematic configuration of an example of a conventional CDMA type receiving apparatus.
- BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of a receiving apparatus and a method according to the present invention will be described with reference to the drawings. I will explain this.
- FIG. 1 shows an example of a CD MA (Code Division Multiple Access) receiving apparatus having two coherent receiving sections 101 and 121 as an embodiment of the present invention.
- FIG. 1 For the reference phase information in this example, the pilot signal of a known signal pattern is on a separate channel from the data. (Pilot channel), but the present invention is not limited to this.
- the invention is applicable as long as the data and the reference phase information are transmitted simultaneously and can be separated at the receiving side.
- a coherent receiving unit 101 includes a receiving antenna 102, an RF (Radio Frequency) receiving unit 103 to which a signal received by the antenna 102 is supplied, and an RF receiving unit.
- a quadrature modulator 104 that quadrature-modulates the signal from 103, an AD converter 105 that converts the signal from the quadrature modulator 104 from analog to digital (AD), and this AD converter 1
- the output (correction coefficient) is supplied to and stored in the coefficient register 110, and the output (reception data) ) And the output (correction coefficient) from the coefficient register 110, and the bit width control unit 1 12 to which the output from the multiplier 111 is supplied.
- the signal from the bit width control unit 112 is extracted as an output from the coherent reception unit 101.
- the internal configuration of the coherent receiving unit 121 is the same as the internal configuration of the coherent receiving unit 101, and a description thereof will be omitted.
- the outputs from these two coherent receivers 101 and 121 are added by an adder 117 and sent to a frame buffer 118 for storage.
- the output from the frame buffer 118 is sent to the ding receiver 119, subjected to ding-leave processing, and then sent to the soft-decision input error correction unit 120.
- An error-corrected output is extracted from the soft-decision input error correction unit 120.
- each output for obtaining the transmission path information of the reference phase despreading unit 106 of the coherent receiving unit 101, the despreading unit despreading unit 107, and the base of the coherent receiving unit 1221 Each output for obtaining the transmission path information from the quasi-phase despreading unit and the de-spreading unit is sent to the SNR calculation unit 114 to calculate the SNR (Signal to Noise Ratio). The calculated SNR is sent to the weighting coefficient calculator 115. Weighting The weighting coefficient from the coefficient calculating section 115 is sent to the multiplier 109 of the coherent receiving section 101 and multiplied by the output from the phase correction value calculating section 108 to become a correction coefficient. The same applies to the coherent receiving unit 1 2 1.
- the output from the SNR calculation unit 114 is sent to the bit width calculation unit 115 to calculate the bit width, and the bit width limitation unit 112 of the coherent reception unit 101 and the coherent reception unit The data is sent to the bit width limiting unit of the receiving unit 121.
- One coherent receiver 101 converted the signal received by the RF receiver 103 via the antenna 102 into a complex paceband signal by orthogonally modulating the signal received by the orthogonal modulator 104. Then, it is converted into a digital signal by the AD converter 106.
- the reference phase information and the data are spread by different spreading codes (PN (pseudo noise) codes) and transmitted through different channels (so-called pilot channel and traffic channel).
- PN pseudo noise
- the reference phase information from the reference phase despreading unit 106 is sent to the phase correction value calculation unit 108 to calculate the phase correction value. Also, based on the reference phase information from the reference phase despreading unit 106 and the data signals from the data despreading unit 107, the SNR calculator 114 calculates the SNR value as the transmission path information. Is calculated, and the weighting coefficient calculator 115 calculates the weighting coefficient based on the SNR value. The weighting coefficient from the weighting coefficient calculation section 115 and the phase correction value from the phase correction value calculation section 108 are multiplied by the multiplier 109 and stored in the coefficient register 110 as a correction coefficient.
- the correction coefficient from the coefficient register 110 is sent to the multiplier 111, and is multiplied by the data (reception data) from the data despreading unit 107.
- the reception data is multiplied by the phase correction value and the weighting coefficient first, and then the reception data is multiplied by the correction coefficient.
- the multiplication in the multiplier 111 is performed for each data, but the multiplication in the multiplier 109 is performed every time the SNR is updated, and the number of times of multiplication is small.
- the multiplied output from the multiplier 109 is sent to the bit width control unit 112, where the bit width of the data is limited so that the bit width becomes optimal for error correction in the subsequent stage.
- the bit width control unit 112 calculates the bit width restriction information for determining the bit position to be cut out from the data by the bit width calculation unit 115 using the data from the SNR calculation unit 114. I'm asking.
- the output from the bit width limiter 112 is sent to the adder 117 as the output from the coherent receiver 101.
- the operation of the other coherent receiving unit 121 is the same as the operation of the coherent receiving unit 101 described above, and a description thereof will be omitted.
- Outputs from these two coherent receivers 101 and 121 are sent to an adder 117 and added, accumulated in a frame buffer 118, and stored in a predetermined unit, for example, a soft decision input.
- a predetermined unit for example, a soft decision input.
- the data is sent to the din / reaver 119 and subjected to the interleave processing.
- Sent to 120 The soft-decision input error correction unit 120 performs an error correction process in units of one unit using the video algorithm.
- the reason why weighting based on transmission path information such as SNR of received data is performed as input data to soft decision input error correction section 120 is to improve reception characteristics.
- SNR signal-to-noise ratio
- the phase correction value is multiplied in advance by a weighting value based on SNR to obtain a correction coefficient, and the received data is multiplied by the correction coefficient.
- the number Nr of symbols per unit of the reference phase information output from the reference phase despreading unit 106 and the number of symbols per unit of the output data from the data despreading unit 107 Nd is such that Nr ⁇ Nd.
- the number of multiplications per unit is Nd times in the multiplier 209, and 2 ⁇ Nd times in the two systems of coherent receiving units 201 and 221. , And Nd times in the multiplier 214, so that the total is 3 ⁇ Nd times.
- Nr multiplications by the multiplier 109 in the coherent receiving unit 101 and Nd multiplications by the multiplier 111 are sufficient.
- the number is 2 X (Nr + Nd) per unit.
- the number of multiplications per unit is 3000 in the conventional example of FIG. 2 and 2020 in the embodiment of the present invention in FIG. The number of multiplications can be reduced.
- Nr ⁇ Nd / 2 the number of rides can be reduced by (Nd — 2 x Nr) times per unit, and the effect of the reduction is large when Nr ⁇ Nd.
- the number of Nd multiplications can be reduced.
- bit widths such as multiplication and addition.
- the output of the AD converter 106 is 8 bits
- the outputs of the despreading units 106 and 107 are 8 bits each
- the phase correction calculation unit 1 The phase correction value from 08 and the weighting coefficient value from the weighting coefficient calculation unit are also each 8 bits
- the input to the soft decision input error correction unit 120 is 6 bits.
- the multiplication output becomes 16 bits due to the 8-bit despreading data in the multiplier 209 and the 8-bit phase correction value.
- the result is a 17-bit value, which is stored in the frame buffer 211, and then multiplied by an 8-bit weighting coefficient value to become 25 bits.
- the bit width is limited to 6 bits by a bit width limiting unit 216 and supplied to a soft decision input error correcting unit 218.
- the multiplier 109 multiplies the 8-bit phase correction value by the 8-bit weighting coefficient value, and the output becomes 16 bits.
- the coefficient is stored in the register 110.
- Multiplier 1 1 1 The 16-bit coefficient from bit 110 is multiplied by the 8-bit despread data, and the output becomes 24 bits, but the bit width is limited by the bit width limiting section 112.
- the data is limited to 6 bits, added by the adder 117, rounded to 6 bits, sent to the frame buffer 118, and stored.
- the frame buffer 211 of the conventional example in FIG. 2 requires 25 bits, whereas the frame buffer 11 according to the embodiment of the present invention shown in FIG.
- the 8-bit width is only 6 bits, and the circuit scale of the memory such as the RAM is reduced to about 1/4.
- the embodiment of the present invention when multiplying the reception data (the data from the data de-spreading unit) by the weighting coefficient based on the transmission path information such as the SNR value.
- the transmission path information such as the SNR value.
- the present invention is not limited to only the above-described embodiment.
- an example is shown in which data and reference phase information are transmitted on different channels. Therefore, the present invention can be applied to various transmission methods such as disposing reference phase information in a portion different from data.
- the number of coherent receiving units is not limited to two, but may be three or more.
- the present invention multiplies a phase correction value based on reference phase information by a weighting coefficient in advance, and multiplies the separated data by the multiplied correction coefficient to obtain a multiplication. The amount of calculation such as the number of times can be reduced, and the circuit scale of a memory or the like can be reduced.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20010270971 EP1248402A1 (en) | 2000-12-13 | 2001-12-13 | Receiving device and method |
US10/204,931 US7352828B2 (en) | 2000-12-13 | 2001-12-13 | Receiving apparatus and receiving method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-379282 | 2000-12-13 | ||
JP2000379282A JP2002185430A (ja) | 2000-12-13 | 2000-12-13 | 受信装置及び方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002049251A1 true WO2002049251A1 (fr) | 2002-06-20 |
Family
ID=18847690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/010947 WO2002049251A1 (fr) | 2000-12-13 | 2001-12-13 | Dispositif et procédé de réception |
Country Status (5)
Country | Link |
---|---|
US (1) | US7352828B2 (ja) |
EP (1) | EP1248402A1 (ja) |
JP (1) | JP2002185430A (ja) |
CN (1) | CN1205774C (ja) |
WO (1) | WO2002049251A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3801940B2 (ja) * | 2002-03-28 | 2006-07-26 | 川崎マイクロエレクトロニクス株式会社 | 復調器 |
JP4065859B2 (ja) * | 2004-02-23 | 2008-03-26 | シャープ株式会社 | 受信装置、無線通信装置、無線通信システム、受信方法及び受信プログラムを記録した記録媒体 |
US8358988B2 (en) * | 2006-09-28 | 2013-01-22 | Mediatek Inc. | Interface between chip rate processing and bit rate processing in wireless downlink receiver |
US8358987B2 (en) * | 2006-09-28 | 2013-01-22 | Mediatek Inc. | Re-quantization in downlink receiver bit rate processor |
US8873671B2 (en) * | 2008-03-26 | 2014-10-28 | Qualcomm Incorporated | Method and system for LLR buffer reduction in a wireless communication modem |
US8831546B2 (en) * | 2011-11-07 | 2014-09-09 | Ibiquity Digital Corporation | MRC antenna diversity for FM IBOC digital signals |
US9077442B2 (en) | 2012-07-16 | 2015-07-07 | Texas Instruments Incorporated | DSSS inverted spreading for smart utility networks |
KR20170140225A (ko) * | 2015-04-30 | 2017-12-20 | 마이크로칩 테크놀로지 인코포레이티드 | 향상된 명령어 세트를 구비한 중앙 처리 유닛 |
WO2023243084A1 (ja) * | 2022-06-17 | 2023-12-21 | 日本電信電話株式会社 | データ処理装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1117761A (ja) * | 1997-06-24 | 1999-01-22 | Sony Corp | 受信装置及び送受信装置並びに通信方法 |
JPH1155166A (ja) * | 1997-08-05 | 1999-02-26 | Sony Corp | 受信装置及び無線通信システム並びに通信方法 |
JP2001267960A (ja) * | 2000-03-15 | 2001-09-28 | Nec Corp | Cdma復調装置及びその方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6185200B1 (en) * | 1998-03-13 | 2001-02-06 | Lucent Technologies Inc. | Reverse-link de-interleaving for communication systems based on closed-form expressions |
JP3458841B2 (ja) * | 1998-11-19 | 2003-10-20 | 三菱電機株式会社 | 移動通信システムに適用される受信装置および復調器 |
-
2000
- 2000-12-13 JP JP2000379282A patent/JP2002185430A/ja not_active Withdrawn
-
2001
- 2001-12-13 WO PCT/JP2001/010947 patent/WO2002049251A1/ja not_active Application Discontinuation
- 2001-12-13 EP EP20010270971 patent/EP1248402A1/en not_active Withdrawn
- 2001-12-13 US US10/204,931 patent/US7352828B2/en not_active Expired - Fee Related
- 2001-12-13 CN CNB018049419A patent/CN1205774C/zh not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1117761A (ja) * | 1997-06-24 | 1999-01-22 | Sony Corp | 受信装置及び送受信装置並びに通信方法 |
JPH1155166A (ja) * | 1997-08-05 | 1999-02-26 | Sony Corp | 受信装置及び無線通信システム並びに通信方法 |
JP2001267960A (ja) * | 2000-03-15 | 2001-09-28 | Nec Corp | Cdma復調装置及びその方法 |
Also Published As
Publication number | Publication date |
---|---|
US7352828B2 (en) | 2008-04-01 |
EP1248402A1 (en) | 2002-10-09 |
CN1401168A (zh) | 2003-03-05 |
JP2002185430A (ja) | 2002-06-28 |
CN1205774C (zh) | 2005-06-08 |
US20030091130A1 (en) | 2003-05-15 |
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