WO2002047170A1

WO2002047170A1 - Semiconductor device

Info

Publication number: WO2002047170A1
Application number: PCT/JP2001/007433
Authority: WO
Inventors: Hiroyuki Ohta; Yukihiro Kumagai; Toshio Ando; Hidenori Sato; Akihiro Shimizu
Original assignee: Hitachi, Ltd.
Priority date: 2000-12-08
Filing date: 2001-08-29
Publication date: 2002-06-13
Also published as: JP2002176174A; TW513799B; JP4441109B2

Abstract

A high-reliability, high-speed semiconductor device which can be produced with a reduction in a source/drain current of a p-channel type transistor prevented even when a self-align contact-use silicon nitride film is formed by using a cold-wall-type single-wafer thermal CVD system to lower an inner wall temperature of a chamber to 30 °C or below.

Description

Technical field

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a semiconductor device having a P-channel field-effect transistor.

Background art

Light

In the recent manufacturing process of miniaturized semiconductor integrated circuit devices, MISF ET (Metal Insulator Semiconductor Field Effect Transistor) <is used by utilizing the difference in etching rate between the silicon oxide film and the silicon nitride film. A technique for forming a contact hole in a self-aligned manner with a gate electrode has been used. The formation of such self-aligned contacts (Se Align Contact; SAC) is disclosed, for example, in Japanese Patent Application Laid-Open No. 11-17147. The self-alignment. Silicon nitride film to be used in contour click preparative formation step is generally a monosilane (S i H ₄₎ and ammonia (NH ₃₎ is formed by a thermal CVD method using a gas source. For this thermal CVD system, a hot-hot batch type thermal CVD system that processes a plurality of (for example, about 100) wafers at once is used.

As mentioned above, hot wall type batch thermal CVD equipment has been used to realize self-aligned contacts, but problems have arisen with the progress of high integration, The introduction of a wall-type single-wafer thermal CVD system is under consideration. The background is described below.

Recently, to prevent the threshold voltage of MISFETs (transistors) from decreasing due to miniaturization, the gate electrode of the n-channel MISFET is made of n-type polycrystalline silicon, and the gate electrode of the P-channel MISFET is The so-called dual-gate CMOS structure, which is made of p-type polycrystalline silicon and both are surface channel types, has been adopted.

In this structure, if high-temperature heat treatment is applied in the process after the formation of the gate electrode, p-type or n-type impurities contained in the polycrystalline silicon, which is the gate electrode, become It diffuses into the silicon substrate through the oxide film and easily changes the threshold voltage of the MISFET. Therefore, if the temperature conditions in the heat treatment step vary, the threshold voltage greatly changes, resulting in a large decrease in the yield of semiconductor devices. In other words, even when depositing a silicon nitride film for a contactor line or a contact in the process after the formation of the good electrode, the film formation temperature is high, so it is necessary to precisely control the film formation temperature conditions. However, it is difficult to precisely control temperature conditions with a batch thermal CVD unit.

Therefore, a single-wafer thermal CVD apparatus that processes wafers one by one in a single chamber is easier to set precise temperature conditions than the above-mentioned patch-type thermal CVD apparatus, and has a film thickness within the wafer plane. Because of its good uniformity, application to self-alignment silicon nitride film for contact is being considered. In particular, a cold-wall type single-wafer thermal CVD apparatus that forms a film with the inner wall temperature of the champer lower than the wafer temperature has many advantages because it can compensate for the decrease in throughput that is a problem with single-wafer apparatuses. It is thought to be the mainstream of self-alignment silicon contact film deposition equipment.

However, as a result of studying the introduction of a cold-wall type single-wafer thermal CVD apparatus for the deposition process of silicon nitride film for self-alignment and contact in highly integrated semiconductor devices, the following problems were found. Was found.

A high-density semiconductor device, which used to form a silicon nitride film for self-alignment contact with a hot-wall batch type thermal CVD device, was tested on a cold-wall type single-wafer thermal CVD device. When a silicon nitride film for self-aligned contact was formed, it was observed that the source / drain current of the ρ-channel MISFET was greatly reduced. Reduction of source and drain current needs to be prevented to reduce the operation speed of the semiconductor device. In particular, ρ-channel type MISFETs are a serious problem because their source and drain currents are smaller than those of n-channel MISFETs.

Disclosure of the invention

It is an object of the present invention to prevent fluctuations in the threshold voltage of a MISFET and to prevent a decrease in the source / drain current of a p-channel type MISFET. It is to provide a semiconductor device.

The present invention provides a silicon substrate and a gate oxide film provided on the surface thereof, a gate electrode film provided in contact with the gate oxide film, a sidewall film provided on a side surface of the good electrode film, A silicon nitride film provided so as to include the gate electrode film and the sidewall film, wherein the silicon nitride film has a tensile stress of 850 MPa or less at room temperature. A semiconductor device characterized in that the sidewall film has a bow I tensile stress of 850 MPa or less at room temperature.

Alternatively, the present invention provides a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of forming a gate electrode pattern, Forming a sidewall film, and depositing a silicon nitride film so as to include the gut electrode film and the sidewall film, wherein the silicon nitride film is formed by using a CVD device and the CVD device. A method of manufacturing a semiconductor device, wherein the inner wall temperature of the chamber is reduced to 30 ° C. or lower.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment of the present invention.

Figure 2 is a graph showing the experimental results of the stress dependence of the source / drain current of a p-channel field-effect transistor.

FIG. 3 is a graph showing the relationship between the minimum line width of the semiconductor device and the stress dependence of the source / drain current of the p-channel field-effect transistor.

Fig. 4 is a graph showing the relationship between the film stress of the silicon nitride film for self-aligned contact and the stress in the silicon substrate near the good electrode by stress analysis.

Fig. 5 shows the experimental results showing the relationship between the inner wall temperature of the chamber of the above-mentioned CVD device and the film stress of the silicon nitride film formed by the device when formed by a cold wall type single wafer thermal CVD device. FIG.

Fig. 6 shows the temperature of the inner wall of the chamber of the CVD device and the silicon nitride film formed by the cold wall type single-wafer thermal CVD device. FIG. 9 is a schematic diagram of an experimental result showing a relationship with a variation in stress.

FIG. 7 is a conceptual diagram of a cold-wall single-wafer thermal CVD apparatus 100 used for forming the silicon nitride film 19 for self-alignment contact.

FIG. 8 is a graph showing the relationship between the film stress of a silicon nitride film at room temperature and the etching rate of the silicon nitride film with hot phosphoric acid.

FIG. 9 is a schematic sectional view showing a part of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a schematic sectional view showing a part of a semiconductor device according to a third embodiment of the present invention. FIG. 11 is a schematic sectional view showing a part of a semiconductor device according to a fourth embodiment of the present invention. FIG. 12 is a schematic sectional view showing a part of a semiconductor device according to a second other embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In order to achieve the above object, the present invention provides a silicon substrate and a gate oxide film provided on a surface thereof, a gate electrode film provided in contact with the gate oxide film, and a gate electrode film provided on a side surface of the gate electrode film. A silicon nitride film provided so as to enclose the good electrode film and the silo film, wherein the silicon nitride film has a tensile strength of 850 MPa or less at room temperature. A semiconductor device characterized by having a stress, or the sidewall film has a tensile stress of 850 MPa or less at room temperature.

Alternatively, the present invention provides a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of forming a gate electrode pattern, Forming a sidewall film, and depositing a silicon nitride film so as to include the gate electrode film and the sidewall film. The silicon nitride film is formed by using a CVD apparatus. Provided is a method for manufacturing a semiconductor device, wherein the inner wall temperature of a chamber of a CVD device is deposited at 30 ° C. or less.

Specifically, for example, a gate oxide film can be formed by thermal oxidation or CVD. Further, a gate electrode film can be formed by a sputtering method or a CVD method. In addition, a pattern of the gate electrode is locally formed by photolithography. Also, the side wall is formed by sputtering or CVD. Forming a film. Further, the sidewall film is etched to leave the sidewall film only on the side surface of the gate electrode film. Then, a silicon nitride film is deposited so as to include the gate electrode film and the sidewall film. For example, a cold-wall type single-wafer thermal CVD apparatus is used for the deposition of the silicon nitride film.

Alternatively, the silicon nitride film of the sidewall film is deposited by using a CVD device at an inner wall temperature of 30 ° C. or lower of the chamber of the CVD device.

Alternatively, the present invention provides a silicon substrate and a gate oxide film provided on the surface thereof; and a gate electrode film provided in contact with the gut oxide film, and a side provided on a side surface of the gate electrode film. In a semiconductor device having a wall film, and a silicon nitride film provided so as to include the gate electrode film and the sidewall film, an etching rate of the silicon nitride film against hot phosphoric acid at 120 ° C. is ll nm / It is characterized by being less than min.

Alternatively, the sidewall film includes a silicon nitride film, and an etching rate of the silicon nitride film with respect to hot phosphoric acid at 120 ° C. is ll nm / min or less.

Alternatively, the present invention provides a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of locally forming a pattern of the gut electrode, Forming a film, etching the sidewall film to leave the sidewall film on a side surface of the good electrode film, and enclosing the gate electrode film and the sidewall film. Depositing a silicon nitride film for self-alignment contact, and ion-implanting the silicon nitride film after depositing the silicon nitride film for self-alignment contact by a CVD method. It is characterized by. The ionic species is Si or Ge or a combination thereof.

Further, the present invention is characterized in that the upper surface of the silicon nitride film contains an element having a higher concentration than the lower surface. The element is Si or Ge or a combination thereof.

In addition, as a result of experiments by the inventors, this phenomenon of source / drain current drop is half It became clear that the miniaturization of conductor devices has progressed, and it has become remarkable when the minimum line width is 0.25 microns or less.

Therefore, according to the present invention, even when the integration density of a semiconductor device advances, the threshold voltage of the MISFET is prevented from fluctuating, and the source-drain current of the p-channel type MISFET is reduced and fluctuated. Thus, a high-speed and highly reliable semiconductor device can be provided.

In addition, fluctuations in the threshold voltage of the MISFET and a decrease in the source / drain current become apparent at the stage of mass-producing semiconductor devices as a reduction in yield. Therefore, according to the present invention, a semiconductor device with high yield and excellent manufacturing cost can be provided.

As described above, in order to suppress the fluctuation of the threshold voltage of the miniaturized MI SFET, a cold wall type single wafer type thermal CVD apparatus was used as a test for self-line contact. When a semiconductor device with a silicon nitride film is created, the source / drain current of a p-channel MIS FET may drop significantly, or a transistor with a significantly different source / drain current in the wafer plane may be manufactured. Was observed.

The inventors conducted a stress load experiment, a stress analysis, and the like to determine the cause. As a result, (1) When the tensile stress of the silicon nitride film for the self-aligned contact increases, the compressive stress in the silicon substrate near the gate electrode decreases, and the source-drain current of the p-type transistor decreases. (2) As the miniaturization of highly integrated semiconductor devices progresses and the minimum line width falls below 0.25 μm, the stress dependence of the source / drain current rises sharply and rapidly with miniaturization. It became clear that the problem had become apparent.

As an example, Fig. 2 shows the experimental results of the stress dependence of the source / drain current of a p-channel MISFET with a minimum line width of 0.14 microns. In this experiment, a four-point bending test was performed on a silicon substrate on which a semiconductor device was formed, and the characteristics of the transistor were measured while applying a known stress to the silicon substrate surface, which is the device formation region. The directions of the stresses are the uniaxial stress in the channel plane parallel to the source and drain currents flowing through the channel of the field effect transistor (stress parallel to the channel), and the The stress is the uniaxial stress in the channel plane perpendicular to the drain current (stress perpendicular to the channel). The sign of the stress is plus for tensile stress and minus for compressive stress. In the case of a channel-type field-effect transistor, the source-drain current increases (approximately 4 o / o! OOMPa) in the direction perpendicular to the channel when a tensile stress is applied, and in the direction parallel to the channel. Thus, it was found that the source / drain current decreased (about 7% / 100MPa). Also, from this result, in the case of biaxial stress in the channel plane, in the case of a p-channel field-effect transistor, when the biaxial stress having the same absolute value acts, the tensile stress of the silicon substrate under the gate electrode increases as the tensile stress increases. On the other hand, it is expected that the source-drain current will decrease as the compressive stress decreases in some levels.

Fig. 3 shows the change in the stress dependence of the source-drain current when the gate width was changed. When the gut width or the minimum line width is large, the stress dependency is small, and it is hidden by other fluctuation factors such as process variation.However, when the minimum line width is less than 0.25 μm, the stress dependency sharply increases. Become larger. In other words, this problem was the first one that became a problem in the manufacture of semiconductor devices as a result of the progress of high integration of semiconductor devices.

Therefore, considering the above experimental results, it can be seen that even if the semiconductor device is miniaturized to a minimum line width of 0.25 micron or less, in order to prevent source / drain current from decreasing, the silicon substrate near the good electrode must be It can be seen that it is sufficient to increase the compressive stress as much as possible. The inventors have realized that in order to realize this, it is only necessary to control the film stress of the silicon nitride film for the self-alignment contact.

Therefore, in order to clarify the film stress of the silicon nitride film to increase the compressive stress in the silicon substrate near the gate electrode, the ff dimension was determined by stress analysis using the finite element method. Figure 4 shows the relationship between the stress in the silicon substrate near the gate, which affects the change in source and drain current, and the stress in the silicon nitride film for self-aligned contact. From this relationship, it was clarified that the smaller the tensile stress of the film stress of the silicon nitride film, the more the compressive stress in the silicon substrate near the gate can be increased.

As described above, the inventors of the present invention have developed a silicon nitride film for self-aligned contact. It was found that by forming the film so that the tensile stress becomes small in a state where the film stress is at room temperature, it is possible to prevent a decrease in the source / drain current. Therefore, it would be sufficient if this could be realized using a cold wall type single wafer thermal CVD apparatus.

The authors examined the relationship between the film formation conditions of a cold-dwell type single-wafer thermal CVD system and the film stress of the silicon nitride film to be formed at room temperature. Was found to be able to reduce the film stress. Figure 5 shows the relationship between the temperature of the chamber and the film stress of the cold wall type single wafer thermal CVD apparatus. When the temperature of the chamber of the cold wall type single-wafer thermal CVD apparatus becomes 30 ° C. or more, the film stress of the silicon nitride film increases remarkably. That is, by setting the temperature of the chamber of the cold-wall type single-wafer thermal CVD apparatus to 30 ° C. or less, the tensile stress of the silicon nitride film can be suppressed low. Since it is possible to increase the compressive stress of the p-channel MISFET, it is possible to prevent the source / drain current of the p-channel MISFET from dropping significantly.

Fig. 6 shows the relationship between the temperature of the chamber and the width of variation of the film stress in the single-wafer thermal CVD apparatus of the coal dwell type. A similar relationship is also observed for variations in film stress, and when the temperature of the chamber of a cold-dual type single-wafer thermal CVD apparatus falls below 30 ° C, the variation in film stress in the wafer plane sharply decreases. Understand.

As described above, a silicon nitride film for self-aligned contact is formed by using a cold wall type single-wafer thermal CVD device so that the temperature of the chamber of the CVD device becomes 30 ° C or less. The tensile stress of the silicon nitride film can be reduced. As a result, the compressive stress in the silicon substrate near the gate electrode can be increased! ) It is possible to prevent a decrease in the source / drain current of the channel type MISFET. In addition, since the film stress of the silicon nitride film for self-align contact in the wafer does not vary, the variation of the compressive stress in the silicon substrate near the gate electrode can be reduced. As a result, variations in the source / drain current in the wafer surface can be suppressed, and the reliability and yield of semiconductor devices can be improved.

Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. The actual In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Fig. 1 is a schematic diagram of the cross section of the semiconductor device of this embodiment. Fig. 2 is the stress dependence of the source-drain current of the p-channel field-effect transistor. Fig. 4 shows a stress analysis of the effect of the intrinsic stress of the SiN film enclosing the gate electrode from the top surface on the channel partial stress (stress in the channel plane parallel to the source / drain current). Results, Fig. 5 shows the relationship between the inner wall temperature of the champer and the film stress, Fig. 6 shows the relationship between the inner wall temperature of the chamber and the variation of the film stress in the wafer surface, and Fig. 7 shows the single-wall thermal CVD system of the common wall type. FIG. 8 is a conceptual diagram, FIG. 8 is an etching rate dependency of the SiN film stress, and FIG. 9 to FIG. 11 are explanatory diagrams of an embodiment of the present invention.

As shown in FIG. 1, the semiconductor device of this embodiment includes an n-channel field-effect transistor に formed on the main surface of a silicon substrate 1 and a p-channel field-effect transistor 30.

The n-channel field-effect transistor is composed of an _n- type source 'drain (12, 13) formed in a p-type well 11, a gate insulating film 14, a gate electrode 15, and a side wall 16; Silicides 17 and 18 are formed on the upper surface of the source and drains (12, 13). Further, a silicon nitride film 19 1 for a self-line contact is formed above the contact hole and wiring.

Similarly, the P-channel field-effect transistor of the present invention focuses on the p-type source / drain (32, 33) formed in the n-type well 31 and the gate insulating film 34, the gate electrode 35, the side wall. The silicides 37 and 38 are formed on the upper surface of the gate electrode 35 and the upper surfaces of the source and drain (32, 33). Further, a silicon nitride film 39 for self-line contact, a contact hole, a wiring, and an interlayer insulating film are formed thereon. These Trang registers a silicon oxide film (S i 0 ₂₎ and consists of silicon nitride (S i N), the device isolation film 2, the insulation of the other transistor is made.

The material of the gut insulating films 14 and 34 is, for example, silicon oxide film (S i Op;), Silicon nitride film (S i N), titanium oxide (T I_〇 _2), zirconium oxide (Z r 〇 _2), hafnium oxide (H f 〇 ₂₎ Yuden such tantalum pentoxide (T a ₂ 0 ₅₎ A body film or a laminated structure thereof is desirable. The material of the gate electrodes 15 and 35 is, for example, a polycrystalline silicon film or a material such as tungsten (W), molybdenum (Μο), platinum (Pt), ruthenium (Ru), or iridium (Ir). A metal film, a silicide of these metals, or a laminated structure thereof is desirable. As the material of the support id walls 16, 36, the silicon nitride film (S i N) and silico phosphorylation film (S i 0 _2), the polycrystalline silicon film is desirable.

The silicon nitride film 39 for self-aligned contact is used to form contact holes in a self-aligning manner, and the thickness of the silicon nitride film 39 is preferably in the range of 10 plates to 200 nra. The silicon nitride film 39 is formed by a cold wafer type single wafer thermal CVD apparatus.

FIG. 7 is a conceptual diagram of a cold wall type single-wafer thermal CVD apparatus 100 used for forming the silicon nitride film 39 for the self-alignment contact. A stage 102 on which the silicon substrate 1 is mounted is provided at the center of the chamber 101 of the cold wall type single wafer thermal CVD apparatus 100. Inside the stage 102, a heater 104 for heating the silicon substrate 1 is provided. Above the stage 102, a shuttle gas for supplying a source gas composed of monosilane (SiH ₄ ) and ammonia (NH ₃ ) to the surface of the silicon substrate 1 together with a carrier gas such as nitrogen (N ₂ ) is provided. C 103 is provided. Outside the chamber 101, a temperature control mechanism 105 for setting the inner wall of the chamber 101 at a lower temperature than the stage 102 and the silicon substrate 1 is provided. The temperature control mechanism 105 is provided with a temperature indicator 106. The temperature control mechanism 105 can be configured to include, for example, a detection unit that detects a wall surface temperature by a temperature sensor or the like, and a control unit that controls the wall surface temperature to a predetermined temperature based on a signal from the detection unit.

The cold-wall type single-wafer thermal CVD apparatus 100 processes silicon substrates 1 one by one on the stage 102, so that more precise temperature conditions can be realized compared to the conventional patch-type thermal CVD apparatus. . Therefore, since the temperature of the silicon substrate 1 can be accurately controlled, the diffusion of impurities into the Si substrate can be controlled. Even when the data is miniaturized, it is possible to suppress the occurrence of fluctuations and variations in the value voltage. Another advantage is that the film thickness uniformity within the wafer surface is better than that of a conventional batch type thermal CVD apparatus.

In particular, the temperature control mechanism 105 controls the temperature of the inner wall of the chamber 101, and the stage 102 ゃ a cold-wafer type single-wafer thermal C VD apparatus 10 for forming a film at a lower temperature than the silicon substrate 1. At 0, most of the source gas reacts on the surface of the wafer composed of the silicon substrate 1 and the like to form a film, and the film hardly deposits on the inner wall of the low-temperature champer 101 Therefore, high-throughput film formation becomes possible. In contrast, in a hot-wall type thermal CVD apparatus that uniformly heats the entire inner wall of the chamber 101 to form a film, the film is easily deposited on the inner wall of the chamber 101, and the film is deposited. Throughput decreases because periodic removal is required.

When a cold-wall type single wafer thermal CVD apparatus 100 is used, the silicon nitride film 39 is formed under the following conditions: the temperature of the silicon substrate 1 is set between 700 ° C. and 800 ° C. The gas pressure was set between 200 Torr and 350 Torr. Also, it is preferable to use a silane-based gas and an ammonia gas as a gas source so that the flow ratio of the ammonia gas to the silane-based gas is at least 14 times. As a specific example, the flow rate of monosilane was 70 sccm, the flow rate of ammonia was 1000 sccm, the flow rate of nitrogen was 7000 sccm, and the gas pressure was 350 Torr. The temperature of the wall surface of the chamber 101 was kept at 30 ° C. or lower. In this example, monosilane was used as the silane-based gas, but disilane, dichlorosilane, and tetraethoxysilane may also be used. Further, instead of ammonia, an organic compound containing a cyano group or an amino group can be used.

Also, what is desired for the CVD device is to have a wall temperature control mechanism or a temperature display function associated with the CVD device. In order to keep the temperature of the wall surface of the chamber 101 at 30 ° C. or less, it is desirable to cool with water, and furthermore, a water cooling system using one chiller unit must be provided.

As a result, the film stress at room temperature of the silicon nitride film 39 for the self-aligned contact can be reduced to a tensile stress of 850 MPa or less, and the silicon nitride film acts to reduce the silicon stress near the gate electrode 35. Reduce the stress of the substrate 31 to the more compressive stress side. Can be Here, it is described that "the stress should be on the compressive stress side" .This means that if the stress of the silicon substrate 31 near the gate electrode 35 was conventionally a tensile stress, the tensile stress would be lower. In other words, if the stress of the silicon substrate 31 near the gate electrode 35 is the conventional compressive stress, it means that the compressive stress is higher. As described above, by reducing the stress of the silicon substrate 31 near the gate electrode 35 to the compressive stress side, it is possible to prevent a decrease in the source-drain current of the p-channel transistor.

Further, when forming the silicon nitride film 39, a chamber of a cold wall type single wafer thermal CVD apparatus is used, and the temperature of the wall surface of the chamber 101 is set to 30 ° C. or less. Since variations in stress in the wafer surface can be suppressed, variations in source / drain current of the p-channel transistor in the wafer surface can be prevented. As a result, the reliability of the semiconductor device is improved and the yield can be improved.

From the viewpoint of stress, it is desirable to keep the inner wall temperature of the chamber 101 at 30 ° C. or lower, but in that case, the etching rate rises, so that when forming the self-aligned contacts. There is a disadvantage that processing becomes difficult because the difference in etch rate from the gate electrode portion is small. Considering this, as a next best measure, the inner wall temperature of the champer 101 may be set to 35 ° C or less.

Since the lower limit temperature differs depending on the cooling means, it will not be described in detail. For example, when a cooling medium such as water is used, the temperature is higher than 0 ° C. at which solidification occurs. However, if the water contains antifreeze, the temperature will be higher than the solidification temperature.

It is known that there is a clear relationship as shown in FIG. 8 between the film stress of the silicon nitride film at room temperature and the etching rate of the silicon nitride film formed under the above conditions by hot phosphoric acid. . From this, when the film stress of a silicon nitride film formed by a cold wall type single wafer thermal CVD apparatus is 850 MPa or less, the etching rate by hot phosphoric acid at 120 ° C is 1 lnm / min or more. It turns out that it becomes.

FIG. 9 shows a second embodiment of the present invention. In the present embodiment, the side wall 36 is formed by a cold dwell type single wafer thermal CVD apparatus, and the temperature of the chamber of the CVD apparatus is set to 30 ° C. or lower. As a result, the sidewall 36 is constructed. The film stress at room temperature of the silicon nitride film to be formed can be set to a tensile stress of 850 MPa or less. By the action of the silicon nitride film, the stress of the silicon substrate 31 in the vicinity below the gate electrode 35 becomes more compressive stress side. can do. This can prevent a decrease in the source-drain current of the p-channel transistor. The sidewall 36 may be formed of a silicon nitride film and a silicon nitride film. In this case, the silicon nitride portion may be formed under the above conditions. That is, a silicon nitride film of a sidewall 36 is manufactured under a film forming condition in which a chamber of the CVD apparatus is formed at a temperature of 30.degree. As shown in FIG. 12, even when there is no silicon nitride film for a self-aligned contact, the same effect can be obtained by applying the present invention.

This embodiment has the following features in addition to the advantages listed in the first embodiment of the present invention. That is, if a silicon nitride film of sidewall 36 is formed under a film forming condition of forming a cold wall type single wafer type thermal CVD apparatus and setting a temperature of a chamber of the CVD apparatus to 30 ° C. or lower. Since the number of hydrogen atoms contained in the silicon nitride film can be reduced, electric characteristics of the transistor can be improved.

FIG. 10 shows a third embodiment of the present invention. In addition to the sidewalls 36, a silicon nitride film 39 for a self-align contact is also manufactured under the above conditions. The stress of the silicon substrate under the electrode can be made more tensile, and the effect is further increased. In the case of this embodiment, since both the sidewall 36 and the silicon nitride film 19 for the self-aligned contact are made of exactly the same material, the sidewall 16 and the self-aligned contact are not used. Since the stress concentration at the material interface of the silicon nitride film 39 is reduced, there is an advantage that the risk of film peeling at the interface is small, in addition to the advantage of the second embodiment.

FIG. 11 shows a fourth embodiment of the present invention, in which the sidewall 36 is composed of two or more layers, and one or more of these layers is formed as a silicon film. The film may be formed under the above conditions. In this embodiment, the sidewall 36 is formed by a combination of the silicon oxide film and the silicon nitride film, and the silicon oxide film is in contact with the silicon substrate. In this embodiment, the silicon nitride film directly contacts the silicon substrate This has the further advantage that impurities such as nitrogen in silicon nitride are unlikely to diffuse into the silicon substrate. Similarly, since a silicon oxide film exists between the silicon nitride film and the silicon substrate, the stress of the silicon nitride film is relaxed by the oxy-silicon film, so that the generation of dislocations in the silicon substrate is suppressed. There is the additional benefit of preventing it.

Further, a fifth embodiment of the present invention will be described with reference to FIGS. In this embodiment, after a silicon nitride film 39 for self-aligned contact is formed, ions are implanted into the entire upper surface of the silicon nitride film. That is, the silicon nitride film 39 is formed, and then ion implantation is performed on the entire surface of the wafer. After that, the silicon nitride film is locally etched to perform a via forming process. The same effect can be obtained by changing the order and performing ion implantation after processing for via formation, but in this case, ions are also implanted into the silicon substrate in the via formation hole. This is not desirable because it is likely to cause dislocations. According to this embodiment, since the ion is implanted into the silicon nitride film, the film stress of the silicon nitride film 39 can be made more compressive, that is, the tensile stress can be reduced. The stress of the silicon substrate 31 near the lower part of the gate electrode 35 can be made to be more on the compressive stress side. As a result, a decrease in the source / drain current of the p-channel transistor can be prevented. In addition, since ion implantation is performed on the entire upper surface of the silicon nitride film 39, there is an advantage that a mask for ion implantation is not required and the number of steps or masks can be reduced. In the case of the configuration shown in FIG. 12, the sidewall portion may be formed as described above.

This embodiment may be combined with the first, second, and third embodiments of the present invention, but is effective even if used alone, and in that case, other advantages also occur. For example, when the monosilane flow rate is 10 sccm, the ammonia flow rate is 5000 sccm, the nitrogen flow rate is 5000 sccm, and the gas pressure is 350 Torr, the silicon nitride film 39 for self-alignment contact is formed. Is extremely higher than the tensile strength of 1 GPa. On the other hand, the impurity in the silicon nitride film 39 is reduced, and there is an advantage that the influence of the diffusion of the impurity on the silicon substrate can be minimized. According to the conventional technology, reducing the impurities in the silicon nitride film is one of the electrical characteristics of the device. On the other hand, the tensile stress of the silicon nitride film increases, which causes a decrease in the source / drain current of the p-channel transistor. This phenomenon is remarkable when the minimum line width is 0.25 μm or less. It has become. By applying this embodiment, under the film formation conditions for reducing impurities, the tensile film stress of the silicon nitride film 39 can be reduced or the compressive film stress can be increased, so that the miniaturization is advanced. Even in such a case, it is possible to prevent the source / drain current of the p-channel transistor from being lowered, and to further minimize the influence of impurities.

As the ion species used for the ion implantation treatment, those having an ion radius larger than Si are desirable because of a large change in stress, and Ge and Si that do not have a risk of changing the electrical characteristics of the device are more desirable. If the ion species are assumed to be commonly used in the semiconductor industry such as Ga, As, In, Sb, Tl, and Bi, the investment in the ion implanter or its peripheral equipment must be invested because the existing equipment can be used. The advantage is that it can be minimized. The acceleration voltage is desirably about lOkeV to about 200 KeV depending on the thickness of the silicon nitride film 39. When the film thickness is small, the acceleration voltage tends to be low. The dose is desirably in the range of ^{10 12} to ^{10 16} dose Zcm ² . When this embodiment is performed, these ion species are detected in the silicon nitride film, and the concentration distribution in the thickness direction is peculiar to the ion implantation process, and the upper surface of the film has a higher concentration than the lower surface.

Industrial applicability

According to the present invention, it is possible to provide a high-speed and highly-reliable semiconductor device that prevents fluctuation of the threshold voltage of the MISFET and prevents a decrease in the source-drain current of the p-channel MISFET.

Claims

The scope of the claims

1. a silicon substrate, a gate oxide film provided on the surface thereof, a good electrode film provided in contact with the gate oxide film, a side wall film provided on a side surface of the good electrode film, A semiconductor device comprising: a silicon nitride film provided so as to include a gate electrode film and a sidewall film; wherein the silicon nitride film has a tensile stress of 850 MPa or less at room temperature.

2. It has a silicon substrate, a gate oxide film provided on the surface thereof, a gut electrode film provided in contact with the gate oxide film, and a side wall film provided on a side surface of the gut electrode film. In the semiconductor device, the sidewall film has a tensile stress of 850 MPa or less at room temperature.

3. a silicon substrate, a gate oxide film provided on the surface thereof, a gut electrode film provided in contact with the gate oxide film, and silicon nitride provided on a side surface of the gut electrode film. In a semiconductor device having a sidewall film including a film, a silicon nitride film provided so as to include the gate electrode film and the sidewall film, the silicon nitride film and the sidewall film may be 850 MPa at room temperature. A semiconductor device having the following tensile stress.

4. a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of forming a pattern of a gate electrode, and forming the side wall film on a side surface of the gate electrode film. Forming a silicon nitride film so as to include the gut electrode film and the side wall film, wherein the silicon nitride film is formed by using a CVD device to form a champer of the CVD device. A method for manufacturing a semiconductor device, wherein the deposition is performed at an inner wall temperature of 30 ° C. or lower.

5. a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of depositing a silicon nitride film to form a sidewall film, and etching the sidewall film. And leaving the sidewall film on the side surface of the good electrode film by performing a CVD process. The silicon nitride film of the sidewall film is formed by using a CVD device to measure the inner wall temperature of the chamber of the CVD device. And depositing at a temperature of 30 ° C. or less.

6. a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of forming a side wall film, and etching the side wall film to form the gate electrode film. A step of leaving the sidewall film on a side surface, and a step of depositing a silicon nitride film for a self-aligned contact so as to include the gate electrode film and the sidewall film. The semiconductor device according to claim 1, wherein the silicon nitride film and the silicon nitride film for the self-alignment contact are deposited by using a CVD apparatus at an inner wall temperature of 30 ° C. or lower in a chamber of the CVD apparatus. Production method.

7. A silicon substrate and a gate oxide film provided on the surface thereof, a gate electrode film provided in contact with the gate oxide film, a sidewall film provided on a side surface of the gate electrode film, and the gate In a semiconductor device having a silicon nitride film provided so as to include an electrode film and a sidewall film, an etching rate force of the silicon nitride film to hot phosphoric acid at 120 ° C. is not more than Sllnm / fflin. Characteristic semiconductor device.

8. a silicon substrate and a gate oxide film provided on the surface thereof, a gate electrode film provided in contact with the gate oxide film, and a sidewall film provided on a side surface of the good electrode film. A semiconductor device having at least a sidewall film including a silicon nitride film, wherein an etching rate of the silicon nitride film to hot phosphoric acid at 120 ° C. is 1 lnm / min or less. .

9. A silicon substrate and a gate oxide film provided on the surface thereof, a gate electrode film provided in contact with the gate oxide film, and a silicon nitride film provided on a side surface of the gate electrode film. A silicon nitride film provided so as to include the gate electrode film and the sidewall film, and a nitride film forming the sidewall film with the silicon nitride film. A silicon film is a semiconductor device characterized in that the etching rate with respect to hot phosphoric acid at 120 ° C. is not more than ll nm / min.

10. A step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of locally forming a pattern of the gate electrode, and a step of forming a sidewall film Etching the sidewall film A step of leaving the sidewall film on the side surface of the gate electrode film, and a step of depositing a silicon nitride film for self-alignment contact so as to include the gate electrode film and the sidewall film. Then, after depositing the silicon nitride film for the self-aligned contact, ion implantation is performed on the silicon nitride film.

11. A step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of locally forming a pattern of the gate electrode, and a step of forming a side wall film Etching the sidewall film to leave the sidewall film on the side surface of the gate electrode film; and nitriding for self-align contact so as to include the gate electrode film and the sidewall film. A method of manufacturing a semiconductor device, comprising: depositing a silicon film; and ion-implanting the sidewall film after depositing the sidewall film.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the ionic species is Si or Ge or a combination thereof.

13. a silicon substrate and a gate oxide film provided on the surface thereof, a gut electrode film provided in contact with the gate oxide film, and a sidewall film provided on a side surface of the gate electrode film; and A silicon nitride film provided so as to include the gate electrode film and the sidewall film, wherein an upper surface of the silicon nitride film contains an element having a higher concentration than a lower surface. Semiconductor

14. The semiconductor integrated circuit device according to claim 12, wherein the element is Si, Ge, or a combination thereof.