TW513799B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW513799B
TW513799B TW90120919A TW90120919A TW513799B TW 513799 B TW513799 B TW 513799B TW 90120919 A TW90120919 A TW 90120919A TW 90120919 A TW90120919 A TW 90120919A TW 513799 B TW513799 B TW 513799B
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Taiwan
Prior art keywords
film
gate electrode
silicon nitride
side wall
nitride film
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TW90120919A
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Chinese (zh)
Inventor
Hiroyuki Ohta
Yukihiro Kumagai
Toshio Ando
Hidenori Sato
Akihiro Shimizu
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In order to cope with dimension reduction of transistor, the present invention provides a high-reliability, high-speed semiconductor device, which can prevent a reduction in a source/drain current of a p-channel type transistor even when a silicon nitride film for a self-aligned contact is formed by using a cold-wall-type single-wafer thermal CVD system. When the silicon nitride film used for the self-aligned contact is being formed, a cold-wall-type single-wafer thermal CVD is used to for a sidewall with the inner wall temperature of the process chamber maintained at 30 DEG C or below.

Description

513799 A7 _ _ B7 _ 五、發明説明（1) 本發明係關於半導體積體電路裝置，及其製造方法， 特別是關於，具有p通道型場效電晶體之半導體裝置。 (請先閱讀背面之注意事項再填寫本頁) 最近之細微化之半導體基體電路裝置之製造處理程序 ’係採用，利用氧 化矽膜與氮化矽膜之蝕刻速度差，藉此以自行匹配方 式對 MISFET (Metal Insulator Semiconductor Field Effect513799 A7 _ _ B7 _ V. Description of the invention (1) The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and particularly to a semiconductor device having a p-channel field effect transistor. (Please read the precautions on the back before filling in this page.) The recent miniaturization of the semiconductor substrate circuit device manufacturing process is adopted. It uses the difference in etching speed between the silicon oxide film and the silicon nitride film to self-match. For MISFET (Metal Insulator Semiconductor Field Effect

Transistor)之閘電極形成接觸孔之技術。有關於這種自對準 接觸（Self Align Contact : SAC)之形成示於，例如；日本國 特開平11 - 17147號。在此自對準接觸之形成過程使用之 矽氮化膜，一般係藉由用甲矽烷（SiH4)及氨氣（NH3)爲瓦斯源 之熱CVD法形成。此熱CVD裝置使用能夠整批處理多片（ 例如100片左右）晶圓之熱壁型之整批型熱CVD裝置。 如上述，以往在實現自對準接觸時使用熱壁型之整批 型熱CVD裝置，但隨著高度積體化卻發生一些問題點，因 此目前是在檢討引進冷壁型之葉片式熱CVD裝置之階段。 先說明其背景如下。 經濟部智慧財產局員工消費合作社印製(Transistor) gate electrode forming contact hole technology. The formation of such a self-aligned contact (SAC) is shown in, for example, Japanese Patent Application Laid-Open No. 11-17147. The silicon nitride film used in the formation of the self-aligned contact is generally formed by a thermal CVD method using silane (SiH4) and ammonia (NH3) as gas sources. This thermal CVD apparatus uses a thermal batch type thermal CVD apparatus capable of processing a plurality of wafers (for example, about 100 wafers) in a batch. As mentioned above, in the past, when a self-aligned contact was used, a batch-type thermal CVD device with a hot wall type was used. However, some problems occurred with the high integration. Therefore, the introduction of a cold-wall type blade thermal CVD is currently under review. Installation phase. First explain its background as follows. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

最近，爲了防止隨著細微化而發生之MISFET(電晶體） 之啓始値電壓降低，而採用，以η型多晶矽構成η通道型 MISFET之閘電極，以ρ型多晶矽構成ρ通道型MISFET之 閘電極，兩者均用表面通道型之所謂雙閘（Dual Gate)CM〇S 構造。 這種構造在形成閘電極後之製程加上高溫之熱處理時 ，含在閘電極之多晶矽中之P型或η型之雜質將通過閘極 氧化膜擴散至矽基板，很容易使MISFET之啓始値電壓發生 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4- 513799 A7 B7 五、發明説明（2) (請先閲讀背面之注意事項再填寫本頁) 變動。因之，上述熱處理製程之溫度條件有參差不齊時， 啓始値電壓便大幅度變動，其結果是，使半導體裝置之生 產性大幅度降低。亦即，在形成閘電極後之製程堆積自對 準接觸用等之氮化矽膜時，也是因爲溫度很高，需要特別 精密測量成膜之溫度條件，但整批式熱CVD裝置要精密控 制溫度條件很困難。 因此，由於在一個處理室內每次處理一片之葉片式熱 CVD裝置，較上述整批式熱CVD裝置容易設定溫度條件， 且晶圓面內之膜厚度均一性也良好，因此正在檢討應用在 自對準接觸用氮化矽膜之成膜。尤其是使處理室內壁溫度 較晶圓溫度低之低溫進行成膜之冷壁型之葉片式熱CVD裝 置，因爲具有可以補償葉片式裝置成爲問題之總生產量之 降低之優點，因此被認爲會成爲自對準接觸用氮化矽膜之 成膜裝置之主流。 然而，本發明人等在經過檢討將冷壁型之葉片式熱 CVD裝置引進高積體半導體裝置之自對準接觸用氮化矽膜 之成膜處理之結果，發現有下列問題。 經濟部智慧財產局員工消費合作社印製 在傳統上以熱壁型之整批式熱CVD裝置形成自對準接 觸用氮化矽膜之高績體半導體裝置，試驗性使用冷壁型之 葉片式熱CVD裝置形成自對準接觸用氮化矽膜之結果，觀 察到P通道型MISFET之源極♦汲極電流大幅度降低之情形 。源極·汲極電流之降低會使半導體裝置之動作速度降低 ，因此必須防止。尤其是p通道型MISFET因源極♦汲極電 流較η通道型MISFET小，因此這個問題很嚴重。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _5_ 513799 A7 B7 五、發明説明（3) 因此，本發明之目的在提供，可防止MISFET之啓始値 電壓之變動，且可防止P通道型MISFET之源極·汲極電流 降低之高速，同時可靠性高之半導體裝置。 爲了達成上述課題，本發明係一種半導體裝置，具備 有，砂基板、設在其表面之_極氧化膜、接觸於上述聞極 氧化膜狀配設之閘電極膜、設在上述閘電極膜側面之側壁 膜、以及，內含上述閘電極膜及側壁膜狀配設之氮化矽膜 ，上述氮化矽膜在室溫時具有850 Mpa之牽引應力，爲其 特徵。或上述側壁膜在室溫時具有850 Mpa之牽引應力， 爲其特徵。 同時，本發明係具備有：在矽基板上形成閘極氧化膜 之製程；在其上面形成閘電極膜之製程；形成閘電極之圖 案之製程；在上述閘電極膜之側面形成上述側壁膜之製程 ;以及，以包含上述閘電極膜及上述側壁膜狀堆積氮化矽 膜之製程，上述氮化矽膜係使用CVD裝置，使上述CVD裝 置之處理室之內壁溫度在30 °C以下，以進行堆積爲其其特 具體上是，例如可以藉由熱氧化或CVD法形成閘極氧 化膜。同時可以藉由濺鍍法或CVD法形成閘電極氧化膜。 同時可藉由光平版印刷術局部性形成閘電極之圖案。同時 可藉由濺鍍法或CVD法形成側壁膜。同時可藉由蝕刻側壁 膜，僅令上述閘電極膜之側面殘留上述側壁膜。而以內包 上述閘電極膜與上述側壁膜之狀態堆積氮化矽膜。而在堆 積上述氮化矽膜時，係例如使用冷壁型之葉片式熱CVD裝 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' " -6 - I —*--t------ (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 513799 A7 B7 五、發明説明（4) 置。 (請先閲讀背面之注意事項再填寫本頁) 或，上述側壁膜之氮化矽膜係使用CVD裝置，使上述 CVD裝置之處理室之內壁溫度在30。(：以下，以進行堆積 ，爲其特徵。 同時，本發明係一種半導體裝置，具備有，矽基板、 設在其表面之閘極氧化膜、接觸於上述閘極氧化膜狀配設 之閘電極膜、設在上述閘電極膜側面之側壁膜、以及，內 含上述閘電極膜及側壁膜狀配設之氮化矽膜，上述氮化矽 膜對1 2 0 ° C之熱磷酸之蝕刻率在11 n m / m i η以下，爲其特 徵。 或者，上述側壁膜含有氮化矽膜，上述氮化矽膜對i 2〇 。(：之熱磷酸之蝕刻率在11 nm/min以下，爲其特徵。 經濟部智慧財產局員工消費合作社印製 同時，本發明係具備有：在矽基板上形成閘極氧化膜 之製程；在其上面形成閘電極膜之製程；.局部性形成閘電 極之圖案之製程；形成側壁膜之製程；蝕刻上述側壁膜， 藉此使上述側壁膜殘留在上述閘電極膜之側面之製程；以 及，以內含上述閘電極膜及上述側壁膜狀堆積自對準接觸 用之氮化矽膜之製程，藉由CVD法堆積上述自對準接觸用 之氮化矽膜後，在上述氮化矽膜注入離子爲其特徵。再者 ，上述離子種係S i或G e或此等之組合。 同時，本發明係上述氮化矽膜之上面含有濃度較下面 爲尚之兀素’爲其特徵。再者，上述元素係Si或Ge或 此等之組合。 同時，根據發明人等之實驗之結果發現，此項源極· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 513799 Α7 Β7 五、發明説明（5) 汲極電流之降低現象，在半導體裝置之細微化進展，最小 邊緣寬度變成〇· 25 μιη以下便會很顯著。 (請先閲讀背面之注意事項再填寫本頁) 因之’可以藉由本發明提供，半導體裝置之高積體化 充分進展時，仍可防止MISFET之啓始値電壓之變動，同時 可以防止P通道型MISFET之源極·汲極電流之降低或變動 ，高速且可靠性高之半導體裝置。 同時’ MISFET之啓始値電壓之變動或源極·汲極電流 之減少，在半導體裝置之量產階段成爲生產量之降低而顯 現化。 因之’可以藉由本發明提供，生產性良好，製造成本 低之半導體裝置。 再者，如上述，以抑制細微化MISFET之啓始値電路之 變動爲目的，試驗性使用冷壁型之業片式熱CVD裝置，製 成形成自對準接觸用之氮化矽膜之半導體裝置之結果，可 以觀察到，有時會製成p通道型MISFET之源極·汲極電流 大幅度降低，或在晶圓面內源極·汲極電流有大幅度之差 異之電晶體。 經濟部智慧財產局員工消費合作社印製 爲了查明其原因，由發明人等進行應力負荷實驗或應 力解析等。其結果，發現（1)當自對準接觸用氮化矽膜之牽 引力增加時，閘電極附近之矽基板內之壓縮應力減少，因 此，P型電晶體之源極·汲極電流會減少，（2)高積體度半 導體裝置之細微化進展，最小邊緣寬度變成0· 25 μιη以下 時，源極♦汲極電流之應力依存性便會急激上昇，隨著細 微化使問題快速顯現化。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） "" -8- 513799 A7 B7 五、發明説明（6) (請先閱讀背面之注意事項再填寫本頁) 第2圖表示，最小邊緣寬度〇. 14 μιη之p通道型 MISFET之源極·汲極電流之應力依存性之一個例子之實驗 結果。本實驗係對形成半導體裝置之矽基板進行4點彎曲 試驗，在裝置形成領域之砍基板表面施加已知應力之負荷 ，同時測試電晶體之特性。應力之方向係與流通場效電晶 體之通道之源極·汲極電流之方向成平行方向之通道面內 單軸應力（平行於通道之應力），及垂直於源極·汲極電流之 方向之通道面內單軸應力（垂直於通道之應力），應力之記號 係正表示牽引應力，負表示壓縮應力。ρ通道型場效電晶體 時，加上牽引應力時，對垂直於通道方向，源極·汲極電 流會增加（約4 % / 100 MPa)，但對平行於通道方向，源極 •汲極電流會減少（約 7 % / 100 MPa)。 同時，從此結果 可以推測，若是通道面內之雙軸應力，P通道型場效電晶體 在作用有絕對値相同之雙軸應力時，閘電極下之矽基板之 牽引力愈大，或者壓縮應力愈小，源極·汲極電流會減少 〇 經濟部智慧財產局員工消費合作社印製 第3圖表示令閘極寬度變化時之源極·汲極電流之應 力依存性之變化。閘極寬度亦即最小邊緣寬度大時應力依 存性小，會被處理程序等之參差不齊等其他要因蓋掉，但 最小邊緣寬度縮小到〇· 25 μιη以下時，應力依存性便會急 激變大。亦即，本課題係半導體裝置之高積體化進展之結 果，始成爲半導體裝置之製造上之問題。 因此，若依據以上之實驗結果進行探討，要使半導體 裝置細微化到最小線寬度〇. 25 μιη以下，源極·汲極電流 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）~' -9- 513799 A7 B7 五、發明説明（7) (請先閱讀背面之注意事項再填寫本頁) 仍不會減少，儘量增加閘電極附近之矽基板內之壓縮應力 即可。發明人等注意到，若能控制自對準接觸用氮化矽膜 之膜應力便能夠實現。 於是，爲了淸楚瞭解，要增加閘電極附近之矽基板內 之壓縮應力，應如何控制氮化矽膜之膜應力，而進行使用 有限要素法之應力解析之檢討。第4圖表示對源極·汲極 電流之變化有影響之閘電極近旁之矽基板內之應力，與對 準接觸用之氮化矽膜之膜應力之關係。從此關係可以暸解 ，上述氮化矽膜之膜應力之牽引應力愈小，愈能夠增加閘 電極近旁之矽基板內之壓縮應力。 如以上所述，發明人等發現，如果在成膜時使自對準 接觸用之氮化矽膜之膜應力在室溫狀態下之牽引應力較小 ，便能夠防止源極·汲極電流降低。因此，能夠使用冷壁 型之葉片式熱CVD裝置加以實現便可以。 經濟部智慧財產局員工消費合作社印製 於是調查冷壁型之葉片式熱CVD裝置之成膜條件與成 膜之氮化矽膜在室溫下之膜應力之關係之結果，注意到， 在某特殊成膜條件之範圍內可以使牽引之膜應力減少。第5 圖表示冷壁型之葉片式熱CVD裝置之處理室溫度與膜應力 之關係。冷壁型之葉片式熱CVD裝置之處理室內溫度到達 30 °C以上時，氮化矽膜之膜應力便會顯著增加。亦即，使 冷壁型之葉片式熱CVD裝置之處理室內溫度在30 °C以下 ，便可以抑制氮化矽膜之牽引應力，藉此，可以增加閘電 極附近之矽基板內之壓縮應力，因此，可以防止P通道型 MISFET之源極·汲極電流大幅度降低。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ -10- 513799 A7 B7 五、發明説明（8) (請先閲讀背面之注意事項再填寫本頁) 第6圖表示冷壁型之葉片式熱CVD裝置之處理室內 溫度與膜應力之參差不齊幅度之關係。膜應力之參差不齊 也顯示同樣之關係，可以看出，冷壁型之葉片式熱CVD裝 置之處理室內溫度變成30。(：以下時，膜應力在晶圓面內之 參差不齊會急遽變小。 如以上所述，使用冷壁型之葉片式熱CVD裝置，以 CVD裝置之處理室內溫度30 °C以下之情況，對自對準接 觸用之氮化矽膜進行成膜，則可以減低上述氮化矽膜之牽 引應力。藉此便可以增加閘電極附近之矽基板內之壓縮應 力，因此，可以防止P通道型MISFET之源極·汲極電流減 少。同時，藉此可以使晶圓面內之自對準接觸用之氮化矽 膜之膜應力之不再有參差不齊，因此，閘電極附近之矽基 板內之壓縮應力之參差不齊也可以變小。其結果，’可以抑 制源極·汲極電流在晶圓面內之參差不齊，因而可以提高 半導體裝置之可靠性及生產性。 經濟部智慧財產局員工消費合作社印製 茲參照附圖詳細說明本發明之第1實施例之形態如下 。再者，在用以說明實施形態之所有圖式，具有相同功能 者標示相同之記號，省略重複之說明。 第1圖係本實施例之半導體裝置之截面之模式圖，第2 圖係P通道型場效電晶體之源極·汲極電流之應力依存性 ，第3圖係隨著裝置之細微化，源極♦汲極電流對應力之 變化率，第4圖係以應力解析分析法從上面分析閘電極之 內含SiN膜之真性應力對通道部分應力（平行於源極·汲極 電流，通道面內之應力）造成之影響之結果，第5圖係處理 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 513799 A7 _ B7 _ 五、發明説明（9) (請先閱讀背面之注意事項再填寫本頁) 室之內壁溫度與膜應力之關係，第6圖係處理室之內壁溫 度與上述膜應力之晶圓面內參差不齊之關係，第7圖係冷 壁型之葉片式熱CVD裝置之槪念圖，第8圖係SiN膜應力 之鈾刻率依存性，第9圖至第11圖係本發明之實施例之說 明圖。 本實施例之半導體裝置係如第1圖所示，由形成在矽 基板1之主面之η通道型場效電晶體10，及p通道型場效 電晶體30，所構成。 其中之η通道型場效電晶體係由形成在ρ型井11之η 型源極、汲極（12、13)、閘極絕緣膜14、閘電極15、.及側 壁1 6所構成，在閘電極1 5之上面，及源極、汲極（1 2、1 3) 之上面形成有矽化物17、1 8。並在其上方形成有自對準接 觸用之氮化矽膜19或接觸孔、配線。 同時，本發明著眼點之Ρ通道型場效電晶體也同樣， 經濟部智慧財產局員工消費合作社印製 由形成在η型井31之ρ型源極、汲極（32、33)、閘極絕緣 膜34、閘電極35、及側壁36所構成，在閘電極35之上面 ，及源極、汲極（32、33)之上面形成有矽化物37、38。並在 其上方形成有自對準接觸用氮化矽膜39或接觸孔、配線。 此等電晶體係由矽氧化膜（SiOO或氮化矽（SiN)所構成，而藉 由元件分離膜2與其他電晶體絕緣。 閘極絕緣膜14、34之材料以使用，例如，矽氧化膜 (SiCh)、氮化砍膜（SiN)、氧化鈦（Τι〇2)、氧化鈽（ZrO〇、HfCh 、五氧化釔（Ta2〇5)等之電介質膜，或者此等之積層構造較 佳。而，閘電極15、35之材料則可以使用，例如，鎢（W) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -12- 513799 A7 B7 五、發明説明（ (請先閲讀背面之注意事項再填寫本頁} 、鋁（Mo)、白金（Pt)、釕（RU)、銥（1〇等之金屬膜或此等金屬 之矽化物，或者此等之積層構造較佳。側壁1 6、3 6之材料 以使用氮化矽膜（SiN)、矽氧化膜（Si02)、或多晶矽膜較佳。 自對準接觸用氮化矽膜39係用以自行匹配方式形成 接觸孔，上述氮化矽膜39之厚度以10 nm〜200 nm之範圍 較理想。上述氮化矽膜39係以冷壁型之葉片式熱CVD裝置 形成。 經濟部智慧財產局員工消費合作社印製 第7圖係形成上述自對準接觸用之氮化矽膜39之冷壁 型之葉片式熱CVD裝置1〇〇之槪念圖。在冷壁型之葉片式 熱CVD裝置100之處理室1〇1之中央部設有用以載置矽基 板1之平台102。平台102之內部設有用以對矽基板1加熱 之加熱器104。在平台102之上方設有用以將由甲矽烷 (SiH〇及氨器（NH〇構成之原料氣體連同氮氣（N2)等之載送氣 體一起供給矽基板1表面之噴淋頭1 03。同時。在處理室 101之外部設有用以將處理室101之內壁設定成較平台102 或矽基板1爲低溫之調溫機構1 05。調溫機構1 05設有溫度 顯示器106。上述調溫機構105可以是例如備有藉由溫度感 測器等檢測壁面溫度之檢測部，及依據檢測部之信號將壁 面溫度控制在一定溫度之控制部等之架構。 由於冷壁型之葉片式熱CVD裝置100是在平台102上 一次一片方式處理矽基板1，因此，較之傳統之整批式熱 CVD裝置，可以實現精密之溫度控制。因爲矽基板1之溫 度控制正確，可以控制雜質向Si基板內之擴散，電晶體被 細微化時，仍可以抑制啓始値電壓之變動或參差不齊。同 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -13- 513799 A7 B7 五、發明説明（1) 時也有’較之傳統之整批式熱CVD裝置，晶圓面內之膜厚 度均一性良好之優點。 (請先閲讀背面之注意事項再填寫本頁) 尤其是在’藉由調溫機構1 〇5控制處理室1 〇丨之內壁 溫度’使其較平台102或矽基板1爲低溫，以進行成膜之 冷壁型之葉片式熱CVD裝置10〇，原料氣體之大部分與矽 基板1等構成之晶圓之表面起反應形成膜，溫度低之處理 室101之內壁則幾乎不會堆積膜，因此可以達成總生產量 局之成膜。對此’將處理室1 0 1之整個內壁同樣加熱以進 行成膜之熱壁型之熱CVD裝置，因爲處理室101之內壁也 很容易堆積膜，必須定期去除上述膜，因此總生產量會降 低。 經濟部智慧財產局員工消費合作社印製 使用冷壁型之葉片式熱CVD裝置100時之上述氮化矽 膜39之成膜條件是，矽基板1之溫度設定在700 °C至 800 °C之間，而氣體壓力則設定在200Torr至350Torr之間 。同時，使用矽烷系氣體及氨氣作爲原料氣體，而使氨氣 對砂院系氣體之流量比達14倍以上較佳。舉一具體例子如 下，甲矽烷流量70 seem、氨氣流量1〇〇〇 sccm、氮氣流量 7000 seem、氣壓350ΤΟΠ*。同時，處理室1〇1之壁面溫度則 保持在30 °C以下。本實施例之矽烷系氣體係使用甲矽烷， 但也可以使用乙砂焼、二氯砂院（dichlorosilane)、四乙氧基 矽烷（Tetraethoxy-silane)。也可以用含有氰基、氨基之有機 材料代替氨氣。 同時，對CVD裝置之要求是，最好在上述CVD裝置附 設壁面溫度控制機構。或溫度之顯示功能。要將處理室101 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14- 513799 A7 ___ B7 五、發明説明（ 之溫度保持在30 °C以下，用水冷卻最理想，如果能具備使 用致冷設備（C h i 11 i n g u n i t)之水冷系統更佳。 (請先閱讀背面之注意事項再填寫本頁) 藉此可以使自對準接觸用之氮化矽膜39之室溫時之膜 應力在850 MPa以下，可以藉由上述氮化矽膜之作用使閘 電極3 5下近旁之矽基板3 1之應力更靠壓縮應力側。在此 所說明之「更靠壓縮應力側」之意思是，如果閘電極35附 近之矽基板31之應力在以往是牽引應力時，則使其成爲更 低之牽引應力，如果閘電極35附近之矽基板3 1之應力在 以往是壓縮應力時，則使其成爲更高之壓縮應力。如此， 閘電極35近旁之矽基板31之應力更靠壓縮應力側，便可 以防止P通道型電晶體之源極•汲極電流之減少。 同時，如果上述氮化矽膜39之成膜使用冷壁型之葉片 式熱CVD裝置之處理室，使該處理室101之壁面溫度在30 °C以下，便可以抑制晶圓面內之應力之參差不齊，因此可 以防止晶圓面內之p通道型電晶體之源極·汲極電流之參 差不齊。藉此可以提高半導體裝置之可靠性，同時可以提 高生產量。 經濟部智慧財產局員工消費合作社印製 若從應力之觀點來看，處理室101之內壁溫度最好是 在30 °C以下，但卻有，因爲鈾刻率會上昇，形成自對準接 觸時，與閘電極部之蝕刻率之差變小，致使加工變難之缺 點。若考量這個問題，也可以退一步，使處理室101之內 壁溫度在35 °C以下。 下限之溫度會因冷卻構件而異，因此不特別詳述。例 如使用水等之冷媒時，則是較發生凝固之〇 爲高之溫度 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 513799 A7 B7 五、發明説明（1$ 。但是，如果水中含有不凍成分時，則是到較該凝固溫度 爲局之溫度。 (請先閲讀背面之注意事項再填寫本頁} 再者，氮化矽膜之室溫時之膜應力，與以上述條件成 膜之氮化矽膜之藉熱磷酸之鈾刻率之間，已知存在有如第8 圖所示之明確之關係。從此可以暸解，以冷壁型之葉片式 熱CVD裝置成膜之氮化矽膜之膜應力在850 MPa以下時， 以120 °C之熱磷酸蝕刻時之鈾刻率在11 nm/min以上。 經濟部智慧財產局員工消費合作社印製 第9圖表示本發明之第2實施例。本實施例係藉冷壁 型之葉片式熱CVD裝置形成側壁36，CVD裝置之處理室之 溫度設定在30 °C以下。藉此可以使構成側壁36之氮化矽 膜在室溫下之膜應力在850 MPa以下，因爲上述氮化矽膜 之作用，可以使閘電極3 5近旁之矽基板3 1之應力更靠壓 縮應力側。藉此可以防止p通道型電晶體之源極·汲極電 流減少。側壁36也可以由氮化矽膜及氧化矽膜構成，這時 ，氮化矽之部分可以藉由上述條件作成。亦即，以冷壁型 之葉片式熱CVD裝置形成，使上述CVD裝置之處理室之溫 度設定在30°C以下之成膜條件下製造側壁36之氮化矽膜 。再者’如第1 2圖所示，沒有自對準接觸用之氮化矽膜時 ，若應用本發明，仍可收到同樣之效果。 本實施例在本發明第1實施例所舉之優點以外，另有 下列特徵。亦即，若以冷壁型之葉片式熱CVD裝置形成， 將上述CVD裝置之處理室之溫度設定在30 。(：以下之成 膜條件下製造側壁3 6之氮化矽膜，可以減少上述氮化矽膜 內部所含之氫原子，因此可以使電晶體之電氣特性良好。 本紙張尺度適用中國國家標準（CNS ) A4規格（210'〆297公釐） -16- 經濟部智慧財產局員工消費合作社印製 513799 A7 B7 五、發明説明（ 第10圖表示本發明第3實施例，若除了側壁36以外 ，自對準接觸用之氮化矽膜39也是以上述條件製造，則可 以進一步使閘電極下之矽基板之應力更爲靠近牽引側，效 果更大。本實施例時，由於側壁36與自對準接觸用之氮化 矽膜19之材質完全相同，因此，側壁16與自對準接觸用 之氮化矽膜39之材料介面之應力集中不大，因此，除了第 2實施例之優點以外，另有在界面之膜剝落之危險較少之優 點。 第11圖表示本發明之第4實施例，也可以由兩層以上 之膜形成側壁36，其中之1層以上之膜爲氮化矽膜，而以 上述之條件成膜。本實施例係藉由組合氧化矽膜與氮化矽 膜以構成側壁3 6，氧化矽膜接觸於矽基板。本實施例因氮 化矽膜未直接接觸於矽基板，因此另有氮化矽中之氮等雜 質不易擴散至矽基板之優點。而，同樣在氮化矽膜與矽基 板之間存在有氧化矽膜，氧化矽膜可以緩和氮化矽膜之應 力，因此另有可以防止在矽基板內發生轉位之優點。 再以第11圖及第12圖表示本發明之第5實施例。本 實施例係在彤成自對準接觸用之氮化矽膜39後，在上述氮 化矽膜上面之整面注入離子者。亦即，形成上述氮化矽膜 39，接著，在晶圓表面整面進行離子注入處理。然後，對 上述氮化矽膜進行局部性之蝕刻，進行形成通孔用之加工 。再者，對調此順序，在進行形成通孔之加工後再注入離 子也可以獲得同樣之效果，但如此將在通孔形成孔之部分 之矽基板也注入離子，容易成爲發生轉位之原因，因此不 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） 一 -17- jI —-----βΐ (請先閱讀背面之注意事項再填寫本頁) 訂 513799 A7 _____B7 五、發明説明（1$ 很理想。 (請先閲讀背面之注意事項再填寫本頁) 因爲藉由本實施例在上述氮化膜注入離子，因此可以 使上述氮化矽膜39之膜應力更靠近壓縮側，亦即可以減少 牽引應力，藉此可以使閘電極35下近旁之矽基板31之應 力更靠壓縮應力側。其結果，可以防止p通道型電晶體之 源極·汲極電流減少。同時，離子注入係對上述氮化矽膜 39之上面整面實施，因此不需要注入離子用之掩罩，具有 可以削減製程或掩罩之優點。再者，採第12圖之架構時， 上述側壁部可以形成如上述。 經濟部智慧財產局員工消費合作社印製 本實施例可以與上述第1、第2、第3實施例組合在一 起，但單獨使用也有效果，這時也會產生其他之優點。例 如，以甲砂院流量10 seem、氨氣流量5000 seem、氮氣流 量5000 seem，氣體壓力350 Torr之條件下形成自對準接觸 用之氮化矽膜3 9時，上述氮化矽膜3 9之膜應力爲牽引之1 Gpa以上，非常高，但在另一方面，上述氮化矽膜39中之 雜質減少，而產生可以使上述雜質之擴散對矽基板之影響 減至最小之優點。在傳統之技術，如果使上述氮化矽膜39 中之雜質減少，裝置之電氣特性之1個項目變良好，但在 另一方面，上述氮化矽膜之牽引之膜應力會增加，因此發 生P通道型電晶體之源極•汲極電流減少之弊害，而這種 現象在最小線寬〇, 25 μηι以下時顯現出來。若應用本發明 ，則可以在減少雜質之成膜條件下，使上述氮化矽膜39之 牽引之膜應力減少，或使上述氮化矽膜39之壓縮之膜應力 增加，因此，縱使細微化進展之情況下，仍可以防止ρ通 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -18- 513799 A 7 _ _ _B7_____ 五、發明説明（ 道型電晶體之源極•汲極電流之減少，同時使雜質之影響 爲最小。 (請先閱讀背面之注意事項再填寫本頁) 上述注入離子之處理所使用之離子種以離子半徑較Si 大者因應力變化較大，較理想，不會使裝置之電氣特性變 化之Ge、Si更佳。同時，如果離子種使用半導體產業界常 用之Ga、As、In、Sb、Tl、Bi等，則因可以使用現有設備 ，因此有可以將對離子注入裝置或其周邊設定之投資減至 最少之好處。對應上述氮化矽膜39之厚度，加速電壓以1〇 KeV至200 KeV程度較理想，膜厚度較薄時，有加速電壓 低也可以之傾向。同時，摻雜量在1012〜1016dose/ cm2之範 圍較佳。 實施本實施例時，氮化矽膜中可以檢出此等離子種’ 成爲離子注入處理特有之膜厚度方向濃度分布，膜之上面 之濃度較下面之濃度高。 藉由本發明，可以提供，能夠防止MISFET之啓始値電 壓之變動，且防止P通道型MIS FET之源極•汲極電流之減 少，高速且可靠性高之半導體裝置。 經濟部智慧財產局員工消費合作社印製 圖式之簡單說明 第1圖係表示本發明第1實施例之半導體裝置之截面 之模式圖。 第2圖係P通道型場效電晶體之源極·汲極電流之應 力依存性之實驗結果。 第3圖係表示半導體裝置之最小線寬度，與P通道型 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -19- 513799 A7 B7 五、發明説明（1》 場效電晶體之源極·汲極電流之應力依存性之關係之圖。 (請先閲讀背面之注意事項再填寫本頁) 第4圖係表示藉應力解析求出自對準接觸用之氮化矽 膜之膜應力，及閘電極近旁之矽基板內之應力之關係之結 果之圖。 第5圖係表示以冷壁型之葉片式熱CVD裝置形成時之 上述CVD裝置之處理室內壁溫度，與以上述裝置成膜之氮 化矽膜之膜應力之關係之實驗結果之槪要圖。 第.6圖係表示以冷壁型之葉片式熱CVD裝置形成時之 上述CVD裝置之處理室內壁溫度，與以上述裝置成膜之氮 化矽膜之膜應力之參差不齊之關係之實驗結果之槪要圖。 第7圖係上述自對準接觸用之氮化矽膜19之成膜所使 用之冷壁型之葉片式熱CVD裝置100之槪念圖。 第8圖係表示氮化矽膜在室溫時之膜應力，與氮化矽 膜之藉熱磷酸之蝕刻率之關係之圖。 第9圖係表示本發明之第2實施例之半導體裝置之一 部分之截面模式圖。 經濟部智慧財產局員工消費合作社印製 第10圖係表示本發明之第3實施例之半導體裝置之一 部分之截面模式圖。 第11圖係表示本發明之第4實施例之半導體裝置之一 部分之截面模式圖。 第12圖係表示本發明之第2之其他實施例之半導體裝 置之一部分之截面模式圖。 主要元件對照表 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -20 - 513799 A7 B7 五、發明説明（1$ 1 ------------矽基板 2 ------------元件分離膜 (請先閲讀背面之注意事項再填寫本頁) 3 ------------層間絕緣膜 6------------酉己茅泉 11------------P型井 31------------η型井 12' 13------------η型源極、汲極 32、33------------ρ型源極、汲極 14、 3 4 ------------鬧極絕緣膜 15、 3 5------------聞電極 16、 36------------側壁 17、 18、37、38------------矽化物 19、39----------自對準接觸用氮化矽膜 100 ------------冷壁型之葉片式熱CVD裝置 101 ------------處理室 102 ------------平台 103 ------------噴淋頭 經濟部智慧財產局員工消費合作社印製 104 ----------…加熱器 105 ------------調溫機構 106------------溫度顯示器 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -21 -Recently, in order to prevent the initial voltage of the MISFET (transistor) from decreasing due to miniaturization, the gate electrode of the η-channel MISFET is composed of n-type polycrystalline silicon, and the gate of the ρ-channel MISFET is composed of p-type polycrystalline silicon. The electrodes are both constructed with a so-called dual gate CMOS which is a surface channel type. In this process, when the gate electrode is formed and the high-temperature heat treatment is performed, the P-type or η-type impurities contained in the polycrystalline silicon of the gate electrode will diffuse to the silicon substrate through the gate oxide film, and it is easy to start the MISFET.値 Voltage Occurrence This paper size is subject to Chinese National Standard (CNS) A4 specification (210X297mm) -4- 513799 A7 B7 V. Description of the invention (2) (Please read the precautions on the back before filling this page) Changes. Therefore, when the temperature conditions of the above heat treatment process are uneven, the initial voltage varies greatly. As a result, the productivity of the semiconductor device is greatly reduced. That is, when the silicon nitride film for self-aligned contact is deposited in the process after the gate electrode is formed, it is also because the temperature is very high, and the temperature condition of the film formation needs to be measured precisely, but the batch thermal CVD device must be precisely controlled. Temperature conditions are difficult. Therefore, since a blade-type thermal CVD device that processes one sheet at a time in a processing chamber is easier to set temperature conditions than the above-mentioned batch-type thermal CVD device, and the film thickness uniformity in the wafer surface is also good, it is being reviewed and applied in Film formation of a silicon nitride film for alignment contact. In particular, a cold-wall type blade thermal CVD device that forms a film at a temperature lower than that of the wafer inside the processing chamber is considered to have the advantage of reducing the total throughput of the blade type device, which is a problem. It will become the mainstream of film-forming devices for self-aligned contact silicon nitride films. However, the present inventors have found the following problems as a result of reviewing the film formation process of the self-aligned contact silicon nitride film of a cold-walled leaf type thermal CVD device into a high-integration semiconductor device after review. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a high-performance semiconductor device that traditionally uses a hot-wall type thermal CVD device to form a self-aligned contact silicon nitride film, and experimentally used a cold-wall type blade thermal CVD. As a result of the device forming a silicon nitride film for self-aligned contact, it was observed that the source current of the P-channel type MISFET was greatly reduced. The reduction of the source / drain current will reduce the operating speed of the semiconductor device, so it must be prevented. In particular, the p-channel MISFET has a much smaller drain current than the n-channel MISFET, so this problem is serious. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) _5_ 513799 A7 B7 V. Description of the invention (3) Therefore, the purpose of the present invention is to provide, which can prevent the initial voltage of the MISFET from changing, and can High-speed semiconductor device that prevents the source and sink current of P-channel MISFETs from decreasing. In order to achieve the above-mentioned problem, the present invention is a semiconductor device including a sand substrate, a polar oxide film provided on the surface thereof, a gate electrode film disposed in contact with the above-mentioned odor oxide film, and a side surface of the gate electrode film. The side wall film and the silicon nitride film including the above-mentioned gate electrode film and the side wall film configuration, the above-mentioned silicon nitride film has a traction stress of 850 Mpa at room temperature, which is characteristic. Or the above-mentioned side wall film has a traction stress of 850 Mpa at room temperature, which is characteristic. At the same time, the present invention includes: a process of forming a gate oxide film on a silicon substrate; a process of forming a gate electrode film thereon; a process of forming a pattern of the gate electrode; and a process of forming the sidewall film on the side of the gate electrode film A manufacturing process; and a process of depositing a silicon nitride film in the form of the gate electrode film and the sidewall film, the silicon nitride film uses a CVD device, so that the inner wall temperature of the processing chamber of the CVD device is below 30 ° C, Specifically, the deposition is performed. For example, a gate oxide film can be formed by thermal oxidation or CVD. At the same time, a gate electrode oxide film can be formed by a sputtering method or a CVD method. At the same time, the pattern of the gate electrode can be locally formed by photolithography. At the same time, a sidewall film can be formed by a sputtering method or a CVD method. At the same time, the side wall film can be etched so that only the side wall film of the gate electrode film remains. A silicon nitride film is deposited in a state in which the gate electrode film and the side wall film are enclosed. When stacking the above silicon nitride film, for example, a cold-walled blade-type thermal CVD paper is used. The size of the paper applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) '" -6-I-*- t ------ (Please read the precautions on the back before filling out this page) Order printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy 513799 A7 B7 V. Description of the invention (4). (Please read the precautions on the back before filling this page) Or, the silicon nitride film of the above-mentioned side wall film uses a CVD device, so that the inner wall temperature of the processing chamber of the above CVD device is 30. (: The following is characterized by stacking. At the same time, the present invention is a semiconductor device including a silicon substrate, a gate oxide film provided on the surface thereof, and a gate electrode arranged in contact with the gate oxide film. Film, a side wall film provided on the side of the gate electrode film, and a silicon nitride film containing the gate electrode film and the side wall film, and the etching rate of the silicon nitride film to hot phosphoric acid at 120 ° C Below 11 nm / mi η, it is characterized. Alternatively, the sidewall film contains a silicon nitride film, and the silicon nitride film pair i 2. (The etching rate of hot phosphoric acid is below 11 nm / min, which is Features. At the same time as printing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the present invention is provided with: a process of forming a gate oxide film on a silicon substrate; a process of forming a gate electrode film thereon; and a pattern of locally forming a gate electrode A process of forming a sidewall film; a process of etching the sidewall film so that the sidewall film remains on the side of the gate electrode film; and a self-aligned contact including the gate electrode film and the sidewall film In the manufacturing process of the silicon nitride film, the CVD method is used to deposit the silicon nitride film for self-aligned contact, and then implanting ions into the silicon nitride film is a feature. Furthermore, the ion species is Si or Ge Or the combination thereof. Meanwhile, the present invention is characterized in that the upper surface of the above silicon nitride film has a concentration lower than that of the upper element, which is characteristic. Furthermore, the above-mentioned element is Si or Ge or a combination thereof. Meanwhile, according to the invention, The results of experiments by people and others found that the source and the paper size are in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 513799 Α7 Β7 V. Description of the invention (5) The phenomenon of the reduction of the drain current in semiconductor devices With the progress of miniaturization, the minimum edge width will become significant below 0.25 μm. (Please read the precautions on the back before filling in this page.) Therefore, the advanced integration of semiconductor devices can be provided by the present invention. At the same time, it is possible to prevent the initial voltage of the MISFET from changing, and at the same time prevent the source channel and sink current of the P-channel MISFET from decreasing or changing, and a high-speed and highly reliable semiconductor device. At the beginning, a change in voltage or a decrease in source and drain currents is manifested as a decrease in production volume during the mass production stage of a semiconductor device. Therefore, it can be provided by the present invention with good productivity and low manufacturing cost. In addition, as described above, for the purpose of suppressing the variation of the start-up circuit of the miniaturized MISFET, a cold-wall type wafer thermal CVD device is experimentally used to form silicon nitride for self-aligned contact formation. As a result of the film semiconductor device, it can be observed that the source-drain current of a p-channel type MISFET may be greatly reduced, or the source-drain current may be significantly different in the wafer surface. Crystal. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. To find out the reason, the inventors and others conducted stress load experiments or stress analysis. As a result, it was found that (1) when the traction force of the silicon nitride film for self-aligned contact increases, the compressive stress in the silicon substrate near the gate electrode decreases, so the source and sink current of the P-type transistor will decrease, (2) As the miniaturization of high-integration semiconductor devices progresses, when the minimum edge width becomes 0 · 25 μιη or less, the stress dependency of the source current and the drain current will increase sharply, and the problem will quickly become apparent with the miniaturization. This paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) " " -8- 513799 A7 B7 V. Description of invention (6) (Please read the precautions on the back before filling this page) Figure 2 It shows the experimental results of an example of the stress dependence of the source and sink current of a p-channel MISFET with a minimum edge width of 0.1 μm. This experiment is a 4-point bending test on a silicon substrate forming a semiconductor device. A known stress is applied to the surface of the substrate in the device formation field, and the characteristics of the transistor are tested at the same time. The direction of stress is the uniaxial stress (the stress parallel to the channel) in the plane of the channel parallel to the direction of the source and drain current of the channel through the field effect transistor, and the direction perpendicular to the source and drain current. The uniaxial stress in the channel plane (the stress perpendicular to the channel), the sign of the stress is positive to indicate traction stress, and negative to indicate compressive stress. For ρ-channel field-effect transistor, when traction stress is added, the source and drain current will increase (approximately 4% / 100 MPa) for the direction perpendicular to the channel, but for the source and drain parallel to the channel direction The current will decrease (approximately 7% / 100 MPa). At the same time, it can be inferred from this result that if the biaxial stress in the channel plane, the P-channel field effect transistor has the same biaxial stress, the greater the traction force of the silicon substrate under the gate electrode, or the more compressive stress The source and sink currents will be reduced. The third figure printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs shows the stress dependence of source and sink currents when the gate width is changed. When the gate width, that is, the minimum edge width is large, the stress dependency is small, and it will be covered by other factors such as unevenness of the processing program. However, when the minimum edge width is reduced to less than 0.25 μm, the stress dependency will be sharply changed. Big. That is, the subject is the result of the advancement of high integration of semiconductor devices, which has become a problem in the manufacture of semiconductor devices. Therefore, if the discussion is based on the above experimental results, the semiconductor device must be miniaturized to a minimum line width of 0.25 μm or less, and the source and sink currents should be in accordance with the Chinese National Standard (CNS) A4 specification (210 × 297 mm). ~ '-9- 513799 A7 B7 V. Description of the invention (7) (Please read the precautions on the back before filling in this page) It will still not decrease, try to increase the compressive stress in the silicon substrate near the gate electrode as much as possible. The inventors noticed that the film stress of the silicon nitride film for self-aligned contact can be controlled. Therefore, in order to understand clearly, to increase the compressive stress in the silicon substrate near the gate electrode, how to control the film stress of the silicon nitride film, and conduct a review of stress analysis using the finite element method. Fig. 4 shows the relationship between the stress in the silicon substrate near the gate electrode, which has an effect on the change of the source and sink current, and the film stress of the silicon nitride film used for the alignment contact. It can be understood from this relationship that the smaller the traction stress of the film stress of the above silicon nitride film, the more it can increase the compressive stress in the silicon substrate near the gate electrode. As described above, the inventors have found that if the film stress of the silicon nitride film for self-aligned contact at room temperature is reduced, the traction stress at room temperature is small, and the source / drain current can be prevented from decreasing. . Therefore, it can be realized by using a cold-walled blade type thermal CVD apparatus. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the results of investigating the relationship between film formation conditions of cold-walled leaf-type thermal CVD equipment and film stress of the silicon nitride film formed at room temperature were noted. Within the range of special film forming conditions, the film stress of traction can be reduced. Fig. 5 shows the relationship between the temperature of the processing chamber and the film stress in the cold-walled blade thermal CVD apparatus. When the temperature of the cold-walled blade thermal CVD device reaches more than 30 ° C, the film stress of the silicon nitride film increases significantly. That is, by setting the temperature in the processing chamber of the cold-walled blade thermal CVD device below 30 ° C, the traction stress of the silicon nitride film can be suppressed, thereby increasing the compressive stress in the silicon substrate near the gate electrode. Therefore, it is possible to prevent the source / drain current of the P-channel type MISFET from being greatly reduced. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ~ -10- 513799 A7 B7 V. Description of invention (8) (Please read the precautions on the back before filling this page) Figure 6 shows the cold wall The relationship between the temperature in the processing chamber and the uneven amplitude of the film stress in the blade-type thermal CVD device of the type. The unevenness of the film stress also shows the same relationship. It can be seen that the temperature in the processing chamber of the cold-walled blade thermal CVD device becomes 30. (: In the following cases, the unevenness of the film stress in the wafer surface will be rapidly reduced. As described above, when using a cold-walled blade thermal CVD device, the temperature in the processing chamber of the CVD device is below 30 ° C. By forming the silicon nitride film for self-aligned contact, the traction stress of the silicon nitride film can be reduced. This can increase the compressive stress in the silicon substrate near the gate electrode, so that the P channel can be prevented The source / drain current of the type MISFET is reduced. At the same time, the film stress of the silicon nitride film for self-aligned contact in the wafer surface can no longer be uneven, so the silicon near the gate electrode The variation in the compressive stress in the substrate can also be reduced. As a result, the variation in the source and drain currents within the wafer surface can be suppressed, thereby improving the reliability and productivity of the semiconductor device. Ministry of Economic Affairs Printed by the Intellectual Property Bureau Staff Consumer Cooperatives The detailed description of the first embodiment of the present invention is as follows with reference to the drawings. In addition, in all the drawings used to explain the implementation, those with the same function are marked with the same symbol 1 is a schematic diagram of a cross section of the semiconductor device of this embodiment, and FIG. 2 is a stress dependency of a source-drain current of a P-channel field effect transistor, and FIG. According to the miniaturization of the device, the change rate of the drain current to the stress of the source electrode. Figure 4 is based on the stress analysis method to analyze the true stress of the gate electrode containing the SiN film on the stress of the channel part (parallel to the source electrode.) Figure 5 is the result of the influence caused by the drain current and the stress in the channel plane. Figure 5 deals with the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -11-513799 A7 _ B7 _ V. Description of the invention (9) (Please read the precautions on the back before filling this page) The relationship between the temperature of the inner wall of the chamber and the film stress. Figure 6 shows the unevenness of the temperature of the inner wall of the processing chamber and the wafer surface of the above film stress. Fig. 7 is a conceptual diagram of a cold-walled vane-type thermal CVD apparatus, Fig. 8 is a graph showing dependence of uranium etch rate of SiN film stress, and Figs. 9 to 11 are explanatory diagrams of an embodiment of the present invention The semiconductor device of this embodiment is shown in FIG. The n-channel field-effect transistor 10 and the p-channel field-effect transistor 30 formed on the main surface of the silicon substrate 1 are composed of the n-channel field-effect transistor system formed by the η formed in the p-type well 11 Type source, drain (12, 13), gate insulating film 14, gate electrode 15, and side wall 16 are formed on top of gate electrode 15 and source and drain (1 2, 1 3 ) Are formed with silicides 17, 18, and a silicon nitride film 19 for self-aligned contact, contact holes, and wirings are formed above it. At the same time, the P-channel field effect transistor of the present invention is also focused on. Similarly, the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is composed of a p-type source, a drain (32, 33), a gate insulating film 34, a gate electrode 35, and a sidewall 36 formed in the n-type well 31. Silicides 37 and 38 are formed on the gate electrode 35 and on the source and drain electrodes (32, 33). A silicon nitride film 39 for self-aligned contact, a contact hole, and wiring are formed thereon. These transistor systems are composed of a silicon oxide film (SiOO or silicon nitride (SiN)), and are insulated from other transistors by the element separation film 2. The materials of the gate insulating films 14, 34 are used, for example, silicon oxide Dielectric films such as SiCh, SiN, Titanium Oxide, ZrO0, HfCh, Yttrium Pentoxide (Ta205), or their laminated structures are better And, the materials of the gate electrodes 15, 35 can be used, for example, tungsten (W) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -12- 513799 A7 B7 V. Description of the invention ( (Please read the precautions on the back before filling out this page}, metal films of aluminum (Mo), platinum (Pt), ruthenium (RU), iridium (10 or the like, or silicides of these metals, or their laminates) The structure is better. The material of the side walls 16 and 36 is preferably a silicon nitride film (SiN), a silicon oxide film (Si02), or a polycrystalline silicon film. The silicon nitride film 39 for self-aligned contact is used for self-matching. The contact hole is formed in a manner that the thickness of the silicon nitride film 39 is preferably in a range of 10 nm to 200 nm. The silicon nitride film 39 is Cold-wall type blade thermal CVD device is printed. Figure 7 printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs is a cold-wall type blade thermal CVD device 1 for forming the above-mentioned silicon nitride film 39 for self-aligned contact. 〇 槪 念 图. In the center of the processing chamber 100 of the cold-walled blade thermal CVD apparatus 100 is provided a platform 102 for placing the silicon substrate 1. The inside of the platform 102 is provided for heating the silicon substrate 1. The heater 104. Above the platform 102, a shower head 1 for supplying a source gas composed of silane (SiH0 and ammonia device (NH0) together with a carrier gas such as nitrogen (N2) and the like to the silicon substrate 1 is provided. 03. At the same time, a temperature regulating mechanism 105 for setting the inner wall of the processing chamber 101 to a lower temperature than the platform 102 or the silicon substrate 1 is provided outside the processing chamber 101. The temperature regulating mechanism 105 is provided with a temperature display 106. The above The temperature adjustment mechanism 105 may be a structure provided with, for example, a detection unit that detects a wall surface temperature by using a temperature sensor, and a control unit that controls the wall surface temperature to a certain temperature according to a signal from the detection unit. Thermal CVD apparatus 100 is on the platform 10 2 The silicon substrate 1 was processed one piece at a time last time. Therefore, compared with the traditional batch thermal CVD device, precise temperature control can be achieved. Because the silicon substrate 1 has the correct temperature control, it can control the diffusion of impurities into the Si substrate. When the crystal is miniaturized, it can still suppress the variation or unevenness of the initial voltage. The same paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -13- 513799 A7 B7 V. Description of the invention (1 ) It also has the advantage of better film thickness uniformity within the wafer surface compared to traditional batch thermal CVD equipment. (Please read the precautions on the back before filling in this page) Especially when the temperature of the inner wall of the processing chamber 1 〇 丨 is controlled by the temperature control mechanism 105, it is lower than the platform 102 or the silicon substrate 1 to perform Film-forming cold-walled blade type thermal CVD device 100, most of the raw material gas reacts with the surface of the wafer composed of the silicon substrate 1 to form a film, and the inner wall of the processing chamber 101 with a low temperature hardly accumulates Film, so you can achieve the total production of the film. In response to this, a thermal wall CVD device that heats the entire inner wall of the processing chamber 101 to form a film, because the inner wall of the processing chamber 101 is also easy to deposit films, the above-mentioned films must be removed regularly, so the total production The amount will decrease. The film formation conditions of the above-mentioned silicon nitride film 39 when using a cold-walled blade thermal CVD apparatus 100 printed by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are that the temperature of the silicon substrate 1 is set at 700 ° C to 800 ° C. The gas pressure is set between 200 Torr and 350 Torr. At the same time, it is better to use a silane-based gas and ammonia gas as the raw material gas, so that the flow ratio of ammonia gas to the sand-based gas is more than 14 times. A specific example is as follows. The flow rate of silane is 70 seem, the flow rate of ammonia gas is 1000 sccm, the flow rate of nitrogen gas is 7000 seem, and the air pressure is 350T *. At the same time, the wall temperature of the processing chamber 101 was kept below 30 ° C. In the silane-based gas system of this embodiment, silane is used, but ethalamine, dichlorosilane, and tetraethoxy-silane can also be used. Instead of ammonia, organic materials containing cyano and amino groups can also be used. At the same time, a requirement for a CVD apparatus is that a wall surface temperature control mechanism is preferably attached to the CVD apparatus. Or temperature display function. In order to apply the paper size of the processing room 101 to the Chinese National Standard (CNS) A4 (210X297 mm) -14- 513799 A7 ___ B7 V. Description of the invention (The temperature should be kept below 30 ° C. It is best to use water cooling. It is better to have a water cooling system using a cooling unit (C hi 11 ingunit). (Please read the precautions on the back before filling this page.) This can make the silicon nitride film 39 for self-aligned contact at room temperature. When the film stress is below 850 MPa, the stress of the silicon substrate 31 near the gate electrode 35 can be closer to the compressive stress side by the effect of the above silicon nitride film. The "more compressive stress side" explained here This means that if the stress of the silicon substrate 31 near the gate electrode 35 was a traction stress in the past, it will be made a lower traction stress. If the stress of the silicon substrate 31 near the gate electrode 35 was a compressive stress in the past, This makes it a higher compressive stress. In this way, the stress of the silicon substrate 31 near the gate electrode 35 is closer to the compressive stress side, which can prevent the source and sink current of the P-channel transistor from decreasing. At the same time, if the above The film formation of the silicon nitride film 39 uses a cold-walled blade thermal CVD processing chamber, so that the wall temperature of the processing chamber 101 is below 30 ° C, and the unevenness of the stress in the wafer surface can be suppressed. Therefore, it is possible to prevent uneven source and sink currents of the p-channel transistor in the wafer surface. This can improve the reliability of the semiconductor device and increase the production volume. From the point of view of stress, the temperature of the inner wall of the processing chamber 101 is preferably below 30 ° C, but there is, because the etch rate of uranium will increase, and the self-aligned contact will form an etch rate with the gate electrode portion. The difference becomes smaller, which makes processing difficult. If you consider this problem, you can also take a step back and make the temperature of the inner wall of the processing chamber 101 below 35 ° C. The lower limit temperature will vary depending on the cooling member, so it is not particularly detailed. For example, when using a refrigerant such as water, the temperature is higher than the temperature at which the solidification occurs. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -15- 513799 A7 B7 V. Description of the invention (1 $ .But If the water contains non-freezing ingredients, it is a temperature that is more than the freezing temperature. (Please read the precautions on the back before filling this page} Furthermore, the film stress of silicon nitride film at room temperature, and It is known that there is a clear relationship between the uranium etch rates of the heat-phosphoric acid and the silicon nitride film formed under the above conditions as shown in Fig. 8. From this, it can be understood that the formation of a cold-walled blade thermal CVD device When the film stress of the silicon nitride film is below 850 MPa, the uranium etch rate at the time of etching with hot phosphoric acid at 120 ° C is above 11 nm / min. Printed in Figure 9 by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The second embodiment of the invention. In this embodiment, the side wall 36 is formed by a cold-walled blade type thermal CVD apparatus, and the temperature of the processing chamber of the CVD apparatus is set below 30 ° C. This can make the film stress of the silicon nitride film constituting the side wall 36 at room temperature below 850 MPa, because the effect of the above silicon nitride film can make the stress of the silicon substrate 31 near the gate electrode 35 more compressive. Stress side. This prevents the source and drain current of the p-channel transistor from decreasing. The side wall 36 may be formed of a silicon nitride film and a silicon oxide film. In this case, a portion of the silicon nitride may be formed under the above conditions. That is, a silicon nitride film with a sidewall 36 is formed under a film forming condition in which the temperature of the processing chamber of the CVD device is set below 30 ° C by forming a cold-walled blade-type thermal CVD device. Furthermore, as shown in FIG. 12, when the silicon nitride film for self-aligned contact is not used, the same effect can be obtained if the present invention is applied. This embodiment has the following features in addition to the advantages cited in the first embodiment of the present invention. That is, if it is formed by a cold-wall type blade-type thermal CVD apparatus, the temperature of the processing chamber of the CVD apparatus is set to 30 ° C. (: Manufacture of silicon nitride film with side wall 36 under the following film forming conditions can reduce the hydrogen atoms contained in the silicon nitride film, so that the electrical characteristics of the transistor can be good. This paper size applies to Chinese national standards ( CNS) A4 specification (210'〆297 mm) -16- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513799 A7 B7 V. Description of the invention (Figure 10 shows the third embodiment of the present invention. The silicon nitride film 39 for self-aligned contact is also manufactured under the above-mentioned conditions, so that the stress of the silicon substrate under the gate electrode can be further brought closer to the traction side, and the effect is greater. In this embodiment, since the sidewall 36 and the self-alignment The material of the silicon nitride film 19 for quasi-contact is completely the same. Therefore, the stress concentration of the material interface of the sidewall 16 and the silicon nitride film 39 for self-aligned contact is not large. Therefore, in addition to the advantages of the second embodiment, Another advantage is that there is less danger of film peeling at the interface. Figure 11 shows the fourth embodiment of the present invention, and the side wall 36 can also be formed from two or more films, one of which is a silicon nitride film. While The film was formed under the conditions described above. In this embodiment, a sidewall 36 is formed by combining a silicon oxide film and a silicon nitride film, and the silicon oxide film is in contact with the silicon substrate. In this embodiment, because the silicon nitride film is not directly in contact with the silicon substrate, Therefore, there is an advantage that impurities such as nitrogen in silicon nitride cannot easily diffuse to the silicon substrate. Also, there is a silicon oxide film between the silicon nitride film and the silicon substrate. The silicon oxide film can relieve the stress of the silicon nitride film. Therefore, there is another advantage that the index can be prevented from occurring in the silicon substrate. The fifth embodiment of the present invention is shown in FIG. 11 and FIG. 12. This embodiment is a silicon nitride film for self-aligned contact. After 39, ions are implanted on the entire surface of the silicon nitride film. That is, the silicon nitride film 39 is formed, and then ion implantation is performed on the entire surface of the wafer surface. Then, the silicon nitride film is subjected to ion implantation. Local etching is used to process through holes. Furthermore, the same effect can be obtained by reversing this order and implanting ions after the through hole processing. However, the silicon in the part where the holes are formed in the through holes will be the same. The substrate is also implanted with ions. It is the cause of indexing, so this paper is not applicable. National Standard (CNS) A4 specification (210X297 mm) -17- jI —----- βΐ (Please read the precautions on the back before filling This page) Order 513799 A7 _____B7 V. Description of the invention (1 $ is ideal. (Please read the precautions on the back before filling this page) Because this embodiment implants ions into the above nitride film, the above silicon nitride can be made. The film stress of the film 39 is closer to the compression side, that is, the traction stress can be reduced, so that the stress of the silicon substrate 31 near the gate electrode 35 can be closer to the compression stress side. As a result, the source of the p-channel transistor can be prevented. The drain and drain currents are reduced. At the same time, the ion implantation is performed on the entire surface of the silicon nitride film 39 described above, so that a mask for implanting ions is not required, which has the advantage of reducing the number of processes or masks. In addition, when the structure shown in FIG. 12 is adopted, the side wall portion may be formed as described above. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This embodiment can be combined with the above-mentioned first, second, and third embodiments, but it is also effective when used alone, and other advantages will also occur at this time. For example, when a silicon nitride film 3 9 for self-aligned contact is formed under the conditions of a flow rate of 10 seem in a sand garden, 5000 seem of ammonia flow, 5000 seem of nitrogen flow, and a gas pressure of 350 Torr, the above-mentioned silicon nitride film 3 9 The film stress is 1 Gpa or more, which is very high. However, on the other hand, impurities in the silicon nitride film 39 are reduced, and the advantage that the influence of the diffusion of the impurities on the silicon substrate is minimized is generated. In the conventional technology, if the impurities in the silicon nitride film 39 are reduced, one item of the electrical characteristics of the device becomes better, but on the other hand, the film stress caused by the traction of the silicon nitride film will increase, so The disadvantage of the source-drain current of the P-channel transistor is reduced, and this phenomenon appears at the minimum line width of 0, 25 μηι. If the present invention is applied, the film stress of the traction of the silicon nitride film 39 can be reduced or the film stress of the compressive film of the silicon nitride film 39 can be increased under the film-forming conditions of reducing impurities. In the case of progress, it is still possible to prevent ρ from adapting to the Chinese standard (CNS) A4 specification (210 × 297 mm) of this paper. -18- 513799 A 7 _ _ _B7_____ V. Description of the invention The reduction of the polar current and the influence of impurities are minimized. (Please read the precautions on the back before filling this page.) The ion species used in the above-mentioned ion implantation process have a larger ionic radius than Si due to stress changes. Ideally, Ge and Si that do not change the electrical characteristics of the device are better. At the same time, if Ga, As, In, Sb, Tl, Bi, etc. commonly used in the semiconductor industry are used as the ion species, existing equipment can be used, so It can minimize the investment in the ion implantation device or its surroundings. Corresponding to the thickness of the above silicon nitride film 39, the acceleration voltage is ideal from 10 KeV to 200 KeV, and the film thickness is thin At this time, the acceleration voltage may be low. At the same time, the doping amount is preferably in the range of 1012 to 1016 dose / cm2. When this embodiment is implemented, the plasma species can be detected in the silicon nitride film, which is unique to the ion implantation process. The concentration distribution in the thickness direction of the film, the concentration on the top of the film is higher than the concentration on the bottom. By the present invention, it is possible to prevent the variation of the initial voltage of the MISFET and prevent the source and sink current of the P-channel MIS FET. Reduced, high-speed and high-reliability semiconductor devices. Brief description of printed drawings of employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 1 is a schematic diagram showing a cross-section of a semiconductor device according to the first embodiment of the present invention. It is the experimental result of the stress dependence of the source and drain current of the P-channel field effect transistor. Figure 3 shows the minimum line width of the semiconductor device, and the paper standard of the P-channel type is applicable to the Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -19- 513799 A7 B7 V. Description of the invention (1) The relationship between the stress dependence of the source and drain current of a field effect transistor. (Please read first (Please read the notes on the back and fill in this page again.) Figure 4 is a graph showing the relationship between the stress of the silicon nitride film for self-aligned contact and the stress in the silicon substrate near the gate electrode by stress analysis. Fig. 5 is a summary of the experimental result showing the relationship between the temperature of the processing chamber wall of the CVD device and the film stress of the silicon nitride film formed by the above device when a cold-walled blade thermal CVD device is formed. Fig. 6 shows the uneven relationship between the temperature of the inside wall of the processing chamber of the CVD device and the film stress of the silicon nitride film formed by the above device when a cold-walled blade thermal CVD device is formed. Summary of experimental results. Fig. 7 is a schematic diagram of a cold-walled blade type thermal CVD apparatus 100 used for forming the silicon nitride film 19 for self-aligned contact described above. Fig. 8 is a graph showing the relationship between the film stress of the silicon nitride film at room temperature and the etching rate of the silicon nitride film by thermal phosphoric acid. Fig. 9 is a schematic cross-sectional view showing a part of a semiconductor device according to a second embodiment of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Fig. 10 is a schematic cross-sectional view showing a part of a semiconductor device according to a third embodiment of the present invention. Fig. 11 is a schematic sectional view showing a part of a semiconductor device according to a fourth embodiment of the present invention. Fig. 12 is a schematic cross-sectional view showing a part of a semiconductor device according to a second embodiment of the present invention. Comparison table of main components The paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -20-513799 A7 B7 V. Description of the invention (1 $ 1 ------------ Si substrate 2 ------------ Element separation film (Please read the precautions on the back before filling this page) 3 ------------ Interlayer insulation film 6 ----- ------- Tanji Maoquan 11 ------------ P-type well 31 ------------ η-type well 12 '13 ---- -------- η-type source, drain 32, 33 ------------ ρ-type source, drain 14, 14, 4 --------- --- Alarm insulation film 15, 3 5 ------------ Smell electrode 16, 36 ------------ Side wall 17, 18, 37, 38-- ---------- Silicide 19, 39 ---------- Silicon nitride film for self-aligned contact 100 ------------ Cold-wall type Blade type thermal CVD device 101 ------------ processing chamber 102 ------------ platform 103 ------------ shower Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 104 ----------... Heater 105 ------------ Temperature-adjusting agency 106 -------- ---- Temperature display The paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm) -21-

Claims (1)

經濟部智慧財產局員工消費合作社印製 513799 A8 B8 C8 D8 六、申請專利範圍 1 一種半導體裝置，具備有，矽基板、設在其表面之閘 極氧化膜、接觸於上述閘極氧化膜狀配設之閘電極膜、設 在上述閘電極膜側面之側壁膜、以及，內含上述閘電極膜 及側壁膜狀配設之氮化矽膜，其特徵在於，上述氮化矽膜 在室溫時具有850 Mpa以下之牽引應力。 2 —種半導體裝置，具備有，矽基板、設在其表面之閘 極氧化膜、接觸於上述閘極氧化膜狀配設之閘電極膜、以 及，設在上述閘電極膜側面之側壁膜，其特徵在於，上述 側壁膜在室溫時具有850 Mpa以下之牽引應力。 3 —種半導體裝置，具備有，矽基板、設在其表面之閘 極氧化膜、接觸於上述閘極氧化膜狀配設之閘電極膜、設 在上述閘電極膜側面，包含氮化矽膜之側壁膜、以及，內 含上述閘電極膜及側壁膜狀配設之氮化矽膜，其特徵在於 ，上述氮化矽膜及側壁膜在室溫時具有850 Mpa以下之牽 引應力。 4 一種半導體裝置之製造方法，其特徵在於，具備有： 在矽基板上形成閘極氧化膜之製程；在其上面形成閘電極. 膜之製程；形成閘電極之圖案之製程；在上述閘電極膜之 側面形成上述側壁膜之製程；以及，以包含上述閘電極膜 及上述側壁膜狀堆積氮化矽膜之製程·，上述氮化矽膜係使 用CVD裝置，使上述CVD裝置之處理室之內壁溫度在30 °C以下，而進行堆積。 5 —種半導體裝置之製造方法，其特徵在於，’具備有： 在矽基板上形成閘極氧化膜之製程；在其上面形成閘電極 本紙張；適用中國國家襟準（CNS ) A搬( 210X297公羡j ： ' -22- I ~^ I - n 訂 (請先閲讀背面之注意事項再填寫本頁) 513799 經濟部智慧財產局員工消費合作社印製 Α8 Β8 C8 D8 六、申請專利範圍 膜之製程；堆積氮化矽膜以形成側壁膜之製程；以及，餓 刻上述側壁膜，藉此使上述側壁膜殘留在上述閘電極膜之 側面之製程，上述側壁膜之氮化矽膜係使用CVD裝置，使 上述CVD裝置之處理室之內壁溫度在30。(：以下，而進行 堆積。 6 —種半導體裝置之製造方法，其特徵在於，具備有： 在矽基板上形成閘極氧化膜之製程；在其上面形成閘電極 膜之製程；形成側壁膜之製程；蝕刻上述側壁膜，藉此使 上述側壁膜殘留在上述閘電極膜之側面之製程；以及，以 內含上述閘電極膜及上述側壁膜狀堆積自對準接觸用之氮 化矽膜之製程，上述側壁膜之氮化矽膜及上述自對準接觸 用之氮化矽膜，係使用CVD裝置，使上述CVD裝置之處理 室之內壁溫度在30 °C以下，而進行堆積。 7 —種半導體裝置，具備有，矽基板、設在其表面之閘 極氧化膜、接觸於上述閘極氧化膜狀配設之閘電極膜、設 在上述閘電極膜側面之側壁膜、以及，內含上述閘電極膜 及側壁膜狀配設之氮化矽膜，其特徵在於，上述氮化矽膜. 對120 °C之熱磷酸之鈾刻率在11 nm/min以下。 8 —種半導體裝置，至少具備有，矽基板、設在其表面 之閘極氧化膜、接觸於上述閘極氧化·膜狀配設之閘電極膜 、以及，設在上述閘電極膜側面之側壁膜，其特徵在於， 上述側壁膜含有氮化矽膜，上述氮化矽膜對120 °C之熱磷 酸之鈾刻率在11 n m / m i η以下。 9 一種半導體裝置，具備有，砂基板、設在其表面之閘 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） I - * n I I I I I I 訂— ―― I I I (請先聞讀背面之注意事項再填寫本頁) -23- 經濟部智慧財產局員工消費合作社印製 513799 A8 B8 C8 D8 々、申請專利範圍 極氧化膜、接觸於上述閘極氧化膜狀配設之閘電極膜、設 在上述閘電極膜側面，.包含氮化矽膜之側壁膜、以及，內 含上述閘電極膜及側壁膜狀配設之氮化矽膜，其特徵在於 ，上述氮化矽膜及構成側壁膜之氮化矽膜，·對1 20 °C之熱 磷酸之蝕刻率在11 nm/min以下。 1〇 —種半導體裝置之製造方法，其特徵在於，具備有 :在矽基板上形成閘極氧化膜之製程；在其上面形成閘電 極膜之製程；局部性形成閘電極之圖案之製程；形成側壁 膜之製程；鈾刻上述側壁膜，藉此使上述側壁膜殘留在上 述閘電極膜之側面之製程；以及，以內含上述閘電極膜及 上述側壁膜狀堆積自對準接觸用之氮化矽膜之製程，在堆 積上述自對準接觸用之氮化矽膜後，在上述氮化矽膜注入 離子。 1 1 一種半導體裝置之製造方法，其特徵在於，具備有 :在矽基板上形成閘極氧化膜之製程；在其上面形成閘電 丰亟膜之製程；局部性形成閘電極之圖案之製程；形成側壁 膜之製程；鈾刻上述側壁膜藉此使上述側壁膜殘留在上述 聞電極膜之側面之製程；以及，以內含上述閘電極膜及上 述側壁膜狀堆積自對準接觸用之氮化矽膜之製程，堆積上 述自對準接觸用之氮化矽膜，而在上述氮化矽膜注入離子 〇 12如申請專利範圍第項之半導體裝置之 製造方法，其中，上述離子種係S G e或此等之組合 〇 本紙張^適用中國國家標準（CNS ) ( 210X297公釐） ^ I 1„1 I n 訂 n II — (請先閱讀背面之注意事項再填寫本頁) -24- 8 88 8 ABCD 513799 六、申請專利範圍 13 —種半導體裝置，具備有，矽基板、設在其表面之 閘極氧化膜、接觸於上述閘極氧化膜狀配設之閘電極膜、 設在上述閘電極膜側面之側壁膜、以及，內含上述閘電極 膜及側壁膜狀配設之氮化矽膜，其特徵在於，上述氮化矽 膜之上面含有濃度較下面爲高之元素。 14 一種半導體積體電路裝置，其特徵在於，申請專利 範圍第12項之上述元素係S i或G e或此等之組合。 經濟部智慧財產局員工消費合作社印製 本紙張尺度逋用中國國家揉準（CNS ) A4規格（210X297公釐） -25-Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513799 A8 B8 C8 D8 VI. Patent application scope 1 A semiconductor device with a silicon substrate, a gate oxide film provided on its surface, and a gate oxide film contacting the gate oxide film The gate electrode film, a side wall film provided on the side surface of the gate electrode film, and a silicon nitride film including the gate electrode film and the side wall film-shaped arrangement are characterized in that the silicon nitride film is at room temperature. With traction stress below 850 Mpa. 2-A semiconductor device comprising a silicon substrate, a gate oxide film provided on a surface thereof, a gate electrode film disposed in contact with the gate oxide film, and a side wall film provided on a side surface of the gate electrode film, It is characterized in that the side wall film has a traction stress of 850 Mpa or less at room temperature. A semiconductor device comprising a silicon substrate, a gate oxide film provided on the surface thereof, a gate electrode film disposed in contact with the gate oxide film, and a side surface of the gate electrode film, including a silicon nitride film The side wall film and the silicon nitride film containing the above-mentioned gate electrode film and the side wall film configuration are characterized in that the silicon nitride film and the side wall film have a traction stress of 850 Mpa or less at room temperature. 4 A method for manufacturing a semiconductor device, comprising: a process of forming a gate oxide film on a silicon substrate; forming a gate electrode thereon; a process of forming a film; a process of forming a pattern of a gate electrode; A process for forming the sidewall film on the side of the film; and a process for depositing a silicon nitride film in the form of the gate electrode film and the sidewall film; the silicon nitride film uses a CVD device to make the processing chamber of the CVD device The inner wall temperature is below 30 ° C, and the accumulation is performed. 5 — A method for manufacturing a semiconductor device, characterized in that: 'It has: a process for forming a gate oxide film on a silicon substrate; a gate electrode paper on which it is formed; applicable to China National Standards (CNS) A move (210X297) Public envy j: '-22- I ~ ^ I-n (Please read the notes on the back before filling this page) 513799 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α8 Β8 C8 D8 A process of depositing a silicon nitride film to form a sidewall film; and a process of engraving the sidewall film to leave the sidewall film on the side of the gate electrode film; the silicon nitride film of the sidewall film uses CVD The device allows the temperature of the inner wall of the processing chamber of the CVD device to be 30. (: The following is performed. 6-A method for manufacturing a semiconductor device, comprising: forming a gate oxide film on a silicon substrate; A process of forming a gate electrode film thereon; a process of forming a side wall film; a process of etching the side wall film so that the side wall film remains on a side surface of the gate electrode film; And, a process including the gate electrode film and the side wall film-like silicon nitride film for self-aligned contact, the silicon nitride film for the side wall film, and the silicon nitride film for self-aligned contact, A CVD device is used to stack the inner wall temperature of the processing chamber of the CVD device below 30 ° C. 7 —Semiconductor device including a silicon substrate, a gate oxide film provided on the surface, and contacting the above A gate electrode film arranged in a gate oxide film form, a side wall film provided on a side surface of the gate electrode film, and a silicon nitride film containing the gate electrode film and a side wall film form, wherein the nitride Silicon film. The uranium etch rate for hot phosphoric acid at 120 ° C is below 11 nm / min. 8—Semiconductor devices, at least, a silicon substrate, a gate oxide film provided on the surface, and contact with the gate oxide A gate electrode film disposed in a film form, and a side wall film provided on a side surface of the gate electrode film, characterized in that the side wall film contains a silicon nitride film, and the silicon nitride film is uranium phosphoric acid at 120 ° C The etch rate is below 11 nm / mi η. 9 types Semiconductor device, equipped with sand substrate and sluices on the surface. The paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 mm). I-* n IIIIII Order — Ⅲ (Please read the note on the back first Please fill in this page for further details) -23- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 513799 A8 B8 C8 D8 The side surface of the gate electrode film includes a side wall film including a silicon nitride film and a silicon nitride film including the gate electrode film and the side wall film, and is characterized in that the silicon nitride film and the side film constitute a side wall film. Silicon nitride film, · The etching rate of hot phosphoric acid at 120 ° C is below 11 nm / min. 10—A method for manufacturing a semiconductor device, comprising: a process of forming a gate oxide film on a silicon substrate; a process of forming a gate electrode film thereon; a process of locally forming a pattern of a gate electrode; forming Manufacturing process of side wall film; process of engraving the side wall film to leave the side wall film on the side surface of the gate electrode film; and containing the gate electrode film and the side wall film-like deposit nitrogen for self-aligned contact In the process of forming a silicon film, after the silicon nitride film for self-aligned contact is deposited, ions are implanted into the silicon nitride film. 1 1 A method for manufacturing a semiconductor device, comprising: a process of forming a gate oxide film on a silicon substrate; a process of forming a gate electrode film on the silicon substrate; and a process of locally forming a pattern of a gate electrode; A process of forming a side wall film; a process of engraving the side wall film so that the side wall film remains on the side of the electrode film; and containing the gate electrode film and the side wall film-like nitrogen for self-aligned contact In the process of forming a silicon film, the above-mentioned silicon nitride film for self-aligned contact is deposited, and ions are implanted into the silicon nitride film, such as the method of manufacturing a semiconductor device according to the scope of the patent application, wherein the above-mentioned ion species is SG. e or a combination of them 〇 This paper ^ Applies to Chinese National Standards (CNS) (210X297 mm) ^ I 1 „1 I n Order n II — (Please read the precautions on the back before filling this page) -24- 8 88 8 ABCD 513799 6. Application patent scope 13 — A semiconductor device including a silicon substrate, a gate oxide film provided on the surface thereof, a gate electrode film arranged in contact with the gate oxide film, The side wall film provided on the side surface of the gate electrode film and the silicon nitride film containing the gate electrode film and the side wall film are characterized in that the upper surface of the silicon nitride film contains an element having a higher concentration than the lower surface. 14 A semiconductor integrated circuit device, characterized in that the above-mentioned elements in the scope of application for patent No. 12 are Si or Ge or a combination thereof. The paper is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and used in China. National Standard (CNS) A4 (210X297 mm) -25-
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