JP4441109B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4441109B2
JP4441109B2 JP2000379786A JP2000379786A JP4441109B2 JP 4441109 B2 JP4441109 B2 JP 4441109B2 JP 2000379786 A JP2000379786 A JP 2000379786A JP 2000379786 A JP2000379786 A JP 2000379786A JP 4441109 B2 JP4441109 B2 JP 4441109B2
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film
forming
silicon nitride
gate electrode
nitride film
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JP2002176174A (en
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英紀 佐藤
裕之 太田
敏夫 安藤
昭博 清水
幸博 熊谷
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株式会社ルネサステクノロジ
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly to a semiconductor device having a P-channel field effect transistor.
[0002]
[Prior art]
In recent manufacturing processes of miniaturized semiconductor integrated circuit devices, the difference in etching rate between a silicon oxide film and a silicon nitride film is used to make a gate electrode of a MISFET (Metal Insulator semiconductor Field Effect Transistor). A technique for forming contact holes in a self-aligned manner has been used. The formation of such a self-aligned contact (SAC) is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-17147. The silicon nitride film used in the self-aligned contact forming process is generally formed by a thermal CVD method using monosilane (SiH4) and ammonia (NH3) as a gas source. As this thermal CVD apparatus, a hot wall type batch type thermal CVD apparatus is used which collectively processes a plurality of (for example, about 100) wafers.
[0003]
[Problems to be solved by the invention]
As described above, a hot wall type batch type thermal CVD apparatus has been conventionally used to realize self-alignment contact. However, problems have arisen as the degree of integration increases, The introduction of a cold-wall type single wafer thermal CVD apparatus is under consideration. The background is described below.
[0004]
Recently, in order to prevent the threshold voltage of the MISFET (transistor) from being lowered due to miniaturization, the gate electrode of the n-channel MISFET is made of n-type polycrystalline silicon, and the gate electrode of the p-channel MISFET is p-type. A so-called dual gate CMOS structure, which is made of polycrystalline silicon and both are surface channel types, has come to be adopted.
[0005]
In this structure, when high-temperature heat treatment is applied in the process after the formation of the gate electrode, p-type or n-type impurities contained in the polycrystalline silicon as the gate electrode diffuse into the silicon substrate through the gate oxide film, and the MISFET The threshold voltage is easily changed. Therefore, if the temperature condition of the heat treatment process varies, the threshold voltage fluctuates greatly, resulting in a large yield reduction of the semiconductor device. That is, even when depositing a silicon nitride film for self-aligned contact or the like in the process after forming the gate electrode, the film forming temperature is high, so it is necessary to control the film forming temperature condition particularly precisely. It is difficult to control precise temperature conditions with a thermal CVD system.
[0006]
Therefore, a single wafer thermal CVD apparatus that processes wafers one by one in one chamber is easier to set precise temperature conditions than the batch thermal CVD apparatus described above, and the film thickness within the wafer surface. Since the uniformity is also good, application to the formation of a silicon nitride film for self-aligned contact is being studied. In particular, a cold-wall type single-wafer thermal CVD apparatus that forms a film with the inner wall temperature of the chamber lower than the wafer temperature has many advantages because it can compensate for a decrease in throughput that is a problem with the single-wafer apparatus. This is considered to be the mainstream of silicon nitride film forming devices for align and contact.
[0007]
However, as a result of studying the introduction of a cold wall type single-wafer thermal CVD apparatus for forming a silicon nitride film for self-aligned contact in a highly integrated semiconductor device, the present inventors have the following problems. I found
[0008]
Conventionally, a high-integrated semiconductor device, in which a silicon nitride film for self-aligned contact has been formed by a hot wall type batch type thermal CVD apparatus, was tested using a cold wall type single wafer type thermal CVD apparatus. When a silicon nitride film for align contact was formed, it was observed that the source / drain current of the p-channel type MISFET was significantly reduced. It is necessary to prevent the source / drain current from decreasing in order to reduce the operating speed of the semiconductor device. In particular, the p-channel type MISFET is a serious problem because the source / drain current is smaller than that of the n-channel type MISFET.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed and high-reliability semiconductor device that prevents fluctuations in the threshold voltage of a MISFET and prevents the source / drain current of a p-channel MISFET from decreasing.
[0010]
[Means for Solving the Problems]
To achieve the above object, the present invention is provided on a silicon substrate, a gate oxide film provided on the surface thereof, a gate electrode film provided in contact with the gate oxide film, and a side surface of the gate electrode film. In a semiconductor device having a sidewall film, and a silicon nitride film provided so as to enclose the gate electrode film and the sidewall film, the silicon nitride film has a tensile stress of 850 MPa or less at room temperature. To do. Alternatively, the sidewall film has a tensile stress of 850 MPa or less at room temperature.
[0011]
Alternatively, the present invention includes a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of forming a pattern of a gate electrode, and the side on the side surface of the gate electrode film. A step of forming a wall film, and a step of depositing a silicon nitride film so as to include the gate electrode film and the sidewall film, and the silicon nitride film is formed using a CVD apparatus, and the chamber of the CVD apparatus is formed. The inner wall temperature is 30 ° C. or lower for deposition.
[0012]
Specifically, for example, the gate oxide film can be formed by thermal oxidation or CVD. Further, the gate electrode film can be formed by sputtering or CVD. Further, a pattern of the gate electrode is locally formed by photolithography. A sidewall film is formed by sputtering or CVD. Further, the sidewall film is left only on the side surface of the gate electrode film by etching the sidewall film. Then, a silicon nitride film is deposited so as to enclose the gate electrode film and the sidewall film. For example, a cold wall type single wafer thermal CVD apparatus is used for the silicon nitride film deposition.
Alternatively, the silicon nitride film of the sidewall film is deposited by using a CVD apparatus so that the inner wall temperature of the chamber of the CVD apparatus is 30 ° C. or lower.
[0013]
Alternatively, the present invention provides a silicon substrate and a gate oxide film provided on the surface thereof, a gate electrode film provided in contact with the gate oxide film, and a sidewall film provided on a side surface of the gate electrode film, and In a semiconductor device having a silicon nitride film provided so as to include the gate electrode film and the sidewall film, the etching rate of the silicon nitride film with respect to 120 ° C. hot phosphoric acid is 11 nm / min or less. To do.
[0014]
Alternatively, the sidewall film includes a silicon nitride film, and the etching rate of the silicon nitride film with respect to 120 ° C. hot phosphoric acid is 11 nm / min or less.
[0015]
Alternatively, according to the present invention, a step of forming a gate oxide film on a silicon substrate, a step of forming a gate electrode film thereon, a step of locally forming a pattern of the gate electrode, and a sidewall film are formed. A step of etching the sidewall film to leave the sidewall film on a side surface of the gate electrode film; and a self-align contact for including the gate electrode film and the sidewall film. Depositing a silicon nitride film, and depositing the silicon nitride film for self-alignment contact by a CVD method, and then ion-implanting the silicon nitride film. The ion species is Si or Ge or a combination thereof.
[0016]
Further, the present invention is characterized in that the upper surface of the silicon nitride film contains an element having a higher concentration than the lower surface. The element is Si, Ge, or a combination thereof.
[0017]
As a result of experiments by the inventors, it has been clarified that the phenomenon of decreasing the source / drain current becomes remarkable when the semiconductor device is miniaturized and the minimum line width is 0.25 microns or less.
[0018]
Therefore, according to the present invention, even when the integration of the semiconductor device is advanced, the threshold voltage of the MISFET is prevented from changing and the source / drain current of the p-channel type MISFET is prevented from being lowered and changed. A highly reliable semiconductor device can be provided.
[0019]
Further, the fluctuation of the threshold voltage of MISFET and the decrease of the source / drain current are manifested as a decrease in yield at the stage of mass production of semiconductor devices.
[0020]
Therefore, according to the present invention, it is possible to provide a semiconductor device with good yield and excellent manufacturing cost.
[0021]
As described above, for the purpose of suppressing fluctuations in the threshold voltage of the miniaturized MISFET, a silicon nitride film for self-aligned contact is experimentally tested using a cold wall type single wafer thermal CVD apparatus. When the formed semiconductor device was produced, it was observed that the source / drain current of the p-channel type MISFET was significantly reduced or a transistor with a significantly different source / drain current in the wafer surface was produced.
[0022]
The inventors conducted stress loading experiments, stress analysis, and the like in order to investigate the cause. As a result, (1) when the tensile stress of the silicon nitride film for self-alignment contact increases, the compressive stress in the silicon substrate near the gate electrode decreases, thereby reducing the source / drain current of the p-type transistor. (2) As miniaturization of highly-integrated semiconductor devices progresses and the line width falls below the minimum line width of 0.25 microns, the stress dependency of the source / drain current rises rapidly, and the problem has rapidly become apparent with miniaturization. It became clear that.
[0023]
As an example, FIG. 2 shows the experimental results of the stress dependence of the source / drain current of a p-channel MISFET having a minimum line width of 0.14 microns. In this experiment, a four-point bending test was performed on a silicon substrate on which a semiconductor device was formed, and the characteristics of the transistor were measured while applying a known stress to the surface of the silicon substrate as a device formation region. The direction of stress is uniaxial stress in the channel plane parallel to the source / drain current flowing through the channel of the field effect transistor (stress parallel to the channel) and uniaxial stress in the channel plane perpendicular to the source / drain current. (Stress perpendicular to the channel), and the sign of the stress indicates a positive tensile stress and a negative stress indicates a compressive stress. In the case of a p-channel field effect transistor, when a tensile stress is applied, the source / drain current increases (about 4% / 100 MPa) in the direction perpendicular to the channel, but in the direction parallel to the channel. , It became clear that the source-drain current decreased (about 7% / 100MPa). Also, from this result, in the case of the biaxial stress in the channel plane, in the p-channel field effect transistor, when the biaxial stress with the same absolute value is applied, the tensile stress of the silicon substrate under the gate electrode increases. Alternatively, the source / drain current is expected to decrease as the compressive stress decreases.
[0024]
FIG. 3 shows changes in the stress dependence of the source / drain current when the gate width is changed. When the gate width, that is, the minimum line width is large, the stress dependency is small and it is hidden by other fluctuation factors such as process variations, but when the minimum line width is less than 0.25 microns, the stress dependency increases rapidly. Become. That is, this problem becomes a problem in the manufacture of semiconductor devices for the first time as a result of the progress of higher integration of semiconductor devices.
[0025]
Therefore, considering the above experimental results, in order to prevent the source / drain current from decreasing even if the semiconductor device is miniaturized to a minimum line width of 0.25 microns or less, the compressive stress in the silicon substrate near the gate electrode is reduced. It can be seen that it should be increased as much as possible. The inventors have realized that in order to realize this, the film stress of the silicon nitride film for self-aligned contact may be controlled.
[0026]
Therefore, in order to clarify the film stress of the silicon nitride film to increase the compressive stress in the silicon substrate in the vicinity of the gate electrode, a study was conducted by stress analysis using the finite element method. FIG. 4 shows the relationship between the stress in the silicon substrate near the gate that affects the change in the source / drain current and the stress in the silicon nitride film for self-alignment contact. From this relationship, it has been clarified that the compressive stress in the silicon substrate near the gate can be increased as the tensile stress of the silicon nitride film is smaller.
[0027]
As described above, the inventors can prevent a decrease in source / drain current by forming a silicon nitride film for self-aligned contact so that the tensile stress is reduced at room temperature. I was able to find it. Therefore, it is only necessary to realize this by using a cold wall type single wafer thermal CVD apparatus.
[0028]
Therefore, when the relationship between the film formation conditions of a cold-wall type single-wafer thermal CVD apparatus and the film stress at room temperature of the silicon nitride film to be formed was examined, a tensile film was found within a certain range of film formation conditions. I realized I could reduce the stress. FIG. 5 shows the relationship between the chamber temperature and film stress of a cold-wall type single wafer thermal CVD apparatus. When the temperature of the chamber of the cold wall type single wafer thermal CVD apparatus becomes 30 ° C. or higher, the film stress of the silicon nitride film increases remarkably. In other words, by setting the chamber temperature of the cold wall type single-wafer thermal CVD apparatus to 30 ° C. or lower, the tensile stress of the silicon nitride film can be kept low, thereby increasing the compressive stress in the silicon substrate near the gate. Therefore, it is possible to prevent the source / drain current of the p-channel type MISFET from greatly decreasing.
[0029]
FIG. 6 shows the relationship between the chamber temperature and the variation width of the film stress in the cold wall type single wafer thermal CVD apparatus. The variation in film stress shows a similar relationship, and it can be seen that when the temperature of the chamber of the cold wall type single wafer thermal CVD apparatus becomes 30 ° C. or less, the variation of the film stress in the wafer surface decreases rapidly.
[0030]
As described above, the silicon nitride film is formed by forming a silicon nitride film for self-alignment contact using a cold wall type single wafer thermal CVD apparatus so that the temperature of the chamber of the CVD apparatus is 30 ° C. or lower. The tensile stress of can be reduced. As a result, the compressive stress in the silicon substrate in the vicinity of the gate electrode can be increased, so that a decrease in the source / drain current of the p-channel type MISFET can be prevented. In addition, since the film stress of the silicon nitride film for self-align contact in the wafer does not vary, the variation in compressive stress in the silicon substrate near the gate electrode can be reduced. As a result, variations in the wafer surface of the source / drain current can be suppressed, and the reliability and yield of the semiconductor device can be improved.
[0031]
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the form of the 1st example of the present invention is described in detail based on a drawing. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0033]
1 is a schematic cross-sectional view of the semiconductor device of this embodiment, FIG. 2 is the stress dependence of the source / drain current of the p-channel field effect transistor, and FIG. 3 is the source / drain current with respect to the stress due to device miniaturization. Fig. 4 shows the results of a stress analysis of the influence of the intrinsic stress of the SiN film containing the gate electrode from the top surface on the channel partial stress (stress in the channel plane parallel to the source / drain current). FIG. 6 shows the relationship between the inner wall temperature of the chamber and the film stress, FIG. 6 shows the relationship between the inner wall temperature of the chamber and the variation of the film stress in the wafer surface, FIG. 7 is a conceptual diagram of a cold wall type single wafer thermal CVD apparatus, and FIG. Etching rate dependency of SiN film stress, FIGS. 9 to 11 are explanatory diagrams of the embodiment of the present invention.
[0034]
As shown in FIG. 1, the semiconductor device of this example is an n-channel field effect transistor formed on the main surface of a silicon substrate 1. Ten And p-channel field effect transistor 30 Consists of.
[0035]
Of these, the n-channel field effect transistor is composed of an n-type source / drain (12, 13) formed in the p-type well 11, a gate insulating film 14, a gate electrode 15, and a side wall 16. Silicides 17 and 18 are formed on the upper surface and the upper surfaces of the source / drain (12, 13). Further, a silicon nitride film 19 for self-align contact, a contact hole, and a wiring are formed thereabove.
[0036]
Similarly, the P-channel field effect transistor, which is the focus of the present invention, also includes p-type source / drain (32, 33) formed in the n-type well 31, a gate insulating film 34, a gate electrode 35, and a sidewall. 36. Silicides 37 and 38 are formed on the upper surface of the gate electrode 35 and the upper surfaces of the source / drain (32, 33). Further, a silicon nitride film 39 for self-align contact, a contact hole, a wiring, and an interlayer insulating film are formed thereabove. These transistors have a silicon oxide film (SiO 2 ) And silicon nitride (SiN), the element isolation film 2 insulates other transistors.
[0037]
As a material of the gate oxide films 14 and 34, for example, a silicon oxide film (SiO 2 ), Silicon nitride film (SiN), titanium oxide (TiO 2 ), Zirconium oxide (ZrO) 2 ), Hafnium oxide (HfO) 2 ), Tantalum pentoxide (Ta 2 O Five ) Or a laminated structure thereof is desirable. The material of the gate electrodes 15 and 35 is, for example, a polycrystalline silicon film or a metal film such as tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), or the like. A metal silicide or a laminated structure thereof is desirable. The sidewalls 16 and 36 are made of silicon nitride (SiN) or silicon oxide (SiO2). 2 ), A polycrystalline silicon film is desirable.
[0038]
The silicon nitride film 39 for self-alignment contact is used for forming contact holes in a self-aligned manner, and the thickness of the silicon nitride film 39 is preferably in the range of 10 nm to 200 nm. The silicon nitride film 39 is formed by a cold wall type single wafer thermal CVD apparatus.
[0039]
FIG. 7 is a conceptual diagram of a cold wall type single wafer thermal CVD apparatus 100 used for forming the silicon nitride film 39 for self-align contact. A stage 102 on which the silicon substrate 1 is placed is provided at the center of the chamber 101 of the cold wall type single wafer thermal CVD apparatus 100. Inside the stage 102, a heater 104 for heating the silicon substrate 1 is provided. Above the stage 102, a shower head 103 for supplying a source gas composed of monosilane (SiH4) and ammonia (NH3) to the surface of the silicon substrate 1 together with a carrier gas such as nitrogen (N2) is provided. In addition, a temperature control mechanism 105 that sets the inner wall of the chamber 101 at a lower temperature than the stage 102 and the silicon substrate 1 is provided outside the chamber 101. The temperature control mechanism 105 is provided with a temperature indicator 106. The temperature adjustment mechanism 105 can include, for example, a detection unit that detects a wall surface temperature using a temperature sensor and the like, and a control unit that controls the wall surface temperature to a predetermined temperature based on a signal from the detection unit.
[0040]
Since the cold-wall type single wafer thermal CVD apparatus 100 processes the silicon substrates 1 one by one on the stage 102, it is possible to realize a more precise temperature condition than the conventional batch thermal CVD apparatus. Therefore, since the temperature control of the silicon substrate 1 can be accurately performed, the diffusion of impurities into the Si substrate can be controlled, and fluctuations and variations in threshold voltage can be suppressed even when the transistor is miniaturized. . In addition, there is an advantage that the film thickness uniformity in the wafer surface is good as compared with the conventional batch type thermal CVD apparatus.
[0041]
In particular, in the cold wall type single wafer thermal CVD apparatus 100 in which the inner wall temperature of the chamber 101 is controlled by the temperature control mechanism 105 to form a film at a temperature lower than that of the stage 102 or the silicon substrate 1, most of the source gas is silicon. A film is formed by reacting on the surface of the wafer constituted by the substrate 1 and the like, and the film is hardly deposited on the inner wall of the chamber 101 having a low temperature. In contrast, in a hot wall type thermal CVD apparatus that forms a film by uniformly heating the entire inner wall of the chamber 101, a film is easily deposited on the inner wall of the chamber 101, and the film is periodically removed. The throughput is reduced due to the necessity.
[0042]
When using the cold wall type single-wafer thermal CVD apparatus 100, the silicon nitride film 39 is formed under the conditions that the temperature of the silicon substrate 1 is between 700 ° C. and 800 ° C., and the gas pressure is 200 Torr. From 350Torr. It is also desirable to use silane gas and ammonia gas as gas sources so that the flow rate ratio of ammonia gas to silane gas is 14 times or more. As a specific example, the monosilane flow rate was 70 sccm, the ammonia flow rate was 1000 sccm, the nitrogen flow rate was 7000 sccm, and the gas pressure was 350 Torr. The temperature of the wall surface of the chamber 101 was kept at 30 ° C. or lower. As the silane-based gas, monosilane is used in this embodiment, but disilane, dichlorosilane, and tetraethoxysilane can also be used. Further, an organic material containing a cyano group or an amino group can be used instead of ammonia.
[0043]
What is desired for the CVD apparatus is that it has a wall temperature control mechanism or a temperature display function associated with the CVD apparatus. In order to keep the temperature of the wall surface of the chamber 101 at 30 ° C. or lower, cooling with water is desirable, and further a water cooling system using a chiller unit may be provided.
[0044]
As a result, the film stress at room temperature of the silicon nitride film 39 for self-alignment contact can be reduced to 850 MPa or less, and the stress of the silicon substrate 31 near the gate electrode 35 is reduced by the action of the silicon nitride film. More compressive stress can be achieved. Here, it is described as “to be more compressive stress side”, which means that if the stress of the silicon substrate 31 in the vicinity of the gate electrode 35 is conventionally a tensile stress, it becomes a lower tensile stress, When the stress of the silicon substrate 31 in the vicinity of the gate electrode 35 is the conventional compressive stress, it means that the stress is higher. In this way, by reducing the stress of the silicon substrate 31 in the vicinity of the gate electrode 35 to the compressive stress side, it is possible to prevent a decrease in the source / drain current of the p-channel transistor.
[0045]
The silicon nitride film 39 is formed using a chamber of a cold-wall type single wafer thermal CVD apparatus, and when the temperature of the wall surface of the chamber 101 is 30 ° C. or less, the stress variation in the wafer surface is changed. Therefore, variations in source / drain currents of the p-channel transistor in the wafer surface can be prevented. As a result, the reliability of the semiconductor device is improved and the yield can be improved.
[0046]
From the viewpoint of stress, it is desirable that the temperature of the inner wall of the chamber 101 is 30 ° C. or lower. However, in this case, the etching rate increases, and therefore, the self-aligned contact with the gate electrode portion is formed. There is a drawback that the processing becomes difficult because the difference in etch rate becomes small. Considering this, as a second best measure, the inner wall temperature of the chamber 101 may be set to 35 ° C. or lower.
[0047]
Since the lower limit temperature differs depending on the cooling means, it will not be described in detail. For example, when a coolant such as water is used, the temperature is higher than 0 ° C. at which the solidification occurs. However, when the antifreeze component is contained in the water, the temperature is higher than the solidification temperature.
[0048]
It is known that there is a clear relationship as shown in FIG. 8 between the film stress of the silicon nitride film at room temperature and the etching rate of the silicon nitride film formed under the above conditions by hot phosphoric acid. From this, it can be seen that when the film stress of the silicon nitride film formed by the cold wall type single wafer thermal CVD apparatus is 850 MPa or less, the etching rate by hot phosphoric acid at 120 ° C. is 11 nm / min or more.
[0049]
FIG. 9 shows a second embodiment of the present invention. In this embodiment, the sidewall 36 is formed by a cold-wall type single-wafer thermal CVD apparatus, and the temperature of the chamber of the CVD apparatus is set to 30 ° C. or less. As a result, the film stress at room temperature of the silicon nitride film constituting the sidewall 36 can be reduced to 850 MPa or less, and by the action of the silicon nitride film, the stress of the silicon substrate 31 near the gate electrode 35 is reduced, More compressive stress can be achieved. This can prevent a decrease in source / drain current of the p-channel transistor. The sidewall 36 may be formed of a silicon nitride film and a silicon oxide film. In this case, the silicon nitride portion may be formed under the above conditions. That is, the silicon nitride film of the sidewall 36 is manufactured under the film forming condition that is formed by a cold wall type single wafer thermal CVD apparatus and the temperature of the chamber of the CVD apparatus is 30 ° C. or less. As shown in FIG. 12, even if there is no silicon nitride film for self-alignment contact, the same effect can be obtained by applying the present invention.
[0050]
This embodiment has the following features in addition to the advantages listed in the first embodiment of the present invention. That is, if the silicon nitride film of the sidewall 36 is manufactured under a film forming condition that is formed by a cold wall type single-wafer thermal CVD apparatus and the chamber temperature of the CVD apparatus is 30 ° C. or less, the nitridation is performed. Since hydrogen atoms contained in the silicon film can be reduced, the electrical characteristics of the transistor can be improved.
[0051]
FIG. 10 shows a third embodiment of the present invention. When a silicon nitride film 39 for self-alignment contact is manufactured under the above conditions in addition to the sidewall 36, a silicon substrate under the gate electrode is further formed. The stress can be further pulled, and the effect is further increased. In this embodiment, both the sidewall 36 and the silicon nitride film 19 for self-alignment contact are made of the same material. Therefore, the material interface between the sidewall 16 and the silicon nitride film 39 for self-alignment contact is used. In addition to the advantages of the second embodiment, there is an advantage that the risk of film peeling at the interface is small because the stress concentration is small.
[0052]
FIG. 11 shows a fourth embodiment of the present invention. The sidewall 36 is composed of two or more films, and one or more of these films are formed as silicon nitride films under the above conditions. May be. In this embodiment, the side wall 36 is constituted by a combination of a silicon oxide film and a silicon nitride film, and the silicon oxide film is in contact with the silicon substrate. In this embodiment, since the silicon nitride film is not in direct contact with the silicon substrate, there is an additional advantage that impurities such as nitrogen in the silicon nitride are difficult to diffuse into the silicon substrate. Similarly, since a silicon oxide film exists between the silicon nitride film and the silicon substrate, the silicon oxide film relaxes the stress of the silicon nitride film, thereby preventing the occurrence of dislocations in the silicon substrate. There is an additional advantage of doing so.
[0053]
Further, a fifth embodiment of the present invention will be described with reference to FIGS. In this embodiment, a silicon nitride film 39 for self-alignment contact is formed and then ion implantation is performed on the entire upper surface of the silicon nitride film. That is, the silicon nitride film 39 is formed, and then ion implantation is performed on the entire wafer surface. Thereafter, the silicon nitride film is locally etched, and processing for forming vias is performed. It should be noted that the same effect can be obtained by changing the order and performing ion implantation after processing for via formation, but in this case, ions are also implanted into the silicon substrate in the via formation hole, This is not desirable because it tends to cause dislocations.
[0054]
According to this embodiment, since ions are implanted into the silicon nitride film, the film stress of the silicon nitride film 39 can be made more compressive, that is, the tensile stress can be reduced. The stress of the substrate 31 can be made closer to the compressive stress side. As a result, a decrease in source / drain current of the p-channel transistor can be prevented. In addition, since ion implantation is performed on the entire upper surface of the silicon nitride film 39, there is an advantage that a mask for ion implantation is unnecessary and the number of steps or masks can be reduced. In the case of the configuration as shown in FIG. 12, the sidewall portion may be formed as described above.
[0055]
Although this embodiment may be combined with the first, second, and third embodiments of the present invention, it is effective when used alone, in which case other advantages are also generated. For example, when a silicon nitride film 39 for self-aligned contact is formed under the conditions of a monosilane flow rate of 10 sccm, an ammonia flow rate of 5000 sccm, and a nitrogen flow rate of 5000 sccm and a gas pressure of 350 Torr, the film stress of the silicon nitride film 39 is 1 GPa or more of tensile On the other hand, the impurities in the silicon nitride film 39 are reduced, and there is an advantage that the influence on the silicon substrate due to the diffusion of the impurities can be minimized. In the prior art, if the impurity in the silicon nitride film is reduced, one item of electrical characteristics of the device is improved, but the tensile stress of the silicon nitride film is increased, so that the source / drain of the p-channel transistor is increased. The adverse effect of decreasing the current occurs, and this phenomenon has become prominent when the minimum line width is 0.25 microns or less. If this embodiment is applied, it is possible to reduce the tensile film stress of the silicon nitride film 39 or increase the compressive film stress under the film forming conditions in which impurities are reduced. Even in this case, it is possible to prevent the source / drain current of the p-channel transistor from being lowered, and the influence of impurities can be minimized.
As the ion species used in the ion implantation process, those having an ion radius larger than Si are preferable because stress changes are large, and Ge and Si that do not change the electrical characteristics of the device are more preferable. In addition, if the ion species are often used in the semiconductor industry such as Ga, As, In, Sb, Tl, Bi, etc., the existing equipment can be used, so the investment in the ion implanter or its peripheral equipment can be minimized. Occurs. The acceleration voltage is preferably about 10 keV to 200 KeV depending on the thickness of the silicon nitride film 39. When the film thickness is small, the acceleration voltage tends to be low. The dose is 10 12 ~Ten 16 Dose / cm 2 A range of is desirable.
[0056]
When this embodiment is performed, these ion species are detected in the silicon nitride film, resulting in a concentration distribution in the film thickness direction peculiar to the ion implantation process, and the upper surface of the film has a higher concentration than the lower surface.
[0057]
【The invention's effect】
According to the present invention, it is possible to provide a high-speed and high-reliability semiconductor device that prevents fluctuations in the threshold voltage of the MISFET and prevents the source / drain current of the p-channel type MISFET from decreasing.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 shows an experimental result of stress dependence of a source / drain current of a p-channel field effect transistor.
FIG. 3 is a graph showing the relationship between the minimum line width of a semiconductor device and the stress dependence of the source / drain current of a p-channel field effect transistor.
FIG. 4 is a diagram showing the result of a stress analysis for the relationship between the film stress of a silicon nitride film for self-aligned contact and the stress in the silicon substrate near the gate electrode.
FIG. 5 shows the experimental results showing the relationship between the inner wall temperature of the chamber of the CVD apparatus and the film stress of the silicon nitride film formed by the apparatus when formed by a cold wall type single wafer thermal CVD apparatus. Overview diagram.
FIG. 6 shows the relationship between the inner wall temperature of the chamber of the CVD apparatus and the variation in film stress of the silicon nitride film formed by the apparatus when formed by a cold wall type single wafer thermal CVD apparatus. The schematic diagram of an experimental result.
FIG. 7 is a conceptual diagram of a cold wall type single wafer thermal CVD apparatus 100 used for forming the silicon nitride film 19 for self-alignment contact.
FIG. 8 is a graph showing a relationship between a film stress of a silicon nitride film at room temperature and an etching rate of the silicon nitride film by hot phosphoric acid.
FIG. 9 is a schematic sectional view showing a part of a semiconductor device according to a second embodiment of the present invention.
FIG. 10 is a schematic cross-sectional view showing a part of a semiconductor device according to a third embodiment of the present invention.
FIG. 11 is a schematic sectional view showing a part of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 12 is a schematic cross-sectional view showing a part of a semiconductor device according to a second other embodiment of the present invention.
[Explanation of symbols]
1 ... silicon substrate, 2 ... element isolation film, 3 ... interlayer insulation film, 6 ... wiring, 11 ... p-type well, 31 ... n-type well, 12, 13, ... -N-type source / drain, 32, 33 ... p-type source / drain, 14, 34 ... gate insulating film, 15, 35 ... gate electrode, 16, 36 ... sidewall, 17, 18 , 37, 38 ... Silicide, 19, 39 ... Silicon nitride film for self-aligned contact
100 ... Cold wall type single wafer thermal CVD apparatus, 101 ... Chamber, 102 ... Stage, 103 ... Shower head, 104 ... Heater, 105 ... Temperature control mechanism, 106 ..Temperature display

Claims (2)

  1. Forming a gate oxide film on the silicon substrate; forming a gate electrode film thereon; forming a gate electrode pattern; and forming the sidewall film on a side surface of the gate electrode film And forming a source and a drain on the silicon substrate, thereby forming a p-channel field effect transistor;
    After forming the p-channel field effect transistor, a step of further depositing a silicon nitride film so as to include the gate electrode film and the sidewall film, and penetrating the silicon nitride film to form the source or drain In the method of manufacturing a semiconductor device, the method includes a step of forming a contact hole that reaches the thickness of the contact hole and a step of forming a wiring on the contact hole, wherein the minimum line width of the gate width of the gate electrode film is 0.25 μm or less.
    The silicon nitride film has a tensile stress of 850 MPa or less at room temperature by depositing the silicon nitride film by using a thermal CVD apparatus so that the inner wall temperature of the chamber of the thermal CVD apparatus is 30 ° C. or lower. Method.
  2. Forming a gate oxide film on the silicon substrate; forming a gate electrode film thereon; forming a sidewall film; and etching the sidewall film to form side surfaces of the gate electrode film Forming a p-channel field effect transistor by having a step of leaving the sidewall film and a step of forming a source and a drain on the silicon substrate;
    After forming the p-channel field effect transistor, a step of depositing a silicon nitride film for self-alignment contact so as to include the gate electrode film and the sidewall film; and penetrating the silicon nitride film And a step of forming a contact hole reaching the source or the drain and a step of forming a wiring over the contact hole, wherein the gate electrode film has a minimum gate width of 0.25 μm or less. In the device manufacturing method,
    It said side wall film and a silicon nitride film for the self-aligned contact, using a thermal CVD apparatus, by depositing the inner wall temperature of the chamber of the thermal CVD apparatus 30 ° C. or less, tensile follows 850MPa at room temperature A method of manufacturing a semiconductor device, characterized by having stress .
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