KR101134157B1 - Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress - Google Patents

Abstract

By providing a contact etch stop layer 116, the stress in the channel regions of the differential transistor types 100N, 100P can be effectively controlled, wherein the tensile or compressive stress portions of the contact break layer are chemically etched, plasma etched. Can be obtained by well established processes such as ion implantation, plasma treatment and the like. Thus, significant improvements in transistor 100N, 100P performance are obtained, while not significantly contributing to processor complexity.

Intrinsic stress, differential mechanical stress in the differential channel region

Description

TECHNICAL FOR CREATING DIFFERENT MECHANICAL STRESS IN DIFFERENT CHANNEL REGIONS BY FORMING AN ETCH STOP LAYER HAVING DIFFERENTLY MODIFIED INTRINSIC STRESS }

In general, the present invention relates to the formation of integrated circuits, and more particularly to the formation of field effect transistors having channel regions with a certain intrinsic stress to improve charge carrier mobility.

Fabrication of integrated circuits requires forming a large number of circuit elements on a given chip area, depending on the particular circuit layout. In general, a plurality of process techniques are currently being implemented, and for complex circuits such as microprocessors, storage chips, etc., CMOS technology is the most promising technology at present, which has excellent characteristics in terms of operating speed and / or power consumption. Because it looks. During the manufacture of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate comprising a crystalline semiconductor layer. Regardless of whether it is an N-channel transistor or a P-channel transistor, a MOS transistor is a so-called PN formed by an interface of heavily doped drain and source regions having a reversely doped channel region disposed between the drain region and the source regions. Including junctions. The conductivity of the channel region, i.e. the current driving performance of the conductive channel, is controlled by a gate electrode formed over the channel region and separated from the channel region by a thin insulating layer. The conductivity of the channel region when forming a conductive channel due to the application of an appropriate control voltage to the gate electrode depends on the concentration of impurities and the mobility of the plurality of charge carriers, and on the expansion of the predetermined channel region in the transistor width direction. The distance between the source and drain regions is also referred to as the channel length. Thus, along with the ability to quickly form a conductive channel under the insulating layer when applying a control voltage to the gate electrode, the conductivity of the channel region essentially determines the performance of the MOS transistors. Therefore, the reduction in channel length associated with the reduction in channel resistance makes the channel length a major design criterion for inspiring the speed of operation of integrated circuits.

However, the reduction in transistor dimensions involves a number of related problems that must be solved in order not to excessively offset the gains obtained by steadily reducing the channel length of MOS transistors. One major problem in this regard is the development of improved optical lithography and etching techniques for producing reliable and reproducible critical dimension circuit elements, such as the gate electrode of a transistor, for a new device generation. Moreover, very sophisticated impurity profiles in the vertical as well as the transverse directions are required in the drain and source regions to provide a low sheet and contact resistance in combination with the desired channel controllability. In addition, the vertical position of the PN junction relative to the gate insulating layer also presents an important design criterion in terms of leakage current control. So also reducing the channel length requires reducing the depth of the drain and source regions in terms of the interface formed by the gate insulating layer and the channel region, thus requiring sophisticated implantation techniques. According to another approach, epitaxially grown regions are formed with special offsets in the gate electrode, which are referred to as raised drain and source regions to provide increased conductivity of the raised drain and source regions. While at the same time a shallow PN junction is maintained with respect to the gate insulating layer.

Regardless of the technical approach used, sophisticated spacer techniques create highly complex impurity profiles, and masks that form drain and source regions in a self-aligned and metal silicide regions within the gate electrode. It is necessary to provide as. Continuous reduction in size, i.e., reducing the gate length of the transistors, to a critical dimension requires adaptation to the identified process steps and new development of process techniques, so that charge in the channel region for a given channel length It has been proposed to improve the device performance of the transistor device by increasing carrier mobility. In principle, at least two mechanisms can be used in combination or separately to increase the mobility of charge carriers in the channel region. First, the impurity concentration in the channel region can be reduced, thereby reducing scattering of charge carriers and increasing conductivity. However, significantly reducing the impurity concentration in the channel region affects the threshold voltage of the transistor device, so if other mechanisms are not developed to adjust the required threshold voltage, the reduction of impurity concentration is not a more effective approach. . Secondly, the lattice structure of the channel region can be deformed, for example by creating a tensile or compressive stress, which deforms the mobility for each of the electrons and holes. Let's do it. For example, creating a tensile stress in the channel region increases the mobility of the electrons, where an increase in mobility up to 20% can be obtained, depending on the strength of the tensile stress, and the corresponding conductivity directly increases. . On the other hand, compressive stress in the channel region can increase the mobility of the holes, where it can provide the potential for improving the performance of P-type transistors. As a result, it has been proposed to insert, for example, a silicon / germanium layer or a silicon / carbon layer in or below the channel region to create tensile or compressive stresses. Although the performance of the transistor has been significantly improved by the insertion of a tensile stress layer in or below the channel region, considerable effort is required to carry out the formation of corresponding stress layers with conventional and well established CMOS technology. For example, additional epitaxially growing techniques must be developed, and process flows must be carried out to form germanium or carbon containing stress layers at appropriate locations in or below the channel region. The complexity of the process is thus significantly increased, thus also increasing the potential for reduced production costs and yields.

Moreover, it is difficult to induce stress in a reliable and controlled manner by other devices, such as spacer devices, which makes the spacer formation process perfectly tailored to the implantation process and silicidation, especially for extremely scaled devices. Because it has to be, and therefore provides less flexibility for changes in the process that can satisfy any requirements for stress characteristics.

In view of the above situation, there is a need for an alternative technique that enables the creation of stress conditions required in transistor structures without the need for complex and expensive epitaxial growth techniques such as spacer formation or changes in critical fabrication steps.

The following presents a brief summary of the invention in which certain aspects of the invention provide a basic understanding. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

In general, the present invention provides a channel region of different transistor elements by modifying the stress characteristics of the contact etch stop layer formed after completion of the basic transistor structure for forming contact openings for gate and drain and source terminals in the interlayer dielectric material. We present a technique that enables us to create the required stress conditions within. As is well known, when reducing the feature dimensions of transistor elements, reliable and sophisticated control of the mechanical stresses induced in the transistor elements can be achieved by nucleation of defects, void formation, electrical It becomes even more important to cope with phenomena such as changes in properties, in which stresses specifically induced by deformations of electrical behavior can be used positively to improve device performance. Effective control of the mechanical stress in the channel region, ie effective stress engineering, affects the sidewall spaces and the contact etch stop layer as both sidewall spacers and the contact etch stop layer are placed directly on the transistor structure. Can be achieved by consideration. According to the present invention, effective stress engineering can be achieved by adjusting the intrinsic stress characteristics of the contact breakdown layer to provide differential stress conditions for the differential transistor device, while at the same time high in conventional and well established process techniques. Maintain compatibility.

According to one exemplary embodiment of the present invention, the method includes forming a dielectric layer over the first transistor element and the second transistor element, wherein the dielectric layer has a first predetermined intrinsic mechanical stress. Further, a mask layer is formed over the first and second transistor elements to expose a first portion of the dielectric layer formed over the first transistor element and cover the second portion of the dielectric layer formed over the second transistor element. Finally, the first intrinsic stress in the first portion is transformed into an intrinsic stress deformed by the ion bombardment of the first portion.

According to another exemplary embodiment of the invention, the method includes forming a first dielectric layer over the first transistor and the second transistor, wherein the first dielectric layer has a first predetermined intrinsic mechanical stress. Moreover, the first portion of the first dielectric layer formed over the first transistor element is selectively removed. Additionally, a second dielectric layer is formed over the first transistor element and a second portion of the first dielectric layer formed over the second transistor element, wherein the second dielectric layer is subjected to a second intrinsic stress different from the first intrinsic stress. Have Finally, the second portion of the second dielectric layer formed over the second portion of the first dielectric layer is selectively removed.

According to another exemplary embodiment of the present invention, a semiconductor device includes a first transistor element having a first channel region and a first dielectric layer surrounding the first transistor element, wherein the first dielectric layer is the first dielectric layer. Induce a first stress in the channel region. Moreover, the semiconductor device includes a second transistor element having a second channel region and a second dielectric layer, wherein the second dielectric layer surrounds the second transistor element and induces a second stress in the second channel region. Wherein the second stress is different from the first stress.

The invention can be understood with reference to the following description in conjunction with the accompanying drawings. Here, like reference numerals denote like elements.

1A-1G schematically illustrate cross-sectional views of a semiconductor device including two transistors at various stages of fabrication, wherein the intrinsic mechanical stress of the contact etch layer is modified by treatment with non-reactive ions in accordance with an embodiment of the present invention. do.

2A-2J schematically show a cross-sectional view of a semiconductor device including two different transistor elements, wherein the intrinsic stress of the contact etch stop layer is modified by treating with non-reactive ions in accordance with other embodiments of the present invention. ; And

3A-3G schematically illustrate a cross-sectional view of a semiconductor device including two different transistor types, wherein the two different transistor types selectively select their portions by dry etching techniques in accordance with other embodiments of the present invention. By removing the correspondingly designed contact etch stop layers.

The invention can be in various modifications and alternative forms, with specific embodiments of which are shown by way of example in the drawings and are described in detail herein. However, the description of specific embodiments herein is not intended to limit the invention to the particular forms disclosed, but rather, the invention is intended to cover all modifications and equivalents falling within the spirit and scope of the invention as defined by the appended claims. And the alternatives.

Exemplary embodiments of the invention are described below. In the interest of clarity, not all features of the embodiments have been described herein. Of course, in the development of any such practical embodiment, many execution characterizations must be made to achieve the developer's specific goals, such as complying with system and business-related constraints, and vary from implementation of one of these constraints to another. Will be understood. Moreover, it is to be understood that such development efforts are complex and time consuming, and can nevertheless be undertaken conventionally for those skilled in the art having the benefit of this disclosure.

The invention will now be described with reference to the accompanying drawings. Various structures, systems, and devices have been shown schematically in the drawings in order not to obscure the present invention only for purposes of explanation and details that are well known to those skilled in the art. Nevertheless, the attached drawings include describing or describing exemplary views of the invention. The words and phrases used herein should be understood and interpreted in a manner consistent with the meaning of the words and phrases used in the art. Any particular definition of a term or phrase, that is, a definition different from the usual and customary meanings understood by those skilled in the art, is not intended to be implied by the coincidental use of the term or phrase herein. If a term or phrase is intended to have a special meaning, that is, to have a meaning different from that understood by a skilled artisan, it will be clearly stated by way of definition that provides a direct and distinctly specific definition of the term or phrase.

The present invention is based on the concept that effective stress engineering in the channel region of a differential transistor can be effectively achieved by modifying the intrinsic stress of the dielectric layer in contact with the transistor structure or at least located in close proximity to the transistor structure. Deformation of the intrinsic stress of the dielectric layer can be accomplished by adjusting processor parameters and / or treating with non-reactive ions. Because the dielectric layer is located above the transistor structure, and also because it is at least partly used as a contact etch stop layer covering a large area of the transistor structure, mechanical coupling to the transistor structure does not require significant deformations during the transistor formation process and the channel region. Enable effective stress engineering within. Moreover, the present invention allows the deformation and formation of corresponding dielectric layers having different stress properties at different die locations or at different dies in the substrate. Therefore, on a local scale, the present invention enables the formation of differential stresses comprising dielectric layers in closely aligned transistor elements, such as CMOS devices that are complementary transistor pairs, and thus complex CMOS, such as CPUs, memory chips, and the like. It offers the potential to improve the overall performance of the device. Thus, for the geometry of a given transistor, i.e. for a given technology node, faster operation at the same leakage level is achieved, or leakage currents and power consumption can be reduced for a given operating speed. On a more general scale, processor non-uniformity causing variation in electrical characteristics of devices located at differential locations of the wafer or deviations in devices formed on other wafers may selectively cause stress levels to other wafers or wafer locations. It can be reduced or compensated for by fitting, where stress adaptation takes place within the transistor level, ie in the channel region included in the transistor devices, thus making stress engineering very effective.

As mentioned above, the stress induction problem relates to the further reduction in feature size, and therefore the present invention is particularly advantageous in the combination of highly refined semiconductor devices, and thus intrinsic to the performance caused by the stress induced problem. It is possible to expect lossless device miniaturization.

With reference to the drawings, more exemplary embodiments of the present invention will be described in more detail. 1A shows a cross-sectional view of a semiconductor device 150 including a first transistor element 100n and a second transistor element 100p. The transistor elements 100n and 100p may be connected to other forms of transistor elements, such as N-channel transistors and P-channel transistors, or transistors of the same or different type located at differential die locations or differential substrate locations. And in certain embodiments the transistor 100n may represent an N-channel transistor, and the second transistors 100p may represent a P-channel transistor, both of which are complementary transistors. Arranged to form a pair. Although the transistors 100n and 100p may have different dimensions, conductivity types, locations, functions, etc., the transistors shown for convenience have essentially the same configuration, and the transistors 100n and ( Corresponding elements of 100p) are denoted by the same reference numerals. Also, although the present invention is particularly advantageous for transistor devices without stress inducing components such as additional epitaxy layers within or below each channel region, the present invention may be combined with such additional stress generating techniques. It should be noted that. It should also be understood that in the following description of a more exemplary embodiment of the present invention, transistor elements are provided in the form of a silicon-on-insulator (SOI) without any raised drain and source regions. As will be apparent during the description, the present invention can also be applied to transistor devices formed on bulk semiconductor substrates, and can be readily applied to transistor designs using raised drain and source regions.

The semiconductor device 150 includes a substrate 101 on which an insulating layer, such as a buried silicon dioxide layer, a silicon nitride layer, and the like, is formed, and then a crystalline semiconductor layer 103 is formed, including many complex logic circuits. Since the integrated circuits of are based on silicon, the layer will be referred to as the "silicon layer" in the following description. However, the semiconductor layer 103 may be composed of any suitable semiconductor material, depending on design requirements. The first and second transistors 100n and 100p may be separated from each other in an isolation structure 120, for example, shallow trench isolation. The first transistor 100n may further include a gate electrode structure 105 comprising a polysilicon portion and a semiconductor portion 106 such as, for example, a metal containing portion 108 provided in the form of a metal silicide. . The gate electrode structure 105 further includes a gate insulating layer 107 that separates the gate electrode structure 105 from the channel region 104, wherein the channel region 104 defines metal silicide regions 112. The branches separate the appropriately doped source and drain regions 111 laterally. A spacer element 110 is formed proximate the sidewalls of the gate electrode structure 105 and is separated from the gate electrode structure 105 by a liner 109. In some cases, the liner 109 may be omitted.

The second transistor 100p may have a component that is essentially the same as the configuration, wherein the channel region 104 and the drain and source regions 111 may include the first and second transistors 100n and 100p. When referring to a transistor device having a differential conductivity type, it may include other impurities compared to the respective regions of the transistor 100n.

As shown in FIG. 1A, a typical process flow for forming semiconductor device 150 may include the following processes. Substrate 101, insulating layer 102 and semiconductor layer 103 may be formed by improved wafer bonding techniques when semiconductor device 150 represents an SOI device, or substrate 101 may be bulk It may be provided without an insulating layer 102, such as a semiconductor substrate, where the semiconductor substrate 103 may represent a portion of the upper layer of the substrate, or may be formed by epitaxial growth techniques. The gate insulating layer 107 may then be deposited and / or formed by oxidation in accordance with well established processor techniques, followed by deposition of a gate electrode material such as polysilicon by low pressure chemical vapor deposition (LPCVD). do. Thereafter, the gate electrode material and gate insulating layer 107 are patterned by sophisticated photolithography and etching techniques according to well established processor methods. Next, implantation cycles can be performed in combination with a fabrication process to form the spacer element 110, where a finely laterally profiled dopant concentration for the drain and source regions 111 is required. When formed, the spacer element 110 may be formed as two or more differential spacer elements using immediate implant processes. For example, extended areas of reduced penetration depth may be required. After an anneal cycle to partially heal the crystal damage caused by activation and implantation, the metal silicide regions 108 and 112 deposit a refractory metal and initiate a chemical reaction with the underlying silicon. And the spacer element 110 acts as a reaction mask to prevent or reduce the formation of a metal component between the gate electrode structure 105 and the drain and source regions 111.

1B schematically illustrates a semiconductor device 150 with a first dielectric layer 116 formed over transistor elements 100n and 100p. Typically, the transistor elements 100n and 100p are embedded in an interlayer dielectric material (not shown in FIG. 1B), wherein corresponding metallization layers are formed over the interlayer dielectric material to provide the required electrical connection with the individual circuit elements. Will establish. The interlayer dielectric material must be patterned to provide contact with the gate electrode structure 105 and the drain and source regions 111 by an anisotropic etching process. Since the anisotropic etching process must be performed at different depths, a reliable layer stop layer prevents metal from being removed from the gate electrode structure 105 when the etch front reaches the gate electrode structure 105. Is normally provided and still accesses the drain / source regions 111. Thus, in a particular embodiment, the first dielectric layer 116 is designed to act at least in part as an etch stop layer for contact etch, and thus may also be referred to as a contact etch stop layer. Often, the interlayer dielectric material is composed of silicon dioxide, and thus the first dielectric layer 116 comprises silicon nitride because silicon nitride shows good etch selectivity for well-established anisotropic processing methods for etching silicon dioxide. can do. In particular, silicon nitride can be deposited according to well established deposition methods, where the deposition parameters can be adjusted to provide some intrinsic mechanical stress, while at the same time providing the high etch selectivity required for silicon dioxide. Keep still. Silicon nitride is typically deposited by plasma enhanced chemical vapor deposition (PECVD), where parameters of the plasma atmosphere, such as, for example, the bias power supplied to the plasma atmosphere, are deposited into the silicon nitride layer as it is deposited. It can be varied to adjust the mechanical stress produced. For example, the deposition is well established based on silane (SiH ₄ ) and ammonia (NH ₃ ), nitrogen oxides (N ₂ O) or nitrogen (N ₂ ) in a deposition tool for a PECVD method for a silicon nitride layer. It can be carried out based on the processing methods. The stress in the silicon nitride layer can be determined by deposition conditions, where, for example, compressive stress in silicon nitride of about 150 MPa can be achieved with a moderately high bias power according to well established deposition methods and In contrast, in other embodiments about 0-10,000 MPa tensile stress can be achieved. In general, the stress produced in silicon nitride during the deposition is dependent on gas mixing, deposition rate, temperature and ion bombardment. According to known methods, the amount of corresponding tensile or compressive stress in the layer may be adjustable by changing any such process parameters that determine the plasma atmosphere, for example, during deposition of the layer by PECVD. In particular, the bias energy supplied to the plasma atmosphere can be varied by adjusting the degree of ion bombardment during the deposition process, thereby creating a tensile or compressive stress in the silicon nitride layer. To produce the required ion bombardment, dual frequency CVD reactors are usually used to adjust the required amount of bias power. For example, if the low frequency supply is significantly reduced or turned off, a silicon nitride layer with tensile stress is produced. In contrast, a suitable high bias power creates compressive stress in the silicon nitride layer. The corresponding deposition process can be performed with any deposition tool that allows the creation of a suitable plasma atmosphere.

For example, the first dielectric layer 116 may be deposited as a silicon nitride layer having a predetermined compressive stress. Corresponding process methods can also be readily achieved on a test substrate for depositing silicon nitride with the required dimensions of compressive or tensile stress, where one or more process parameters are changed and the stress of the silicon nitride layers Properties are measured and associated with the parameters of each process. In the description below, it is assumed that the first dielectric layer 116 includes compressive stress, whereas in other embodiments it may be formed with tensile stress.

FIG. 1C shows a semiconductor device 150 in which a resist mask 140 is formed, where the resistor mask 140 exposes the first transistor device 100n and exposes the second transistor device 100p. Cover. The resist mask 140 can also be formed according to the photolithography mask required for the formation of P-type and N-type transistors, and the formation of the resist mask 140 is easily integrated with conventional processor flows. Can be. In addition, semiconductor device 150 is treated 160 with non-reactive ions, including, for example, xenon, germanium, and the like when treatment 160 is performed as an ion implantation sequence. Due to the ion bombardment, the molecular structure of the first portion 116n of the layer 116 is modified to significantly reduce intrinsic stress within the first portion 116n of the layer 116. The process parameters of the treatment 160 may be selected depending on the layer thickness of the first dielectric layer 116 and the type of ion species used when performed as an ion implantation process. For example, a dose of about 10 ¹⁵ -10 ¹⁶ ions / cm ² can be used at an implantation energy of about 10-100 keV for a thickness of about 50-100 nm for the given ionic species. However, the values of the relevant parameters can be easily determined by simulation. In another embodiment, the treatment 160 may be performed in a plasma atmosphere based on inert gases such as argon, helium, etc. that exhibit greater penetration depth at smaller acceleration energies, thus intrinsic within the portion 116n. Represents ion energies generated in a suitable plasma atmosphere to relieve stress. Suitable plasma atmosphere may be generated in any suitable plasma etch or plasma deposition tool.

1D shows semiconductor device 150 after completion of ion bombardment with reduced stress or essentially stress free portion 116n depending on design requirements, the semiconductor device being provided over first transistor 100n. And a portion 116p that still has the compressive stress of the first deposited dielectric layer 116. In some embodiments, the reduced intrinsic stress or significantly reduced compressive stress of the first portion 116n is such that the first transistor 100n is achieved to achieve essentially symmetrical behavior of the first and second transistors 100n and 100p. May be appropriately considered to achieve the required deformation of the electrical behavior of the channel region 104 of the < RTI ID = 0.0 >), < / RTI > During use, this may continue by depositing an interlayer dielectric material, such as silicon dioxide, and forming corresponding contact openings.

FIG. 1E illustrates a semiconductor device 150 in accordance with example embodiments when a more pronounced strain of stress condition is required in the channel region 104 of the first transistor 100n. As already explained, if transistor 100n represents an N-type transistor, the tensile stress in channel region 104 may provide improved mobility of the electrons. Therefore, a second dielectric layer 117 having intrinsic stress required for the first transistor 100n can be formed over the first and second transistors 100n and 100p. For example, the dielectric layer 117 may be deposited to exhibit an intrinsic tensile stress of a predetermined size. In some embodiments, the compressive stress in the second portion 116p is modified to achieve the total stress (eg, compressive stress condition) required in the channel region 104 of the second transistor 100p. 2 may be selected to significantly overcompensate the tensile stress induced by dielectric layer 117. In another embodiment, partial compensation for the compressive stress of the second portion 116p by the tensile stress of the dielectric layer 117 may be improperly considered, and over the second transistor 100p to the dielectric layer 117. The intrinsic stress generated by this may be modified by, for example, a process similar to process 160, or in other embodiments, a portion of the layer 117 may be removed over the second transistor 100p.

1F shows a semiconductor device 150 in which a resist mask 170 is formed, which covers the first transistor element 100n while the second transistor element 100p is exposed. Furthermore, the second transistor 100p is subjected to a plasma etching process 180 to remove the exposed portion of the layer 117. In some embodiments, the dielectric layer 117 is formed when the etch front of the plasma etching process 180 reaches the second portion 116p of the layer 116 or the liner acts as an etch stop layer. It may include a thin liner (not shown) formed on the first dielectric layer 116 to provide an indication of.

1G schematically illustrates the semiconductor device 150 after removal of the exposed portion of the layer 117 and removal of the resist mask 170. Thus, the stress generated in the channel region 104 of the first transistor 100n is essentially determined by the second dielectric layer 117, while the stress in the channel region 104 of the second transistor 100p is zero. Essentially determined by two portions 116p. The type and dimension of intrinsic stress in the first dielectric layer 116 and the second dielectric layer 117 can be selected according to design requirements, and are not necessarily selected in the manner described above.

In another embodiment, the plasma etching process 180 shown in FIG. 1F is performed by the ion bombardment of FIG. 1C to reduce or relieve stress in the exposed portion of the dielectric layer 117 without removing the exposed portion of the dielectric layer 117. It can be replaced with an ion bombardment similar to 160. By appropriately selecting the injection parameters or parameters for the plasma atmosphere, the degree of stress relaxation is achieved in order to achieve the total induced stress required in the channel region 104 of the second transistor 100p. Can be controlled appropriately. In this way, essentially equivalent layer thicknesses can be obtained for the layers 116 and 117 over the first and second transistor elements 100n, 100p, and thus essentially the same etching conditions during subsequent contact opening etching. Provide them.

Moreover, in the above-described embodiment, the tensile stress in the N transistors and the compressive stress in the P transistor advantageously occur. However, other combinations of stresses can be created. In particular, two or more differential stress levels can be obtained at two or more differential substrate locations. For example, the ion bombardment 160 has various parameters and can be performed in several steps, where each etching process is performed with a differential resist mask 140. Similarly, the plasma etching process 180 may not completely remove each layer 117 and may also be performed in several steps using differential resist masks 170.

2A-2J, a further exemplary embodiment will be described. In FIG. 2A, the semiconductor device 250 includes a first transistor element 200n and a second transistor element 200c. Configurations of the first and second transistors 200n and 200p may be the same as those described with reference to FIG. 1A, and the same reference numerals are used except that “2” is used instead of the leading “1”. Was used. Therefore, detailed descriptions of these components are omitted.

2B schematically illustrates a semiconductor device 250 having a first dielectric layer 216, which may include a first liner 216a, a stress inducing layer 216b, and a second liner 216c. In one embodiment, the liners 216a and 216c may be formed of silicon dioxide, while the stress inducing layer 216b may comprise silicon nitride. Methods of depositing silicon dioxide are well proven and can be readily applied to the formation of the liners 216a and 216c. For the formation of the stress inducing layer 216b, the same criteria apply as described above with respect to the dielectric layer 116 in FIG. 1B. For convenience, assume that the stress inducing layer 216b includes grain stress, which is transmitted to the second transistor element 200p, while the first transistor 200n receives tensile stress. However, in other embodiments, the stress inducing layer 216b may have a tensile stress.

2C schematically shows a semiconductor device 250 with a resist mask 240, which covers the second transistor 200p and exposes the first transistor 200n. Furthermore, semiconductor device 250 is subjected to wet chemical etching process 260 to remove exposed portions of liner 216c. In one particular embodiment, the wet chemical etching process is based on dilute hydrofluoric acid (HF), which has a significantly reduced etch rate for the resist mask 240 while the silicon in the liner 216c. Attacks dioxide. Corresponding etching methods for selectively removing silicon dioxide by HF have been well proven in the art.

2D schematically illustrates semiconductor device 250 after removal of the exposed portion of liner 216c and removal of resist mask 240. Thus, the second transistor element 200p is still covered by the liner 216c, while the stress inducing layer 216b is exposed above the first transistor 200n.

In FIG. 2E, an additional wet chemical etching process 261 is applied to the semiconductor device 250 and is designed to selectively remove the stress inducing layer 216b while substantially not attacking the liners 216a and 216c. Can be. In one exemplary embodiment, the stress inducing layer 216b may comprise silicon nitride, and the etching chemistry may be based on hot phosphoric acid (H ₃ PO ₄ ), which is silicon It shows good etch selectivity for dioxide. As a result, the stress inducing layer 216b over the second transistor element 200p is below the etching region. Except for a few, the stress inducing layer 216b over the first transistor element 200n is essentially completely removed.

2F schematically illustrates a semiconductor device 250 with a resist mask 241 covering the first transistor element 200n while the second transistor element 200p is exposed. Furthermore, the semiconductor device 250 is further subjected to the wet chemical etching process 262 to remove the liner 216c exposed on the second transistor device 200p. Similar to the etching process 260, the process 262 may be based on HF if the liner 216c includes silicon dioxide, whereas the liner 216a on the first transistor 200n is provided. Is protected by the resist mask 241.

2G schematically illustrates the semiconductor device 250 after completion of the wet chemical etching process 262 and after removal of the resist mask 241. Thus, the second transistor 200p has an exposed stress inducing layer 216b formed thereon, while the first transistor 200n is still covered by the liner 216a. Next, a subsequent dielectric layer having an intrinsic stress different from the intrinsic stress of the stress inducing layer 216b may be deposited.

2H schematically illustrates a semiconductor device 250 in which a second dielectric layer 217 having a predetermined intrinsic stress, such as a tensile stress, is formed over the first and second transistor elements 200n and 200p. For certain deposition methods and properties of the layer, such as layer thickness, material composition, etc., the same criteria may be applied as previously described for layers 116, 117 and 216b. In one exemplary embodiment, second dielectric layer 217 may include silicon nitride having a suitable layer thickness to serve as a contact etch stop layer in subsequent fabrication processes.

2i schematically illustrates a semiconductor device 250 with an additional register mask 242 above, which exposes the second transistor element 200p while covering the first transistor element 200n. Since the stress induced in the channel region 204 of the second transistor element 200p has been determined at least in part by the stress inducing layer 216b and the dielectric layer 217, according to one embodiment, A process 263 may be applied to the two transistors 200p to mitigate or reduce the intrinsic stress in the layers 217. For this purpose, non-reactive ion treatment may be performed by ion implantation based on, for example, xenon, germanium, or the like, or plasma treatment based on argon, helium, or the like may be used. Process parameters of the processing 263 may be selected based on the total stress required in the channel region 204 of the second transistor 200p and according to the characteristics of the dielectric layer 217, such as layer thickness, material composition, and the like. Can be. As already described for ion bombardment 160 and plasma etching 180, the degree of stress relaxation and the location of stress relaxation may be processed by performing two or more steps having differential resist mask 242 and differential process parameters. Can be controlled.

In another embodiment, the influence of the dielectric layer 217 on the induced stress in the channel region 204 of the second transistor device 200p is prevented by removing the exposed portion of the layer 217 by a plasma etching process. In this case, preferably, the liner 216c is not removed (see FIG. 2F) and the liner 216c during plasma etching processes to reliably control the removal of the exposed portion of the layer 217. Is used as an effective etch stop layer or etch indicator. As a result, after the plasma etching process and the corresponding removal of the exposed portions of the layer 217, the stress in the channel region 204 of the second transistor 200p is essentially determined by the stress inducing layer 216b. On the other hand, the stress in the first transistor element 200n is essentially created by the remaining dielectric layer 217.

Again with respect to FIG. 2I, after completion of the treatment 263, the exposed portion of the layer 217 is essentially relaxed, where the stress is significantly reduced or adjusted to the required level.

FIG. 2J schematically illustrates a semiconductor device 250 in which a low stress layer 217b is left after the processing 263 and removal of the resist mask 242 are completed, wherein the low stress layer is formed of the second transistor element 200p. It does not contribute significantly to the total stress. Depositing an interlayer dielectric material such as silicon dioxide on the semiconductor device 250, and using the layers 216b and 217 on the one hand or the layer 217 as the etch stop layers on the other hand, each contact opening. Further processing can be continued by forming them. In combination with the layer 217p, the difference in thickness of the contact etch stop layer with respect to the first transistor 200n and the second transistor 200p, i.e., the layer 217 and the layer 216p, is still A liner 216a is provided on both transistor elements, an additional etch stop layer that opens each layer 217 to the transistor 200n on the one hand and the layer 216p to the transistor 200p on the other hand. It should be noted that since it is provided as the layer 217p in combination with, it has essentially no effect on the contact hole forming process.

3A schematically illustrates a cross-sectional view of a semiconductor device 350 including a first transistor element 300n and a second transistor element 300p, which may have a configuration as described with respect to FIGS. 1A and 2A. . Thus, corresponding components are denoted by the same number except for leading "3" instead of leading "1" or "2". As a result, detailed descriptions of these components are omitted here.

3B schematically illustrates a semiconductor device 350 having a dielectric layer 316, which may include, for example, a stress inducing layer 316b formed from silicon nitride and a liner 316c formed from silicon dioxide. For the liner 316c and the stress inducing layer 316b, the same criteria as previously described for the liners 216a and 216c and the stress inducing layer 216b apply. For example, the stress inducing layer 316b may include a compressive stress, which may be transmitted to the second transistor device 300p while a tensile stress is generated in the first transistor device 300n.

3C schematically illustrates a semiconductor device 350 in which a resist mask 340 is formed, which covers the second transistor element 300p and exposes the first transistor element 300n. Furthermore, the semiconductor device 350 is subjected to a plasma etching process 360 to remove exposed portions of the liner 316a and the stress inducing layer 316b. Corresponding plasma etching methods are well established in the art, and the process parameters used while the spacer elements 310 are formed may also be used.

FIG. 3D shows the semiconductor device 350 after the plasma etching process 360 has been completed and the resist mask 340 has been removed, thereby providing the stress inducing layer 316b and the liner with the second transistor 300p. Leaving 316c, while the first transistor 300n is essentially completely exposed.

3E schematically illustrates a semiconductor device 350 having a second dielectric layer 317 having a predetermined intrinsic stress, such as a tensile stress transmitted to the channel region 304 of the first transistor element 300n. The same criteria as previously described with respect to the layers 117 and 217 may be applied with respect to the characteristics of the dielectric layer 317 and the deposition parameters.

3F schematically illustrates a semiconductor device 350 in which a resist mask 341 is further formed, and the resist mask covers the first transistor element 300n while the second transistor element 300p is exposed. Furthermore, the semiconductor device 350 is exposed to a plasma etching atmosphere 361 to remove the exposed portion of the dielectric layer 317. Corresponding etching methods may well be achieved, for example in the form of methods used while the spacer element 310 is formed. During the etching process 361, the liner 316c acts as an etch stop layer or an etch indicator layer, thereby enabling reliable control of the etching process 361. After the exposed portions of the layer 317 are removed, any remaining portions of the liner 316c that are not consumed by the etching process 361 may be based on some embodiments, for example based on HF. It may be removed by a wet chemical etching process. The resist mast 341 is then removed.

3G shows, for example, layers 316b that induce compressive stress in channel region 304 of second transistor 300p and tensile stress in channel region 304 of first transistor device 300n, for example. A semiconductor device 350 is schematically shown having a remaining layer 317 leading to As in the embodiment described above, subsequent processing of semiconductor device 350 continues to form contact openings 381 and deposition of interlayer dielectric material 380, for example in the form of silicon dioxide, wherein the stress induction Layers 317 and 316b can be effectively used as etch stop layers during the anisotropic etching process.

As a result, the present invention provides a technique that allows the formation of stress-induced dielectric layers in direct contact with or located in close proximity to the transistor structures, wherein wet chemical etching processes, plasma etching processes, ions Conventional and well-established processes, such as implantation or plasma treatment processes, can be used to provide differential forms of stress inducing layers at the differential locations. Thus, the stress determination parameters are well controllable and allow for effective stress engineering. In particular, the stress induced in the respective channel regions of the transistor elements can be essentially controlled by the dielectric layer, and the dielectric layer can also act as a contact etch stop layer, so that the stress is also in combination with the contact etch stop layers. The stress engineering is greatly facilitated because it is essentially determined by one component which can be better controlled than two or more components such as spacers. Exemplary embodiments described with reference to the figures may be combined, and certain process steps may be replaced by process steps of other embodiments in any suitable manner.

The particular embodiments disclosed above are merely exemplary, while the invention may be modified or otherwise practiced, and equivalent methods will be apparent to those skilled in the art having the benefit of teaching herein. For example, the published process steps may be performed in a different order. Moreover, it is not intended to be exhaustive or to limit the details of the design or construction shown herein, but to what is described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified, and all such changes are considered within the spirit and scope of the invention. The protection required herein is therefore as disclosed in the claims below.

Claims (18)

Forming a first dielectric layer 116 having a first predetermined intrinsic mechanical stress on the first transistor element 100N and the second transistor element 100P; The second portion to expose a first portion of the first dielectric layer 116 formed on the first transistor element 100N and to cover a second portion of the first dielectric layer 116 formed on the second transistor element 100P. Forming a mask layer (140) over the transistor device; And Transforming the first intrinsic stress of the first portion into a modified instinsic stress by ion bombardment (160) on the first portion; Removing the mask layer (140); And Forming a second dielectric layer (117) having a second intrinsic stress on the dielectric layer (116), wherein the second intrinsic stress is different from the first intrinsic stress. delete 2. The method of claim 1, further comprising selectively removing the second dielectric layer (117) material over a second portion of the first dielectric layer (116). The first and second dielectric layers of claim 1, wherein the second dielectric layer 116 covers the first portion of the second dielectric layer 117 and is formed on the second portion of the first dielectric layer 116. And forming a second mask layer (170) to expose the second portion of the second dielectric layer (117). 5. The second intrinsic of the second portion of the second dielectric layer 117 by ion bombardment according to claim 4, in order to generate a second strained intrinsic stress in the second portion of the second dielectric layer 117. And deforming the stress. The method of claim 1, further comprising selectively forming a second dielectric layer having a second intrinsic stress on the first transistor element 100N before forming the first dielectric layer 116. Way. 7. The method of claim 6, wherein selectively forming the second dielectric layer comprises: forming the second dielectric layer over the first transistor element and the second transistor element, covering the first transistor element 100N; Forming a second mask layer 341 exposing the second transistor element 100P, and removing a first portion of the second dielectric layer exposed by the second mask layer 341. Method comprising a. 8. The method of claim 7, wherein forming the second dielectric layer over the first transistor element and the second transistor element comprises depositing a first liner 216A and determining the second intrinsic stress. Depositing a stress-inducing layer 216B, and depositing a second liner 216C, wherein the first and second liners 216A, 216C comprise the stress-inducing layer 216C. And selectively etchable relative to 216B. 10. The method of claim 8, wherein removing the first portion of the second dielectric layer comprises selectively etching the second liner 216C to expose the stress inducing layer 216B, and Selectively removing the exposed portion of the stress inducing layer (216B) to expose the liner (216A). 10. The method of claim 9, further comprising: removing the second mask layer, forming a third mask layer to cover the second transistor element and expose the first transistor element; Selectively etching the second liner (216C) to expose the stress inducing layer (216B) over the device. Forming a first dielectric layer over the first transistor element and the second transistor element, the first dielectric layer having a first predetermined intrinsic mechanical stress; Forming a first liner over said first dielectric layer over said first and second transistor elements, said first liner being selectively etchable with respect to said first dielectric layer; Selectively etching the first liner over the first transistor element while covering the second transistor element with a first resist mask; Removing the first resist mask and selectively etching the first dielectric layer by a wet etching process using the first liner on the second transistor as an etch mask to remove the first resist layer from the first transistor. Removing one portion; Forming a second dielectric layer on the first dielectric layer and the second portion of the first liner and on the first transistor element, the second dielectric layer being different from the first intrinsic stress; 2 has intrinsic stress; And Selectively performing the second intrinsic stress of the second transistor element and the second portion of the second dielectric layer over the second portion of the first dielectric layer by performing an ion bombardment process on the second portion of the second dielectric layer And modifying the method. 12. The method of claim 11, wherein selectively modifying the second intrinsic stress of the second portion of the second dielectric layer over the second transistor element and the first dielectric layer and the second portion of the first liner, A second resist covering the first portion of the second dielectric layer over the first transistor element and exposing the second portion of the second dielectric layer before performing the ion bombardment process on the second portion of the second dielectric layer Forming a mask. 13. The method of claim 12, wherein before forming the second dielectric layer, forming a third resist mask covering the first transistor element, and etching the first liner over the second portion of the first dielectric layer. Removing the third resist mask; and removing the third resist mask. 12. The method of claim 11, wherein selectively etching the first liner is performed as a wet etching process. 12. The method of claim 11, further comprising forming a second liner over the first and second transistor elements, prior to forming the first dielectric layer, wherein the second liner is relative to the first dielectric layer. Selectively etchable. The method of claim 15, wherein the material composition of the first liner and the second liner is different from the material composition of the first dielectric layer. delete delete

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