WO2002025699A2 - Matrice active tft pour capteur optique comportant une couche semi-conductrice photosensible, et capteur optique comportant une telle matrice - Google Patents

Matrice active tft pour capteur optique comportant une couche semi-conductrice photosensible, et capteur optique comportant une telle matrice Download PDF

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Publication number
WO2002025699A2
WO2002025699A2 PCT/FR2001/002900 FR0102900W WO0225699A2 WO 2002025699 A2 WO2002025699 A2 WO 2002025699A2 FR 0102900 W FR0102900 W FR 0102900W WO 0225699 A2 WO0225699 A2 WO 0225699A2
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WO
WIPO (PCT)
Prior art keywords
columns
pixel
lines
electrodes
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2001/002900
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English (en)
French (fr)
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WO2002025699A3 (fr
Inventor
Eric Sanson
Nicolas Szydlo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales Avionics LCD SA
Original Assignee
Thales Avionics LCD SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Avionics LCD SA filed Critical Thales Avionics LCD SA
Priority to EP01974379A priority Critical patent/EP1332519B1/fr
Priority to US10/380,757 priority patent/US6815716B2/en
Priority to DE60121785T priority patent/DE60121785T2/de
Priority to JP2002529812A priority patent/JP2004510328A/ja
Priority to AU2001293910A priority patent/AU2001293910A1/en
Publication of WO2002025699A2 publication Critical patent/WO2002025699A2/fr
Publication of WO2002025699A3 publication Critical patent/WO2002025699A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/191Photoconductor image sensors
    • H10F39/195X-ray, gamma-ray or corpuscular radiation imagers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/802Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes

Definitions

  • the invention relates to an active matrix of TFT (thin film transistor) for an optical sensor, of the type which comprises:
  • each transistor comprising a grid, a source and a drain;
  • a level of conductor according to a determined pattern forming an array of electrodes, each electrode defining an area called a pixel; the electrodes being connected to the drains of the transistors;
  • An active matrix of this type can be used in an optical sensor.
  • the electromagnetic radiation that strikes the photosensitive semiconductor layer is converted into electrical charges which are collected by the pixel electrodes. These electrical charges are analyzed in an electronic circuit to restore an image point by point, for example using liquid crystal displays (LCD).
  • LCD liquid crystal displays
  • a particular use of an active TFT matrix relates to the production of images from X-rays, the semiconductor layer advantageously being formed by selenium.
  • US 5,780,871 shows an active matrix of this type having a high pixel optical aperture which, however, leads to a sensitive capacitive coupling between pixel electrodes and lines, in spite of an insulating layer intended to combat this coupling; such capacitive coupling goes against the desired image quality.
  • a first object of the invention is to improve the image restored from an optical sensor equipped with an active TFT matrix as defined above.
  • a pixel electrode is located entirely inside a contour delimited by two successive lines and two columns, a clearance distance being provided between the interior edge of this contour and the periphery of the pixel so that the pixel electrode does not cover the rows or columns.
  • the reduction in the optical aperture which results from the reduction in the useful surface area of the pixel does not entail a significant reduction in charge recovery or a reduction in the quality of the image. This result seems to be due to the kinetic behavior of the carriers generated in a photosensitive semiconductor by electromagnetic radiation. Due to a side field created by the carriers, they naturally move towards the pixel electrodes.
  • the reduction in capacitive coupling obtained by reducing the dimensions of the pixel electrode does not cause any drawbacks as far as charge recovery is concerned.
  • the quality of the restored image is improved.
  • the average guard distance between the contour of the pixel electrode and the external contour formed by the rows and columns is substantially equal to twice the alignment tolerance of a photorepeater which makes it possible to produce the images of different patterns and drawings of circuits and electrodes on the plate resin.
  • the average value of the guard distance can be between 4 and 8 ⁇ m, preferably of the order of 6 ⁇ m.
  • the TFT transistor associated with each pixel is covered by the pixel electrode, and is thus protected.
  • the insulating layer provided between the electrodes and the columns is advantageously formed by a photosensitive or photoimageable resin.
  • a second object of the invention it is desired to improve the contrast of the images obtained, by having a high capacity on the pixels, for storing high charges. Indeed, the higher the stored charges, the better the image contrast.
  • the matrix comprises:
  • bridges provided for electrically connecting the successive storage lines and making it possible, when ordering a line of pixels, to distribute the discharge of the charges of the entire line of pixels over several parallel storage lines.
  • connections parallel to the columns are at the same level as the columns.
  • the storage lines are provided in a level located on the substrate below the level of the control lines; the storage lines form a capacitance with the pixel or drain electrodes, or with a specific electrode produced in the same level as the control lines, and a thin insulating level is located between the level of the storage lines and the level of the lines control .
  • the storage lines are substantially at the same level as the control lines.
  • a number of connections parallel to the columns can be provided equal to the number of columns, ie one bridge per pixel. It is also possible to provide a number of parallel connections less than the number of columns and therefore a number of bridges less than the number of pixels. In particular, provision may be made for a connection parallel to the columns every sixteen columns.
  • High capacity areas defined by the stacking of three layers namely "storage line level”, “fine insulation”, and “upper conductor level” define planar capacities in which the thin insulation is never used alone to electrically separate a step or step from the “storage line level "with a” higher driver level ". This improves the manufacturing yield.
  • the pixel comprises a device for protection against excessively high voltages integrated in the transistor when working in negative voltage, or comprising a diode and a specific transistor when working in positive voltage.
  • the invention also relates to an optical sensor, in particular for X-rays, equipped with an active matrix as defined above.
  • Figure 1 of these drawings is a plan view of a pixel of an active matrix according to the invention.
  • Figure 2 is a plan view, on a smaller scale, of a pixel and a connection parallel to the columns.
  • Figure 3 is a section developed along the line III-III of
  • FIG. 4 is a diagram of a pixel surrounded by two successive control lines and two successive columns.
  • Figure 5 is a plan diagram of a storage line between two control lines.
  • Figure 6 is a schematic section along the line VI-VI of Fig.5, on a different scale.
  • Figure 7 is an electrical diagram illustrating the storage lines.
  • Figure 8 is a vertical section of an alternative embodiment of
  • Figure 9 is a vertical section illustrating a stack for achieving a planar capacity.
  • FIG. 3 in which seven parallel vertical lines correspond to the seven changes of direction of the section line in Fig. 2.
  • An active matrix structure of TFT comprises, according to Fig. 3, bottom to top, a substrate 1 generally made of glass, an insulating grid layer 2, made of silicon nitride or equivalent material, formed on this substrate; a set of lines 3 for controlling the TFT transistors by forming their grid, this set 3 being placed on the substrate 1, under the layer 2. As visible in FIGS. 1 and 2, lines 3 are parallel and horizontal. Lines 3 can be formed by a titanium and molybdenum bi-layer.
  • a level of conductor 4 produced according to a determined design or pattern constitutes a matrix of electrodes.
  • Each electrode 5 is in contact, in a zone 6 forming the bottom of a bowl, with a conductive metal plate 7, for example made of molybdenum, of which an edge 8 comes above and in contact with a layer 9 of amorphous silicon , forming TFT transistor.
  • Layer 9 covers an area of layer 2, above the grid formed by line 3. Plate 7 forms the drain of the transistor.
  • Column 10 forms the source of the transistor.
  • the different columns 10 are parallel to each other, vertical according to the representation in FIG. 2.
  • An insulating layer 12 is provided between the pixel electrodes 5 and the columns 10.
  • the layer 12 has local openings so that each pixel electrode 5 is in contact with the plate 7 by its part referenced 6.
  • the layer 13 is advantageously made of selenium. This layer 13 is covered by an upper electrode 24 put under high voltage.
  • each pixel electrode 5 substantially rectangular or square, is located entirely within a contour defined by two successive columns 10 and two successive lines 3.
  • Guard distances g1 and g2 are provided respectively between the edges of the electrode 5 and the neighboring edges of the lines 3 and of the columns 10. These distances g1, g2 are preferably identical and substantially equal to twice the alignment tolerance of a photorepeater which produces, by exposure to a resin, the different images corresponding to the patterns of the rows, columns and electrodes.
  • the average value of g1 and g2 is advantageously between 4 and 8 ⁇ m, preferably substantially equal to 6 ⁇ m for pixels 5 distributed in a pitch of the order of 150 ⁇ m (the pitch corresponds to the distance between the centers of the pixels 5).
  • the pixel electrode 5 does not cover the lines 3 or the columns 10 so that the stray capacitances between the pixel electrode 5 and the lines and columns are significantly reduced.
  • storage lines 14 (Figs.2, 3 and 5) formed by a conductive surface, metallic, for example made of titanium, forming a ground bus.
  • a line 14, as illustrated in FIG. 5, is constituted by a succession of rectangular surfaces 15 located at a different level but facing a pixel electrode, so as to form the two plates of a capacity.
  • the surfaces 15 are connected by narrower strips 16 located at mid-width.
  • the ground bus or storage line 14 is not in the same plane as the control lines 3 and is not superimposed, even in part, on these lines. Short-circuit faults which could be created by dust or impurities are considerably reduced compared to the case where there is a superposition, or a juxtaposition.
  • the discharge of the charges by the storage lines 14 (15, 16) is controlled by the transistors 9, schematically represented by circles in FIG. 5, in response to a signal supplied on an appropriate control line 3.
  • connections 17 are provided parallel to the columns 10 and substantially at the same level; the connections 17, schematically represented in FIG. 7, electrically connect the successive storage lines 14.
  • a connection 17 and a storage line 14 As seen from Figs. 2 and 3, an electrical contact is established between a connection 17 and a storage line 14 by a projection 18 in the form of a trunk of an inverted pyramid bearing against a conductive plate 19.
  • This plate 19 is itself placed on a projection 20 , in the form of an inverted pyramid trunk, produced in a layer 21 of fine insulation to come into contact with a surface 15 of a storage line 14.
  • Lines 14 are connected to a reference voltage.
  • connection or bridge 17 can be provided per image element or pixel, but the number of connections 17 may be less than the number of image elements or pixel.
  • a bridge 17 for N columns.
  • a bridge 17 is provided for every sixteen columns 10.
  • the storage lines 14 are located on the substrate 1, below the level of the control lines 3.
  • a specific electrode 22, for example in the same metal as that of the lines 3 is provided at the same level as the control lines 3 from which it is isolated.
  • the electrode 22 is located under the major part of the pixel electrode 5, and is isolated from the plate 19 and the bridges 17.
  • the storage lines 14a are at the same level as the control lines 3, and are parallel to them.
  • the storage capacity is then formed directly between the pixel electrode 5, or the drain 1 _ and the line 14a.
  • the high capacity zones (FIG. 9) defined by the stacking of three layers, namely a conductive layer 14 constituting a "level located on the substrate", a layer 21 of "fine insulator", and an upper conductive level B , define planar capacities, that is to say that the fine insulator 21 is never used alone to electrically separate a step or a step such as M and a higher conductive level. This improves the manufacturing yield and avoids the risks of short circuits created by dust or impurities.
  • Pixel 5 can also have a device for protection against excessively high voltages.
  • This protection device is integrated in the transistor 9 when working under a negative voltage applied to the upper electrode 24 above the selenium layer.
  • each electrode 5 has, at its lower left angle according to FIGS. 1 and 2 or at its upper left corner according to Figs. 4 and 7, a sort of rectangular tab 5a, 5b, projecting laterally and transversely which covers the transistor. This results in protection of the transistor against overvoltages.
  • the protection device may comprise a specific diode or transistor limiting the voltage applied to the pixel to a determined value.
  • An optical sensor equipped with an active matrix according to the invention is particularly efficient due to the optimization of the pixel elementary 5 with regard to its design and manufacture.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Thin Film Transistor (AREA)
PCT/FR2001/002900 2000-09-19 2001-09-18 Matrice active tft pour capteur optique comportant une couche semi-conductrice photosensible, et capteur optique comportant une telle matrice Ceased WO2002025699A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP01974379A EP1332519B1 (fr) 2000-09-19 2001-09-18 Matrice active tft pour capteur optique comportant une couche semi-conductrice photosensible, et capteur optique comportant une telle matrice
US10/380,757 US6815716B2 (en) 2000-09-19 2001-09-18 Tft matrix for optical sensor comprising a photosensitive semiconductor layer, and optical sensor comprising such an active matrix
DE60121785T DE60121785T2 (de) 2000-09-19 2001-09-18 Aktive tft-matrix für einen optischen sensor mit lichtempfindlicher halbleiterschicht, und optischer sensor mit einer solchen matrix
JP2002529812A JP2004510328A (ja) 2000-09-19 2001-09-18 感光性半導体層を有する光センサ用のtftアクティブマトリックスおよび該マトリックスを有する光センサ
AU2001293910A AU2001293910A1 (en) 2000-09-19 2001-09-18 Tft matrix for optical sensor comprising a photosensitive semiconductor layer, and optical sensor comprising such an active matrix

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0011927A FR2814281B1 (fr) 2000-09-19 2000-09-19 Matrice active tft pour capteur optique comportant une couche semi-conductrice photosensible, et capteur optique comportant une telle matrice
FR00/11927 2000-09-19

Publications (2)

Publication Number Publication Date
WO2002025699A2 true WO2002025699A2 (fr) 2002-03-28
WO2002025699A3 WO2002025699A3 (fr) 2002-05-16

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PCT/FR2001/002900 Ceased WO2002025699A2 (fr) 2000-09-19 2001-09-18 Matrice active tft pour capteur optique comportant une couche semi-conductrice photosensible, et capteur optique comportant une telle matrice

Country Status (7)

Country Link
US (1) US6815716B2 (https=)
EP (1) EP1332519B1 (https=)
JP (1) JP2004510328A (https=)
AU (1) AU2001293910A1 (https=)
DE (1) DE60121785T2 (https=)
FR (1) FR2814281B1 (https=)
WO (1) WO2002025699A2 (https=)

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Also Published As

Publication number Publication date
WO2002025699A3 (fr) 2002-05-16
JP2004510328A (ja) 2004-04-02
AU2001293910A1 (en) 2002-04-02
DE60121785T2 (de) 2007-10-18
FR2814281B1 (fr) 2003-08-29
EP1332519B1 (fr) 2006-07-26
FR2814281A1 (fr) 2002-03-22
US20040036092A1 (en) 2004-02-26
US6815716B2 (en) 2004-11-09
DE60121785D1 (de) 2006-09-07
EP1332519A2 (fr) 2003-08-06

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