WO2002021713A1 - Dispositif de mesure de rotation de phases et dispositif de station de base radio comprenant celui-ci - Google Patents
Dispositif de mesure de rotation de phases et dispositif de station de base radio comprenant celui-ci Download PDFInfo
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- WO2002021713A1 WO2002021713A1 PCT/JP2001/007586 JP0107586W WO0221713A1 WO 2002021713 A1 WO2002021713 A1 WO 2002021713A1 JP 0107586 W JP0107586 W JP 0107586W WO 0221713 A1 WO0221713 A1 WO 0221713A1
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- phase rotation
- detection
- output
- frequency offset
- delay detection
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/155—Ground-based stations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
- H04B1/712—Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
- H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
Definitions
- the present invention relates to a digital radio communication system, and more particularly to a phase rotation detection device used in a CDMA (Code Division Multiple Access) system and a radio base station device provided with the same.
- CDMA Code Division Multiple Access
- the base station and the communication terminal have independent clocks.
- the base station has a high-precision (0.1 ppm or less) oscillator
- the communication terminal In terms of cost, size, and power consumption, you will have an oscillator with a precision of a few ppm.
- the normal communication terminal has an AFC (Automatic Frequency Control) function to control the clock frequency shift based on the downlink received signal.
- AFC Automatic Frequency Control
- the frequency offset at the communication terminal (the correction error in the AFC that corrects the deviation of the clock frequency of the communication terminal) is still present in the reception of the uplink signal by the base station.
- AFC residual etc.
- the frequency offset of the received signal for example, 200Hz frequency offset Approximately 48 degrees between one slot
- high maximum Doppler frequency due to fading fluctuation (: fD) (for example, 240 Hz (corresponding to about 12 O kmZh / h)) and 57.
- the phase rotation due to greatly degrades the channel estimation, and as a result, the reception characteristics are significantly degraded.
- WM SA Weighted Multi-Symbol Averaging
- phase rotation detection is simply performed using a value obtained by averaging the phase rotation angle, and the reliability of the channel estimation value (estimated transmission characteristics) in m slots, that is, reception in that slot It does not consider the signal level or the magnitude of the differential detection output that depends on it. In general, if the desired signal level is low (the SIR (Signal to Interference Ratio) is low), the received signal is greatly affected by noise, and the reliability of the channel estimation value is low.
- SIR Signal to Interference Ratio
- the magnitude of the differential detection output depends on the magnitude of the channel estimation value of the slot before and after the complex conjugate operation. As described above, in this method, the reliability of the detection angle in the delay detection output is not considered at all, though it depends on the magnitude of the delay detection output. If the phase rotation detection is performed in such a state, the accuracy of the phase rotation detection decreases, and the channel estimation accuracy decreases.
- the interval between channel estimation values used for differential detection is fixed at one slot.
- An object of the present invention is to provide a phase rotation detection device capable of detecting a maximum Doppler frequency due to carrier frequency offset and fading fluctuation with high accuracy, and a radio base station device including the same.
- the present inventors have proposed that the phase rotation that needs to be corrected when performing channel estimation is caused by a correction error (AFC residual) in the AFC that corrects the shift of the clock frequency of the communication terminal.
- the difference is related to the frequency offset, which changes in a relatively gradual time order of several seconds or more due to the external environment (difference), and the fusing change, which frequently changes in the order of several milliseconds.
- the frequency offset component and the fading fluctuation component of the phase rotation are individually detected, and the detected phase rotation value is reflected in the channel estimation in consideration of the reliability of the frequency offset component and the fading fluctuation component. As a result, it has been found that the accuracy of channel estimation can be improved, and the present invention has been made.
- An object of the present invention is to separately detect a frequency offset component and a fading fluctuation component of phase rotation from a known signal included in a received signal, and perform vector synthesis of the delayed detection output to improve the reliability of the received signal. Considering this, high detection accuracy can be achieved by detecting the maximum Doppler frequency using the delayed detection output after frequency offset correction.
- FIG. 1 is a block diagram showing a configuration of a base station provided with a phase rotation detection device according to Embodiment 1 of the present invention
- FIG. 2 is a block diagram showing a configuration of a channel estimation circuit of the base station shown in FIG. 1;
- FIG. 3 is a block diagram showing a configuration of a phase rotation detection circuit in the channel estimation circuit shown in FIG. 2;
- FIG. 4 is a block diagram showing a configuration of a communication terminal that performs radio communication with a base station provided with the phase rotation detection device according to Embodiment 1 of the present invention
- FIG. 5 is a diagram for explaining a time interval of differential detection in the phase rotation detection device of the present invention.
- FIG. 6 is a block diagram showing a configuration of a delay detection circuit of the phase rotation detection device according to the second embodiment of the present invention.
- FIG. 6 is a diagram showing a table used in a delay detection circuit of the phase rotation detection device according to the second embodiment of the present invention
- FIG. 8 is a block diagram showing another configuration of the delay detection circuit of the phase rotation detection device according to Embodiment 2 of the present invention
- FIG. 9 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 3 of the present invention.
- FIG. 10 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 4 of the present invention.
- FIG. 11 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 5 of the present invention.
- FIG. 12 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 6 of the present invention.
- FIG. 13 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 7 of the present invention.
- FIG. 14 is a diagram showing a D determination table used in the phase rotation detection device according to Embodiment 7 of the present invention.
- FIG. 15 is a block diagram showing a configuration of a base station including a phase rotation detection device according to Embodiment 8 of the present invention.
- FIG. 16 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 8 of the present invention.
- FIG. 17 is a block diagram showing a configuration of a base station including a phase rotation detection device according to Embodiment 9 of the present invention.
- FIG. 18 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 9 of the present invention.
- FIG. 19 is a block diagram showing a configuration of a base station provided with a phase rotation detection device according to Embodiment 10 of the present invention.
- FIG. 20 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 10 of the present invention.
- FIG. 21 shows a detection timing change of the phase rotation detection according to Embodiment 10 of the present invention. Diagram showing further changes;
- FIG. 22 is a diagram showing a change in detection timing of phase rotation detection according to Embodiment 10 of the present invention.
- FIG. 23 is a block diagram showing an example of a configuration of a phase rotation detection circuit according to Embodiment 11 of the present invention.
- FIG. 24 is a flowchart for explaining switching control of phase rotation detection according to Embodiment 11 of the present invention.
- FIG. 25 is a block diagram showing another example of the configuration of the phase rotation detection circuit according to Embodiment 11 of the present invention.
- phase rotation due to frequency offset and phase rotation due to fusing variation are individually calculated, and both phase rotations are corrected.
- FIG. 1 is a block diagram showing a configuration of a base station including a phase rotation detection device according to Embodiment 1 of the present invention.
- the base station shown in FIG. 1 a case will be described where the number of paths for RAKE combining is 2, but the present invention can also be applied to a case where the number of paths for RAKE combining is 3 or more.
- the base station shown in FIG. 1 for simplicity, only one user sequence is shown. Therefore, the same can be applied to a series of a plurality of users.
- the signal transmitted from the communication terminal that is the communication partner is transmitted from antenna 101 to the duplexer.
- the signal is received by the wireless receiving circuit 103 via the signal receiving circuit 103.
- the radio reception circuit 103 performs predetermined radio reception processing (down conversion, A / D conversion, etc.) on the received signal, and outputs the signal after the radio reception processing to the correlators 104 and 105. Output.
- the signal after the radio reception processing is output to search circuit 106.
- the correlator 104 despreads the data part (DPD CH (Dedicated Physical Data Channel)) of the signal after the radio reception processing using the spreading code used in the spread modulation processing at the communication terminal as the communication partner.
- the signal is processed and output to the delay device 1071 of the synchronous detection circuit 107 and the delay device 1081 of the synchronous detection circuit 108.
- Correlator 105 performs despreading processing on the pilot portion (known signal) of the signal after the radio reception processing using the spreading code used in the spread modulation processing at the communication terminal as the communication partner, and performs synchronous detection.
- the signal is output to the channel estimation circuit 1072 of the circuit 107 and the channel estimation circuit 1082 of the synchronous detection circuit 108.
- the search circuit 106 synchronizes the path for performing the despreading process, and outputs the timing information to the correlator 104 and the correlator 105.
- Correlator 104 and correlator 105 perform despreading processing based on the timing information from search circuit 106.
- Channel estimation circuit 1072 of synchronous detection circuit 107 performs channel estimation using the pilot portion of the received signal, and outputs the channel estimation value to multiplier 1073.
- the multiplier 1073 multiplies the data portion of the received signal, the timing of which has been corrected by the delay unit 1071, by the channel estimation value. As a result, synchronous detection is performed.
- the signal after the synchronous detection is output to RAKE combiner 109.
- Channel estimation circuit 1082 of synchronous detection circuit 108 performs channel estimation using the pilot portion of the received signal, and outputs the channel estimation value to multiplier 1083.
- the multiplier 1083 multiplies the data portion of the received signal, the timing of which has been corrected by the delay unit 1081, with the channel estimation value. As a result, synchronous detection is performed.
- the signal after the synchronous detection is output to RAKE combiner 109.
- RAKE combiner 109 RAKE combines the outputs from synchronous detection circuit 107 and synchronous detection circuit 108 and outputs the signal after RAKE combination to demodulation circuit 110.
- the demodulation circuit 110 performs demodulation processing on the RAKE-combined signal to obtain received data.
- the transmission data is output to the spreading circuit 112 after being modulated by the modulation circuit 111.
- the spreading circuit 112 applies a predetermined spreading code to the data after the modulation processing.
- And performs spread modulation processing, and outputs the data after the spread modulation processing to the wireless transmission circuit 113.
- the wireless transmission circuit 113 performs predetermined wireless transmission processing (D / A conversion, up-conversion) on the data after the spread modulation processing.
- the signal subjected to the wireless transmission processing is transmitted from the antenna 101 to the communication terminal that is the communication partner via the duplexer 102.
- FIG. 2 is a block diagram showing a configuration of a channel estimation circuit of the base station shown in FIG.
- the multiplier 201 multiplies the despread signal by the phase rotation correction value for each symbol, and outputs the multiplied signal to the multiplier 202.
- Multiplier 202 multiplies the de-spread signal after phase rotation correction for each symbol by a pilot pattern (PL pattern), and eliminates the demodulated modulation component due to the PL pattern to make them in-phase.
- the multiplication result is output to the in-phase addition circuit 203.
- the in-phase addition circuit 203 adds the in-phase result of the multiplication to obtain a channel estimation value in slot units.
- the multiplication of the phase rotation correction value for each symbol, the multiplication of the PL pattern, and the in-phase addition are processing in a slot.
- This channel estimation value is output to the weighting and adding circuit 204.
- the signal after the despreading processing is output to the phase rotation detection circuit 205.
- the frequency offset is obtained from the signal after the despreading processing
- the maximum Doppler frequency (hereinafter, the Doppler frequency or fD) is obtained from the signal after the despreading processing.
- the frequency offset and the maximum Doppler frequency are detected individually.
- the frequency offset detection result (the amount of phase rotation corresponding to the frequency offset) detected by the phase rotation detection circuit 205 includes a slot-by-slot phase rotation correction circuit 207 and a symbol-by-symbol phase rotation correction circuit 209, 21 Output to 0.
- the maximum Doppler frequency (the amount of phase rotation corresponding to fD) is output to the weight coefficient calculation circuit 208.
- the detection accuracy is lower than the detection accuracy of the frequency offset (for example, approximately several tens of Hz, or the detection speed of low speed / medium speed Z high speed).
- the symbol-by-symbol phase rotation correction circuit 210 calculates a phase rotation correction value ⁇ 0 symbol for each symbol based on the phase rotation amount of the frequency offset, and outputs the phase rotation correction value A 0 symbol to the multiplier 210. Output.
- the slot-based phase rotation correction circuit 207 calculates a phase rotation correction value A ⁇ slot for each slot based on the phase rotation amount of the frequency offset, and outputs the phase rotation correction value slot to the weighting addition circuit 204. .
- the symbol-by-symbol phase rotation correction circuit 209 calculates a phase rotation correction value symbol for each symbol based on the frequency offset component, and outputs the phase rotation correction value AS symbol to the multiplier 206.
- the weight coefficient calculation circuit 208 calculates a weight coefficient (H) according to the fD detection value, and outputs the weight coefficient ⁇ to the weighting addition circuit 204.
- the weighting and adding circuit 204 uses the phase rotation correction value A 6> slot from the slot / phase rotation correction circuit 207 and the weighting factor H from the weighting factor calculation circuit 208 for slot units over a plurality of slots. Weighted addition is performed on the channel estimation value. Therefore, this weighted addition processing is processing between slots. In this way, a channel estimation value for each symbol or a slot average channel estimation value is obtained from the channel estimation values weighted and added over a plurality of slots. In this case, if necessary, as the channel estimation value, the slot average channel estimation value output from the weighting addition circuit 204 may be used, or the slot average value output from the weighting addition circuit 204 may be used.
- the channel estimation value for each symbol obtained by multiplying the channel estimation value for each symbol by the phase rotation correction value A 6> symbol for each symbol in the multiplier 206 is used.
- the phase rotation detection circuit 205 separately considers the phase rotation by the frequency offset component (frequency offset detection result) and the phase rotation by the maximum Doppler frequency component (fD detection result) in consideration of the reliability of the received signal. Ask. That is, in the frequency offset detection and the maximum Doppler frequency detection, the received signal level in the slot or the magnitude of the differential detection output depending on the received signal level is considered.
- phase rotation detection by separately obtaining the frequency offset component and the maximum Doppler one frequency component, different types of factors affecting the phase rotation can be individually corrected.
- the frequency offset component and the maximum Doppler The phase rotation can be accurately detected by considering the reliability of the received signal level in the slot or the size of the delay detection output depending on the detection. Can be corrected. As a result, highly accurate channel estimation can be performed, and the reception performance at the base station cannot be improved.
- the signals after the despreading process (despread signals) from the correlators 104 and 105 are output to the quadrant correction circuit 205.
- the quadrant correction circuit 205 performs quadrant correction on the despread signal. That is, in-phase addition can be performed by aligning certain quadrants with signal points.
- the quadrant-corrected signal is output to intersymbol averaging circuit 205.
- the intersymbol averaging circuit 205 averages the in-phase addition result over the period (between symbols) in which the delay detection is performed.
- the averaged in-phase addition result is output to the differential detection circuit 205.
- the differential detection circuit 2053 performs differential detection using the averaged in-phase addition result. This differential detection output is sent to the averaging circuit 205 and the multiplier 2060. In the averaging circuit 205, the differential detection output is averaged (vector synthesis) as it is over several tens of frames, for example, in order to improve the accuracy of the differential detection output. The averaged differential detection output is output to the inter-finger averaging circuit 205. The finger-to-finger averaging circuit 205 averages the differential detection output averaged between the fingers. The differential detection output averaged between the fingers is output to the normalization circuit 205.
- the differential detection output averaged between the fingers is normalized. This is because when the differential detection output averaged between the fingers is used to detect the maximum Doppler frequency, it is necessary to use only the angle information.
- the regulated differential detection output is output to the multiplier 260 and is obtained as a frequency offset detection result.
- FIG. 3 illustrates the case where the frequency offset detection result is output from the normalization circuit 258, but the output from the finger-to-finger averaging circuit 257 is used as the frequency offset detection result. You may use as.
- the differential detection output from the differential detection circuit 2053 is multiplied by the complex conjugate of the normalized differential detection output. As a result, a delayed detection output after frequency offset correction is obtained.
- the delay detection output after the frequency offset correction is output to the absolute value calculation circuit 205.
- the absolute value calculation circuit 205 calculates the absolute value of the delay detection output after the frequency offset correction. This is because the direction of the phase rotation due to the Doppler frequency is not constant, and if averaging is performed as it is, fD cannot be detected accurately.
- the differential detection output whose absolute value has been calculated is output to the averaging circuit 205.
- the averaging circuit 20556 in order to improve the accuracy of the differential detection output, the differential detection output is averaged (vector synthesis) as it is over several tens of frames, for example.
- the averaged differential detection output is output to the inter-finger averaging circuit 205.
- the finger-to-finger averaging circuit 205 averages the differential detection output averaged between the fingers.
- the delayed detection output averaged between the fingers is a detection result.
- the base station shown in FIG. 1 as described above constitutes a digital radio system based on the CDMA system with the communication terminals shown in FIG. 4, and the base station shown in FIG. Wireless communication is performed by the communication terminal shown in FIG. Next, this communication terminal will be described with reference to FIG.
- FIG. 4 is a block diagram showing a configuration of a communication terminal that performs radio communication with a base station provided with the phase rotation detection device according to Embodiment 1 of the present invention.
- the communication terminal shown in FIG. 4 a case will be described where the number of paths to be combined is 1, but the present invention can be applied to a case where the number of paths to be combined is 2 or more.
- a signal transmitted from a base station as a communication partner is received by a wireless receiving circuit 303 from an antenna 301 via a duplexer 302.
- the wireless reception circuit 303 performs predetermined wireless reception processing on the received signal, and outputs the signal after the wireless reception processing to the correlator 304 and the search circuit 307.
- the correlator 304 performs despreading processing on the signal after the radio reception processing using the spreading code used in the spread modulation processing at the communication terminal that is the communication partner to perform channel estimation, synchronous detection, Output to the synthesis circuit 305.
- the correlator 304 performs despreading processing based on the timing information from the search circuit 307.
- the channel estimation, synchronous detection, and synthesis circuit 305 perform channel estimation using the pilot portion (known signal) of the signal after the wireless reception processing to obtain a channel estimation value. Multiplication is performed on the data portion of the signal after the reception processing to perform synchronous detection. Further, the channel estimation / synchronous detection / synthesis circuit 305 performs RAKE synthesis using the signal after the synchronous detection.
- the signal after RAKE combining is output to demodulation circuit 306.
- the demodulation circuit 306 performs demodulation processing on the signal after RAKE combining to obtain received data.
- the transmission data is modulated by the modulation circuit 308 and then output to the spreading circuit 309.
- the spreading circuit 309 performs a spread modulation process on the data after the modulation process using a predetermined spreading code, and outputs the data after the spread modulation process to the radio transmission circuit 310.
- the radio transmission circuit 310 performs a predetermined radio transmission process on the data after the spread modulation process.
- the signal subjected to the wireless transmission processing is transmitted from antenna 301 to base station which is a communication partner via duplexer 302. Next, a specific operation of the phase rotation detecting device having the above configuration will be described.
- the base station receives the uplink signal from the communication terminal and performs despreading processing on the received signal using a correlator.
- the despread signal is output to the phase rotation detection circuit 205 in each case.
- the phase rotation detection circuit 205 the frequency offset and fD are individually detected.
- the delay detection output (detection vector) is added (combined). This is because the detection of the phase rotation due to the frequency offset depends on the delay detection output as described above, so that the delay detection output is added as it is. As described above, since the frequency offset is detected in consideration of the reliability of the differential detection output, high detection accuracy can be realized. Also, in this case, the hardware scale can be reduced because the arctangent function in the conventional angle calculation is not used.
- fD a method of detecting the maximum Doppler frequency
- the maximum Doppler frequency is detected using the differential detection output value. Specifically, the inner product is not used for phase rotation detection, and the delay detection outputs (I and Q outputs) between the measurement cycles are added as they are (vector synthesis). However, for the orthogonal component (Q component), add the absolute value.
- the reliability of the detection angle in the delay detection output depends on the magnitude of the delay detection output, and the delay detection output is synthesized as it is. Thereby, high detection accuracy can be realized. Also, in this case, the hardware scale can be reduced because the arc tangent function in the conventional angle calculation is not used.
- the measurement cycle (averaging count) can be variable. For example, control is performed according to the reception SIR (Signal to interference Ratio) and the moving speed. In addition, even if the accuracy is slightly low, such as when starting communication, the detection time must be reduced before entering communication. In such cases, make the measurement cycle shorter than usual. As described above, the measurement cycle may be controlled according to the use situation. This will be described later.
- the maximum Doppler frequency is detected after performing the frequency offset correction on the differential detection output value as described above.
- Frequency offset correction is performed by normalizing the value (averaged differential detection output) that detected the frequency offset, and then multiplying the complex conjugate by the complex conjugate.
- the delay detection output corrected for the frequency offset is added over the measurement period.
- the absolute value is added for the quadrature component (Q component). This value is averaged (combined) between fingers. The value averaged between the fingers is normalized, and the orthogonal component value is calculated to obtain the detection value. Finally, the detected value is compared with the data for judgment (judgment template) to perform fD judgment to obtain an fD detection result.
- the average value of the differential detection output obtained for each finger is averaged by vector addition for each finger as in the following equation (3).
- the positive and negative Doppler shifts of the frequency due to fading are corrected in the obtained average value of the delayed detection output, and the rotation component due to the frequency offset is included.
- the phase rotation due to the frequency offset obtained as described above is removed from the delay detection output, and the component of Doppler shift due to faging is detected.
- the average value of the differential detection output is normalized, and only the rotational component is extracted.
- the differential detection output is multiplied by the complex conjugate of the rotation by the frequency offset obtained in the above equation (4) to correct the rotation component due to the frequency offset.
- One frequency of the fading dobbler is detected from the delayed detection output after correcting the frequency offset.
- phase rotation occurs in both positive and negative directions, so it cannot be determined by simply taking the vector average. Therefore, as shown in the following equation (6), the absolute value of the Q component of the obtained delay detection output after frequency offset correction is calculated, and then the vector average, that is, the I component and the Q component are calculated. And averaged. As a result, the maximum Doppler frequency vector can be calculated.
- the average value of the differential detection output after frequency offset correction obtained for each finger is further vector-combined (averaged) between the fingers as shown in the following equation (7).
- the phase rotation caused by the frequency offset can be considered constant for the measurement time (on the order of several seconds). Since the phase rotation due to fading fluctuation is not constant even in a short section in both the rotation amount and the rotation direction, the difference between the long-term average detection value and the instantaneous phase rotation amount is large, and the phase rotation correction is performed based on the erroneous detection value. Doing so may degrade the channel estimation accuracy.
- phase rotation caused by the frequency offset and the phase rotation caused by fD are separately detected, and both phase rotation amounts are reflected in the channel estimation. It is possible to prevent channel estimation degradation when the difference from the phase rotation amount is large, and to reduce the influence of phase rotation on in-phase addition due to fading.
- the frequency offset detection result obtained by the phase rotation detection circuit 205 is output to the symbol-based phase rotation correction circuits 209 and 210 and the slot-based phase rotation correction circuit 207. That is, in the present invention, the correction for each symbol and the correction for each slot before weighting addition are used as the phase rotation correction. Therefore, in the intra-slot processing, the phase rotation is corrected on a symbol-by-symbol basis, and the phase rotation is corrected on a slot-by-slot basis (using the preceding and succeeding slots).
- phase rotation correction By performing such two-stage phase rotation correction, first, frequency offset components are removed from the channel estimation value of each symbol by symbol-by-symbol correction, and channel estimation accuracy in slot units by in-phase addition is improved. In addition, by removing the frequency offset component between the preceding and succeeding slots with respect to the demodulation slot in the WM SA, it is possible to improve the channel estimation accuracy by weighted addition by the WM SA. Thus, at the symbol level and at the slot level, Since the phase rotation correction can be performed in a short time, the channel estimation value can be obtained with higher accuracy.
- phase rotation correction value is obtained by the following specific calculations.
- phase rotation correction value in symbol units obtained by the symbol-by-symbol phase rotation correction circuit 209, 210 is
- the phase rotation correction value per slot obtained by the slot-by-slot phase rotation correction circuit 207 is
- the phase rotation correction value symbol of the symbol-by-symbol phase rotation correction circuit 210 is output to the multiplier 201 and is multiplied by the despread signal before the PL pattern multiplication. As a result, the phase rotation is corrected for each symbol before correlating with the PL pattern. PL is applied to the despread signal of the pilot part whose phase rotation has been corrected for each symbol.
- the correlation output pl (m) multiplied by the noise is output to the in-phase addition circuit 203. In the in-phase addition circuit 203,
- ch (t, m) is a channel estimate of t slot, m symbol.
- the channel estimation value is a value before weighted multi-symbol averaging (WMS A).
- the channel estimation value after the in-phase addition is output to the weighting addition circuit 204.
- the weighting and adding circuit 204 performs WMS A using the weighting factor calculated by the weighting factor calculating circuit 208 and the phase rotation correction value A0slot output from the per-slot phase rotation correction circuit 207.
- WMSA correction focuses on the slot to be demodulated.
- WMSA calculates the channel estimation value of the m-th symbol of the n-th slot of the first branch as shown in the following equation (12).
- i ( ⁇ l) is a weighting factor
- t —2, —1, 0, +1 and +2 are used, but the number of slots is not particularly limited.
- w (t) is a WMSA weighting factor.
- CH (t, m) is a channel estimate for t slots, m symbols. This channel estimate is after WM S A.
- the WMSA calculation after the correction between the slots is performed.
- the estimation value is corrected according to the head of the slot. Therefore, if WMSA is performed as it is, the obtained channel estimation value corresponds to the one at the beginning of the slot. For this reason, when calculating the channel estimation value for each symbol and performing synchronous detection, the phase detection starts from the next symbol at the beginning.
- the shift correction value AS symbol By multiplying the shift correction value AS symbol, the channel estimation value of each symbol can be obtained. That is, when the channel estimation value for each symbol is obtained, the output of the weighting addition circuit 204 is multiplied by the multiplier 206 with the phase rotation correction value symbol obtained by the phase rotation correction circuit 209 for each symbol. (Symbol-based processing).
- the slot average channel estimation value or the symbol-based channel estimation value can be changed as appropriate.
- an instruction that the channel estimation value is in symbol units is input to the symbol-by-symbol phase rotation correction circuit 209, and the symbol-by-symbol phase rotation correction circuit 209 receives the instruction in response to the instruction. Therefore, the output of the weighting addition circuit 204 is multiplied by the phase rotation correction value symbol.
- the slot average channel estimation value is used, the channel estimation value is adjusted to the slot median value according to the effect that the channel estimation value is the slot average.
- the state of change separately corrects the phase rotation caused by the frequency offset and the phase rotation caused by the fading fluctuation, and reflects both corrections in the channel estimation.
- the estimation accuracy can be improved.
- channel estimation is performed by correcting the phase rotation in symbol units (in-slot processing) before in-phase addition of the despread signal, and correcting the phase rotation in slot units (in-slot processing) after in-phase addition.
- channel estimation accuracy can be improved.
- the channel estimation value of the symbol may be calculated or the channel estimation value of each symbol may be obtained.
- the frequency offset and the maximum Doppler frequency are individually determined in consideration of the reliability of the received signal by performing vector synthesis of the differential detection outputs. Since phase rotation detection is performed, angle calculation (inverse tangent function) for correction is not required, and the hardware scale can be reduced. In addition, in the detection of the maximum Doppler frequency, the influence of the frequency offset can be eliminated, so that the maximum Doppler frequency can be detected with high accuracy.
- Delay detection in frequency offset detection and maximum Doppler frequency detection is performed using channel estimation values at arbitrary time intervals.
- the value of the delay detection output varies depending on the time interval at which the delay detection is performed. For example, a time interval of 1 Z
- the phase rotation amount will be 1 Z2, and the delay detection output will decrease accordingly.
- the phase rotation is reliably detected by increasing the delay detection time interval to avoid the effect of noise. It is desirable. Conversely, if the amount of phase rotation is large, it may be erroneously detected that the delay detection time interval is too large. Therefore, it is desirable to reduce the delay detection time interval. Thus, it is considered that there is an optimal delay detection time interval for the phase rotation amount assumed as the detection target.
- the delay detection interval is one slot.
- the delay detection interval is two slots.
- the delay detection interval is 0.3 slot (more precisely, 10 Z3 slots).
- the delay detection time interval is not limited to these three types. In this way, by using the differential detection outputs with different time intervals, it is possible to perform more accurate phase rotation detection.
- a differential detection circuit 205 having the configuration shown in FIG. 6 is used.
- the delay detection circuit 205 holds a lookup table 405 storing the correct relationship between the three types of delay detection output values and the amount of phase rotation as shown in FIG.
- a delay detection circuit (0.3 slot delay detection circuit 401, 1 slot delay detection circuit) that always operates at these three types of time intervals for phase rotation detection. 4 0 2, 2 slot delay detection circuit 4 0 3), all of these delay detection circuits 4 0 1 to 4 0 3 are operated, and their delay detection outputs are compared to the comparison section 4. 0 Output to 4.
- the comparing section 404 compares each differential detection output with the reference table 405 and outputs an optimal differential detection output. For example, when the amount of phase rotation to be detected is small, the delay detection output value at the interval of 0.3 slot is small, so there is no reliability, and the amount of phase rotation is detected using the delay detection output value at the interval of two slots. On the other hand, if the amount of phase rotation to be detected is large, erroneous detection may be made only from the output at the 2-slot interval. Compare with 4.5 to select differential detection output. It is to be noted that, instead of using the template as shown in FIG. 7, the configuration may be such that the time interval is switched appropriately according to the amount of phase rotation. Also, instead of always operating the three types of delay detection circuits 401 to 403, the switching control unit 406 switches and operates the delay detection circuit by using a configuration as shown in FIG. Is also good.
- the operation of the delay detection circuit for two slots 403 is stopped and the operation is stopped.
- the slot delay detection circuit 401 is operated. If the detected phase rotation amount is small, the 0.3-slot delay detection circuit 401 is stopped, and the 2-slot delay detection circuit 403 is operated. As a result, the phase rotation amount can be detected with higher accuracy.
- phase rotation detection is performed using only the high-level output, excluding the low-level output among the differential detection outputs. Thereby, the detection accuracy can be improved.
- FIG. 9 is a block diagram showing a configuration of a phase rotation detection device according to Embodiment 3 of the present invention.
- the same parts as those in FIG. 3 are denoted by the same reference numerals as those in FIG.
- the phase rotation detection device includes a threshold value determination circuit 501 that selects a highly reliable differential detection output in consideration of the reliability of the differential detection output. That is, the delay detection output from the delay detection circuit 205 is sent to the threshold determination circuit 501, and the threshold detection circuit 501 detects the delay detection output and the delay detection output selection threshold. Are compared, and only the differential detection output exceeding the threshold value is output to the averaging circuit 205 and the multiplier 206.
- a threshold value used for finger assignment of the path search unit can be used.
- the finger assignment threshold is a threshold for selecting an effective path, which is obtained from the average value of noise levels other than the peak to which the finger is assigned in the delay port file used for the path search.
- the delay detection output having a low reception level, that is, the low reliability is deleted, and the phase rotation is detected using only the high reliability delay detection output. Accuracy can be improved.
- FIG. 10 is a block diagram showing a configuration of a phase rotation detection device according to Embodiment 4 of the present invention. 10 that are the same as in FIG. 3 are assigned the same reference numerals as in FIG. 3, and detailed descriptions thereof are omitted.
- the phase rotation detection device includes a threshold determination circuit 6001 that selects a highly reliable delay detection output having a frequency offset corrected in consideration of the reliability of the frequency offset corrected delay detection output. Have. That is, the threshold detection is performed after the delay detection output from the delay detection circuit 205 is corrected for frequency offset. The delay detection output and the delay detection output selection threshold are compared in the threshold determination circuit 601, and only the delay detection output exceeding the threshold is sent to the absolute value calculation circuit 205. Output.
- the delay detection output after the frequency offset correction having a low reception level, that is, low reliability is deleted, and only the delay detection output after the high reliability frequency offset correction is used. Since the phase rotation detection is performed by using this method, the detection accuracy can be improved.
- a method of adding only the differential detection output of the finger having the maximum reception level (for example, determination based on the level in the delay profile) among a plurality of fingers can be used.
- FIG. 11 is a block diagram showing a configuration of a phase rotation detecting device according to Embodiment 5 of the present invention.
- the same parts as those in FIG. 3 are denoted by the same reference numerals as in FIG. 3, and detailed description thereof will be omitted.
- the phase rotation detection device includes a maximum value determining circuit 7 0 1 that selects a highly reliable delayed detection output having a frequency offset corrected in consideration of the reliability of the delayed detection output having a frequency offset corrected. It has.
- the maximum value determination circuit 701 selects the maximum output from the delay detection outputs after the frequency offset correction between the fingers.
- the delay detection output from the delay detection circuit 205 is sent to the maximum value selection circuit 701 for each finger after the frequency offset correction, and the maximum value selection circuit 701 detects the delay detection for each finger.
- the delay detection output having the highest level is selected from the outputs, and the delay detection output is output to the absolute value calculation circuit 205.
- the delay detection output after the frequency offset correction with low reception level that is, low reliability, is deleted, and the frequency with high reliability is reduced. Since the phase rotation detection is performed using only the delayed detection output after the number offset correction, the detection accuracy can be improved.
- FIG. 12 is a block diagram showing a configuration of a phase rotation detection device according to Embodiment 6 of the present invention. 12 that are the same as in FIG. 3 are given the same reference numerals as in FIG. 3, and detailed description thereof is omitted.
- the phase rotation detection device includes a maximum value determining circuit 7 0 1 that selects a highly reliable delayed detection output having a frequency offset corrected in consideration of the reliability of the delayed detection output having a frequency offset corrected. It has. Further, a threshold determination circuit 702 is provided to delete the output that does not exceed the predetermined threshold even if the delay detection output of the selected dog is not detected.
- the delay detection output from the delay detection circuit 205 is sent to the maximum value selection circuit 701 for each finger after the frequency offset correction, and the maximum value selection circuit 701 detects the delay detection for each finger.
- the delay detection output having the highest level is selected from the outputs, and the delay detection output is output to the threshold determination circuit 702.
- the threshold determination circuit 702 compares the delay detection output with the delay detection output selection threshold, and outputs only the delay detection output exceeding the threshold to the absolute value calculation circuit 205.
- the delay detection output after the frequency offset correction with a low reception level, that is, low reliability, is deleted, and only the delay detection output after the high reliability frequency offset correction is used. Since the phase rotation detection is performed by using this method, the detection accuracy can be improved. In the case of the present embodiment, the detection accuracy can be further improved as compared with the case of the fifth embodiment.
- FIG. 13 is a block diagram showing a configuration of a phase rotation detection device according to Embodiment 7 of the present invention. 13 that are the same as in FIG. 3 are assigned the same reference numerals as in FIG. 3, and detailed descriptions thereof are omitted.
- the phase rotation detection device shown in FIG. 13 includes an fD determination circuit 801 that performs fD determination according to communication quality (reception SIR).
- fD determination is performed using the output of the inter-finger averaging circuit 205 in consideration of the received SIR.
- the delay detection output reception S averaged by the finger-to-finger averaging circuit 205 is output to the: D determination circuit 801.
- the fD determination circuit 801 has a determination table shown in FIG. 14 in advance, and refers to the determination table shown in FIG. 14 according to the received SIR to determine a threshold (determination threshold 1, determination threshold Determine the threshold value 2). Then, the determination in fD detection is performed using this threshold value.
- FIG. 13 shows a case in which the fD determination is performed in three stages: high, medium, and low. Also, the judgment table may be provided for each differential detection interval.
- the phase rotation detection cycle may be made variable. Specifically, since the frequency offset and fD are unknown immediately after the start of communication, even if the error slightly increases, in a specific environment, the detection period is made shorter than usual and the frequency offset and fD are reduced. The convergence of is accelerated. As a result, communication quality can be improved early.
- the phase rotation detection accuracy is degraded due to poor communication quality.
- the correction may degrade the synchronization acquisition performance.
- This state occurs, for example, when wireless channel synchronization has not yet been established at the start of communication and transmission power control has not been sufficiently performed. Therefore, how to apply the phase rotation detection of the present invention in the case of such a low SIR or when synchronization is not achieved will be described using Embodiments 8 to 11 below.
- FIG. 15 is a block diagram showing a configuration of a base station provided with a phase rotation detecting apparatus according to Embodiment 8 of the present invention.
- the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the base station shown in FIG. 15 a case will be described where the number of paths to be combined is 2, but the present invention can also be applied to a case where the number of paths to be combined is 3 or more.
- the base station shown in FIG. 15 for simplicity of description, only one user sequence is shown. Therefore, the present invention can be similarly applied to a series of a plurality of users.
- FIG. 15 includes an SIR measuring device 1501 that measures the received SIR using the output of the correlator 105.
- the SIR measuring device 1501 outputs the measured reception SIR to the channel estimation circuit 1082 of the synchronous detection circuit 108.
- FIG. 16 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 8 of the present invention. In FIG. 16, the same parts as in FIG. 3 are denoted by the same reference numerals as in FIG.
- the phase rotation detection circuit shown in Fig. 16 switches the output of the frequency offset, J, and G detection results from the normalization circuit 250 and the output of the fD detection result from the finger-to-finger averaging circuit 210.
- a control circuit 1502 is provided. This switching control circuit 1502 outputs the received SIR, which is the SIR measurement result, from the SIR measuring device 1501. You.
- the result of the despreading process performed on the signal after the radio reception process is output to the channel estimation circuits 1072 and 1082 of the synchronous detection circuits 107 and 108, and to the SIR measurement device 1501 Is output.
- the 311 measuring device 1501 performs SIR measurement using the pilot portion of the received signal. Specifically, the received SIR is averaged in the phase rotation detection cycle.
- the averaged received SIR is output to the channel estimation circuits 1072 and 1082 of the synchronous detection circuits 107 and 108, respectively. Specifically, the averaged received SIR (SIR measurement result) is output to the switching control circuit 1502 of the channel estimation circuits 1072 and 1082.
- the switching control circuit 1502 performs a threshold decision on the averaged received SIR, and outputs the outputs (frequency offset detection result and fD detection result) of the normalization circuit 2058 and the inter-finger averaging circuit 2059 as they are. Is switched.
- the frequency offset detection result and fD detection obtained in the phase rotation detection detection cycle according to the present invention are used. Output the result as it is.
- the frequency offset detection result and the fD detection result obtained in the phase rotation detection detection cycle according to the present invention are used. Discard and set the frequency offset detection result and fD detection result to the default values.
- the default value for example, 0 Hz is used for the frequency offset, and the default value for medium speed, that is, the phase rotation detection is used for fD.
- the present embodiment when the communication quality is poor, the result of the phase rotation detection that is assumed to be inaccurate is not used, so that the correction based on the result of the low-accuracy phase rotation detection is performed. And prevent deterioration of reception characteristics. Can be.
- reception SIR reception SIR
- phase rotation detection of the present invention is applied in a state where the wireless channel is not synchronized between the base station and the communication terminal.
- FIG. 17 is a block diagram showing a configuration of a base station provided with a phase rotation detecting device according to Embodiment 9 of the present invention.
- the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the base station shown in FIG. 17 a case will be described in which the number of paths for RAKE combining is 2, but the present invention can also be applied to a case where the number of paths for RAKE combining is 3 or more.
- the present invention can be similarly applied to a series of a plurality of users.
- the 17 includes a synchronization determination circuit 1701 that determines whether or not synchronization has been achieved using the output of the demodulation circuit 110.
- the synchronization determination circuit 1701 outputs the synchronization determination result to the channel estimation circuits 1072 and 1082 of the synchronization detection circuits 107 and 108.
- FIG. 18 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 9 of the present invention.
- the same components as those in FIG. 3 are denoted by the same reference numerals as in FIG.
- the phase rotation detection circuit shown in Fig. 18 is a switching control circuit that switches the output of the frequency offset detection result from the normalization circuit 258 and the fD detection result from the finger averaging circuit 259. It is equipped with 502.
- the synchronization determination result is output from the synchronization determination circuit 1701 to the switching control circuit 1502.
- the outputs after synchronous detection by the synchronous detection circuit 107 and the synchronous detection circuit 108 are RAKE-combined, and the signal after RAKE-combination. Is output to the demodulation circuit 110.
- the demodulation circuit 110 performs demodulation processing on the signal after RAKE synthesis to obtain received data. This received data is output to the synchronization determination circuit 1701.
- the synchronization determination circuit 1 7 0 1, by performing the threshold determination with respect to bit error rate of the data DPCCH, such Pairodzuto portion, c and determines whether synchronization is established, channel estimation the synchronization determination result Circuit 1 0 7 2, 1 0 8 2 switching control Output to circuit 1 5 0 2.
- the switching control circuit 1502 outputs the output (frequency offset detection result and fD detection result) of the normalization circuit 205 and the finger-to-finger averaging circuit 205 according to the synchronization judgment result. Is switched.
- the frequency offset detection result and the fD detection result obtained in the detection cycle of the phase rotation detection according to the present invention are output as they are.
- the frequency offset detection result and the D detection result obtained in the detection cycle of the phase rotation detection according to the present invention are discarded, and the frequency offset detection is performed.
- Set the result and fD detection result to default values.
- the default value for example, the frequency offset uses 0 Hz, and fD uses the medium speed, that is, the default value of the phase rotation detection.
- the result of the phase rotation detection that is assumed to be inaccurate is not used, so that correction based on the inaccurate phase rotation detection result can be performed. This can be prevented from being performed, and deterioration of the reception characteristics can be prevented.
- phase rotation detection cycle may be shortened, for example, to 13 which is the normal phase rotation detection cycle.
- synchronization determination is performed using the bit error rate of the data of the DPCCH such as the pilot portion.
- another synchronization determination method is used. Is also good.
- FIG. 19 is a block diagram showing a configuration of a base station provided with a phase rotation detecting apparatus according to Embodiment 10 of the present invention.
- the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the base station shown in FIG. 19 the case where the number of paths to be RAKE combined is 2 will be described, but the present invention can also be applied to the case where the number of paths to be RAKE combined is 3 or more.
- the base station shown in FIG. 19 for simplicity of description, only a series of one user is shown. Therefore, the present invention can be similarly applied to a series of a plurality of users.
- the base station shown in FIG. 19 is synchronized with the SIR measuring device 1501 that measures the received SIR using the output of the correlator 105 and the output of the demodulation circuit 110. And a synchronization judgment circuit 1701 for judging whether or not the judgment is made.
- the SIR measuring device 1501 outputs the measured reception SIR to the channel estimation circuit 1082 of the synchronous detection circuit 108.
- the gorge period determination circuit 1701 outputs the synchronization determination result to the channel estimation circuits 1072 and 1082 of the synchronization detection circuits 107 and 108.
- FIG. 20 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 10 of the present invention. 20, the same components as those in FIG. 3 are denoted by the same reference numerals as those in FIG. 3, and detailed description thereof will be omitted.
- the phase rotation detection circuit shown in FIG. 20 includes a switching control circuit 1502 that switches the output of the frequency offset detection result from the normalization circuit 2058 and the output of the fD detection result from the inter-finger averaging circuit 2059.
- the received SIR which is the SIR measurement result
- the synchronization determination result is output from the synchronization determination circuit 1701.
- the result of the despreading process performed on the signal after the radio reception process is output to the channel estimation circuits 1072 and 1082 of the synchronous detection circuits 107 and 108, and is output to the SIR measuring device 1501. Is output.
- the 311 measuring device 1501 performs S measurement using the pilot portion of the received signal. Specifically, the received SIR is averaged in the phase rotation detection cycle.
- the averaged received SIR is output to the channel estimation circuits 1072 and 1082 of the synchronous detection circuits 107 and 108, respectively.
- the averaged received S IH (SIR measurement result) is output to switching control circuit 1502 of channel estimation circuits 1072 and 1082.
- the outputs after the synchronous detection by the synchronous detection circuit 107 and the synchronous detection circuit 108 are RAKE-combined, and the RAKE-combined signal is output to the demodulation circuit 110.
- Demodulation circuit 1 10 The demodulated signal is subjected to demodulation processing to obtain a received signal. This received data is output to the synchronization determination circuit 1701.
- threshold determination is performed on the bit error rate of the DPCCH, such as the pilot portion, to determine whether or not synchronization has been achieved.
- the switching control circuit 1502 performs a threshold decision on the averaged received SIR, and outputs the outputs of the normalization circuit 205 and the inter-finger averaging circuit 205 (frequency offset detection result and f (D detection result) is switched as is.
- the frequency offset detection result obtained in the detection cycle of the phase rotation detection according to the present invention when the averaged received SIR is higher than the threshold (the communication quality is good), the frequency offset detection result obtained in the detection cycle of the phase rotation detection according to the present invention and: f D Output the detection result as it is.
- the frequency offset detection result and the fD detection result obtained in the phase rotation detection detection cycle according to the present invention Is discarded, and the frequency offset detection result and the fD detection result are set to default values.
- the default value is, for example, 0 Hz for the frequency offset
- D is the medium speed, that is, the default for phase rotation detection. Use values.
- the switching control circuit 1502 outputs the outputs (frequency offset detection result and fD detection result) of the normalization circuit 250 and the inter-finger averaging circuit 205 according to the synchronization determination result. Switching whether or not to output as it is is performed.
- the frequency offset detection result and the fD detection result obtained in the detection cycle of the phase rotation detection according to the present invention are output as they are.
- the frequency offset detection result and the fD detection result obtained in the detection cycle of the phase rotation detection according to the present invention are discarded, and the frequency offset is discarded.
- Set the detection result and fD detection result to default values.
- the default value is, for example, the frequency offset.
- O uses OH z
- f D uses medium speed, that is, the default value of phase rotation detection o
- phase rotation detection result of the present invention is reflected using synchronization establishment and average SIR.
- phase rotation detection is always set to the default setting regardless of SIR.
- the reception characteristics are improved by phase rotation detection.Therefore, the communication terminal side requires a little transmission power before synchronization is established, but reduces transmission power after synchronization is established. be able to.
- phase rotation detection correction operation stops regardless of SIR.
- the phase rotation detection correction operation is stopped or the default setting is made.
- FIG. 21 and FIG. 22 are diagrams showing the detection timing change of the phase rotation detection according to the present invention.
- phase rotation detection according to the present invention is started. (Change of detection timing in Fig. 21).
- the average SIR is measured by the SIR measuring device 1501, and the switching control circuit 1502 compares the average SIR with the SIR threshold.
- the state where the average SIR is lower than the SIR threshold is shifted to a state where the average SIR exceeds the SIR threshold. That is, at the end of the detection cycle n, the average SIR exceeds the SIR threshold. For this reason, the switching control means 1502 outputs the phase rotation detection result in the detection cycle n.
- the switching control means 1502 outputs the phase rotation detection result.
- the phase rotation detection according to the present invention is started (the detection timing change in FIG. 22). ).
- the switching control circuit 1502 compares the average S11 with the 3IR threshold.
- the state where the average S1: 3 ⁇ 4 is lower than the 3 IR threshold continues. That is, the average SIR is lower than the SIR threshold even at the end of the detection cycle n. Therefore, the switching control unit 1502 discards the phase rotation detection result in the detection cycle n, performs default setting, and outputs the default value. Similarly, for the detection cycle n + 1 in FIG. 22, the switching control means 1502 performs default setting and outputs the default value.
- the result of the phase rotation detection that is assumed to be inaccurate is not used, so that the correction based on the result of the low-accuracy phase rotation detection is performed. If the synchronization is not achieved, the result of the phase rotation detection assumed to be inaccurate is not used, so that it is possible to prevent the correction based on the inaccurate phase rotation detection result from being performed. As a result, it is possible to prevent reception characteristics from deteriorating.
- the determination may be made using parameters other than the received SIR as the communication quality.
- phase rotation detection cycle may be shortened, for example, 1 Z 3 which is the normal phase rotation detection cycle.
- synchronization determination is performed using the bit error rate of DPCCH data such as a pilot portion, but other synchronization determination methods may be used in the present invention.
- FIG. 23 is a block diagram showing a configuration of a phase rotation detection circuit according to Embodiment 11 of the present invention.
- the same parts as those in FIG. 20 are denoted by the same reference numerals as those in FIG. 20, and detailed description thereof will be omitted.
- the phase rotation detection circuit shown in Fig. 23 is a switching control circuit that switches the output of the frequency offset detection result from the normalization circuit 258 and the output of the fD detection result from the finger averaging circuit 259. And a pre-detection value holding unit 2301 that holds the phase rotation detection result detected in the previous detection cycle.
- the switching control circuit 1502 the received SIR that is the SIR measurement result is output from the SIR measuring device 1501, and the synchronization determination result is output from the synchronization determination circuit 1701.
- the result of the despreading processing performed on the signal after the radio reception processing is performed by the channel estimation circuits 107, 108 of the synchronous detection circuits 107, 108. 2 and output to the SIR measuring device 1501.
- 3111 measuring device 1501 performs SIR measurement using the pilot portion of the received signal. Specifically, the received S is averaged in the phase rotation detection cycle.
- the averaged received SIR is output to the channel estimation circuits 1072 and 1082 of the synchronous detection circuits 107 and 108, respectively. Specifically, the averaged received SIR (SIR measurement result) is output to the switching control circuit 1502 of the channel estimation circuits 1072 and 1082.
- the outputs after the synchronous detection by the synchronous detection circuits 107 and 108 are RAKE-combined, and the RAKE-combined signal is output to the demodulation circuit 110.
- the demodulation circuit 110 performs demodulation processing on the signal after RAKE combination to obtain received data. This received data is output to the synchronization determination circuit 1701.
- the synchronization determination circuit 1701 performs a threshold determination on the bit error rate of the data of the DP CCH, such as the pilot portion, to determine whether synchronization has been achieved. Then, the synchronization determination result is output to the switching control circuit 1 502 of the channel estimation circuits 1072 and 1082.
- the switching control circuit 1502 performs a threshold determination on the averaged received SIR, and outputs the output (frequency offset detection result and: D detection result) of the normalization circuit 2058 and the inter-finger averaging circuit 2059 as they are. Is switched.
- the frequency offset detection result obtained in the detection cycle of the phase rotation detection according to the present invention when the averaged received SIR is higher than the threshold (the communication quality is good), the frequency offset detection result obtained in the detection cycle of the phase rotation detection according to the present invention and: fD Output the detection result as it is.
- the frequency offset detection result and the fD detection result obtained in the phase rotation detection detection cycle according to the present invention when the averaged received SIR is lower than the threshold (the communication quality is poor), the frequency offset detection result and the fD detection result obtained in the phase rotation detection detection cycle according to the present invention. Is discarded, and the frequency offset detection result and fD detection result are set to default values.
- the default value is 0 Hz for frequency offset
- fD is medium
- the speed that is, the default value of the phase rotation detection is used.
- the switching control circuit 1502 outputs the outputs (frequency offset detection result and fD detection result) of the normalization circuit 205 and the finger-to-finger averaging circuit 205 according to the synchronization determination result. Switching whether or not to output as it is is performed.
- the frequency offset detection result and the fD detection result obtained in the detection cycle of the phase rotation detection according to the present invention are output as they are.
- the frequency offset detection result and the D detection result obtained in the detection cycle of the phase rotation detection according to the present invention are discarded, and the frequency offset detection is performed.
- Result and: f Set the detection result to the default value.
- the default value for example, 0 Hz is used for the frequency offset, and the medium speed, that is, the default value of the phase rotation detection is used for fD.
- the frequency offset detection result and the fD detection result obtained by the phase rotation detection of the present invention are output as they are.
- the result of the frequency offset detection and the result of the eD detection are stored in the previous detection value storage unit 2301. If the reception quality deteriorates during the detection cycle (in the tenth embodiment, when the average SIR falls below the threshold), the frequency offset detection result and the fD detection result are used as default settings. Set to.
- the switching control circuit 1502 sets the pre-detection value holding unit 2301 without setting the default when the reception quality is deteriorated. Is controlled to output the frequency offset detection result and fD detection result of the previous detection cycle held in.
- the phase rotation detection result in that detection period is discarded without being used for correction, and the detection result in the previous detection period is used (the current detection result and the previous one). Make the detection result the same). In this case, the accuracy is low even if the detection result of the detection cycle that is too long is used. It is desirable to use the detection result in the outgoing cycle. Furthermore, if the reception quality is poor even in the next detection cycle, the default value of the phase rotation detection value is used.
- the previous detection result can be obtained without performing correction using the detection result with respect to the deterioration of the detection accuracy in the state where synchronization is not established or the reception quality is poor. By using the control, the influence of the detection error can be reduced and the deterioration of the reception characteristics can be prevented.
- FIG. 24 is a flowchart for explaining switching control of phase rotation detection according to Embodiment 11 of the present invention.
- step (hereinafter abbreviated as ST) 1 the switching control circuit 1502 is set to the default (frequency offset 0 Hz,: D judgment "medium” (WMSA (Weighted Multi-Slot Averaging) 3 slots). Whether synchronization is established or not is determined by the synchronization determination circuit 1701. If synchronization is established, predetermined processing such as delay detection is performed (ST4), and if synchronization is not established, phase rotation is detected. Instruct the circuit 205 to reset the detection cycle (ST 3), and maintain the state of the default setting of the switching control circuit 1502.
- WMSA Weighted Multi-Slot Averaging
- ST5 After the synchronization is established, it is determined whether or not it is a detection cycle, and a phase rotation detection process of 60 frames is performed. That is, if the detection period is after the synchronization is established, the normal detection is continued for every 60 frames (ST6).
- the average SIR is compared with the threshold value even when the reception quality is degraded during normal detection (ST7). If the average SIR exceeds the threshold, it is determined that the reception quality is good, and the detected value is used (ST10).
- the previous average SIR is compared with the threshold (ST8). If the previous average SIR exceeds the threshold value, it is determined that the reception quality is good, and the previous detection result held in the previous detection value holding means 2301 is used (ST11). On the other hand, when the previous average SIR is equal to or less than the threshold, the default setting is performed (ST9). That is, if the average SIR is below the threshold, The detection result of the detection cycle n is discarded, and the result of the previous detection cycle n ⁇ 1 is used in the next detection cycle n + 1. Furthermore, if the average SIR remains lower than the threshold, the default setting is applied from the next detection cycle n + 2. After returning to the default setting, the normal detection operation (ST6) is performed.
- the detection result is used if the average SIR exceeds the threshold value at each time, and the default setting is used if the average SIR is equal to or less than the threshold value.
- the number of frames in the detection cycle is not limited to the present embodiment, and may be other than 60 frames. Further, the control using either the previous detection result or the default value is not limited to the present embodiment.
- the phase rotation detection according to the present invention is performed, and when synchronization has not been established, the previous detection value is used without using the phase rotation detection result.
- the case where the phase rotation is used has been described.
- the control of not performing the phase rotation detection of the present invention may be performed.
- FIG. 25 is a block diagram showing another example of the configuration of the phase rotation detection circuit according to Embodiment 11 of the present invention.
- the same parts as those in FIG. 23 are denoted by the same reference numerals as those in FIG. 23, and detailed description thereof will be omitted.
- the phase rotation detection circuit shown in FIG. 25 includes a switching control circuit 2501 for controlling start / stop of phase rotation detection according to the present invention.
- the synchronization determination result which is the output of the synchronization determination circuit 1701, is input to the switching control circuit 2501.
- the switching control circuit 2501 controls the start / stop of the phase rotation detection of the present invention based on the synchronization determination result. Further, the switching control circuit 2501 outputs a signal indicating the start / stop of the phase rotation detection to the switching control circuit 1502 which outputs the frequency offset detection result and the fD detection result.
- the switching control when the synchronization determination result indicates that synchronization has not been established, the switching control is performed so that the phase rotation detection according to the present invention is stopped, and a signal indicating the stop is output to the switching control circuit. Output to 1502.
- the switching control circuit 1502 holds the previously detected value holding section 2301 in accordance with the signal indicating that the operation is stopped. Controls whether to output the detection result of the previous detection cycle or to output the default value by the default setting.
- the control for outputting the detection result of the previous detection cycle or outputting the default value is the same as the method described above.
- the switching control is performed so that the phase rotation detection according to the present invention starts, and a signal indicating the start is output to the switching control circuit 1502.
- the switching control circuit 1502 detects the frequency offset detection result output from the normalization circuit 250 and the fD detection output from the finger-to-finger averaging circuit 205 according to the signal indicating the start. Output the result.
- the synchronization is not established in this way, by performing the control that does not perform the phase rotation detection of the present invention, the correction based on the inaccurate phase rotation detection result is performed, thereby preventing the reception characteristics from deteriorating. In addition, the amount of signal processing related to reception can be reduced, and the power consumption can be reduced.
- Embodiments 1 to 11 described above can be implemented in appropriate combinations.
- the present invention is not limited to the above-described embodiment, but can be implemented with various modifications.
- Embodiment 1 above the case where the phase rotation detection result obtained by the phase rotation detection according to the present invention is used for channel estimation has been described, but the present invention relates to the present invention.
- the result of the phase rotation detection obtained by the phase rotation detection may be used for other signal processing, for example, optimization of the delay profile averaging number.
- the phase rotation detection device includes: a despreading unit that performs despreading processing on a received signal to obtain a despread signal; a delay detection unit that performs delay detection using the despread signal; A frequency offset detection unit that detects a phase rotation due to a frequency offset by performing vector synthesis on the obtained differential detection outputs is adopted.
- the phase rotation detection device includes: a despreading unit that performs despreading processing on a received signal to obtain a despread signal; a delay detection unit that performs delay detection using the despread signal; By performing vector synthesis on the obtained delayed detection output, And a maximum Doppler frequency detection unit for detecting a phase rotation due to one large Doppler frequency.
- the phase rotation detection device includes: a despreading unit that performs despreading processing on a received signal to obtain a despread signal; a delay detection unit that performs delay detection using the despread signal; A frequency offset detection unit that detects a phase rotation due to a frequency offset by vector-synthesizing the obtained differential detection output, and vector-synthesizes the delay detection output corrected using the phase rotation due to the frequency offset.
- a maximum Doppler frequency detecting unit for detecting a phase rotation based on the maximum Doppler frequency is adopted.
- the phase rotation detection device of the present invention in the above configuration, employs a configuration in which the maximum Doppler frequency detector performs vector synthesis of the absolute value of the quadrature component of the delayed detection output corrected using the phase rotation due to the frequency offset.
- the phase rotation detection device of the present invention employs, in the above configuration, a configuration in which the absolute values of the orthogonal components are vector-synthesized only for the highly reliable differential detection output.
- the phase rotation detection device of the present invention employs a configuration in the above configuration, wherein the delay detection unit has a plurality of delay detection units having different measurement periods.
- the delay detection unit may be configured to output the delay detection output from the plurality of delay detection units based on a table indicating a relationship between the phase rotation amount and the delay detection output value.
- a configuration for selecting an optimal differential detection output is employed.
- the delay detection unit may A configuration is employed in which the operations of the plurality of delay detection units are switched based on the amount of phase rotation in a specific delay detection unit among the delay detection units.
- the phase rotation detection device of the present invention employs a configuration in which, in the above-described configuration, a threshold value is determined for the delayed detection output, and the phase rotation is detected using only a highly reliable output.
- the phase rotation detection device of the present invention employs a configuration in which, in the above-described configuration, the threshold detection is performed on the delay detection output after the frequency offset correction, and the phase rotation is detected using only the highly reliable output.
- the phase rotation detection device of the present invention in the above-described configuration, further includes a selection unit that selects the maximum output from the frequency offset-corrected delay detection outputs determined in the phase rotation detection performed between the fingers.
- the maximum output is used to detect the phase rotation at the maximum Doppler frequency.
- the phase rotation detection device of the present invention employs a configuration in the above configuration, further comprising a threshold value determination unit that performs a threshold value determination on the maximum output.
- the phase rotation detection device of the present invention in the above configuration, employs a configuration in which the maximum Doppler frequency detection unit detects a phase rotation based on the maximum Doppler frequency with reference to a determination table that associates communication quality with the maximum Doppler frequency.
- the reception detection level is low, that is, the delay detection output with low reliability is deleted, and the phase rotation detection is performed using only the delay detection output with high reliability, the detection accuracy can be improved. it can.
- a wireless base station device includes the above-described phase rotation detecting device. Thereby, channel estimation accuracy is improved and reception performance is improved.
- a radio base station apparatus includes: a phase rotation detection device that performs phase rotation detection on a reception signal; a reception quality measurement unit that measures reception quality using the reception signal; A first switching control unit that switches whether to output a result detected by the phase rotation detection device according to the reception quality, wherein the phase rotation detection device performs despreading processing on the received signal.
- a de-spreading unit that obtains a de-spread signal by performing a delay detection using the de-spread signal; and a vector synthesis of the delay detection output obtained by the delay detection, thereby performing phase rotation by frequency offset.
- a frequency offset detecting unit that detects the phase shift by the frequency offset, and performs a vector synthesis of the delayed detection output corrected using the phase rotation by the frequency offset to obtain a maximum Doppler one frequency detecting unit that detects a phase rotation by one frequency.
- a radio base station apparatus includes a phase rotation detection device that performs phase rotation detection on a received signal, a demodulation unit that performs demodulation processing on the received signal, and a synchronization determination using an output of the demodulation unit.
- a first switching control unit that switches whether to output a result detected by the phase rotation detection device according to a result of the synchronization determination, and the phase rotation detection device includes: A despreading unit that performs despreading processing on a received signal to obtain a despread signal; a delay detection unit that performs delay detection using the despread signal; and a delay detection output obtained by the delay detection.
- a frequency offset detecting unit that detects a phase rotation due to a frequency offset, and a vector synthesis of the delayed detection output corrected using the phase rotation due to the frequency offset.
- a maximum Doppler frequency detection unit for detecting phase rotation based on the maximum Doppler frequency.
- the radio base station apparatus performs phase rotation detection on a received signal.
- a detection device a reception quality measurement unit that measures reception quality using the reception signal, a demodulation unit that performs demodulation processing on the reception signal, and a synchronization determination that performs synchronization determination using an output of the demodulation unit.
- a first switching control unit that switches whether to output a result detected by the phase rotation detecting device according to the reception quality and the result of the synchronization determination, and the phase rotation detecting device includes: A despreading unit that performs despreading processing on a signal to obtain a despread signal; a delay detection unit that performs delay detection using the despread signal; and a vector that outputs a delay detection output obtained by the delay detection.
- a frequency offset detecting unit that detects a phase rotation caused by a frequency offset, and a vector synthesis of the delayed detection output corrected using the phase rotation caused by the frequency offset.
- a maximum Doppler frequency detection unit that detects a phase rotation based on the maximum Doppler frequency.
- the first switching control unit may include a receiving port
- a configuration is adopted in which control is performed so that the result detected by the phase rotation detection device is output when the speech quality is good, and the default value is output when the reception quality is poor.
- the first switching control unit outputs a result detected by the phase rotation detection device when synchronization is established, and outputs the result when the synchronization is not established.
- a configuration is used in which control is performed so as to output a default value.
- the wireless base station apparatus in the above configuration, employs a configuration in which the phase rotation detection device makes the phase rotation detection cycle shorter than usual in a specific environment. This makes it possible to quickly establish synchronization from a state where synchronization has not been established or has been lost.
- the phase rotation detection device in the above configuration, includes a holding unit that holds a previous phase rotation detection result, and the first switching control unit uses the holding unit instead of a predetermined value. The control is performed so as to output the previous phase rotation detection result held in.
- control is performed using the previous detection result without performing correction using the detection result for the deterioration of the detection accuracy in a state where synchronization is not established or reception quality is poor. This makes it possible to reduce the influence of the detection error and prevent the reception characteristics from deteriorating.
- the wireless base station apparatus of the present invention employs a configuration in the above-described configuration that includes a second switching control unit that controls start / stop of phase rotation detection.
- the correction based on the inaccurate phase rotation detection result is performed, so that it is possible to prevent reception characteristics from deteriorating, and to reduce the amount of signal processing related to reception and reduce power consumption. can do.
- the phase rotation detection method of the present invention includes: a despreading step of performing despreading processing on a received signal to obtain a despread signal; a delay detection step of performing delay detection using the despread signal; A frequency offset detecting step of detecting a phase rotation due to a frequency offset by vector-combining the differential detection output obtained by the above, and a vector combining of the differential detection output corrected using the phase rotation due to the frequency offset.
- the channel estimation accuracy can be improved.
- the delay detection output is vector-synthesized by performing vector synthesis. Considering reliability and detecting the maximum Doppler frequency using the delayed detection output after frequency offset correction, high detection accuracy can be realized.
- the present specification is based on Japanese Patent Application No. 2000-267532 filed on Sep. 4, 2000 and Japanese Patent Application No. 2001-45710 filed on Feb. 21, 2000. These are all included here. Industrial applicability
- the present invention can be applied to a digital wireless communication system, particularly to a phase rotation detecting device used in a CDMA (code division multiple access) system and a wireless base station device provided with the same.
- CDMA code division multiple access
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/129,146 US20040013169A1 (en) | 2000-09-04 | 2001-09-03 | Phase rotation detection apparatus and radio base station apparatus provided therewith |
EP01961299A EP1233535A4 (en) | 2000-09-04 | 2001-09-03 | DEVICE FOR MEASURING PHASE ROTATION AND RADIO BASE DEVICE WITH THE SAME |
KR1020027005721A KR20020043261A (ko) | 2000-09-04 | 2001-09-03 | 위상 회전 검출 장치 및 그것을 구비한 무선 기지국 장치,및 위상 회전 검출 방법 |
AU2001282598A AU2001282598A1 (en) | 2000-09-04 | 2001-09-03 | Phase rotation measuring device and radio base station device having the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-267532 | 2000-09-04 | ||
JP2000267532 | 2000-09-04 | ||
JP2001045710A JP3497480B2 (ja) | 2000-09-04 | 2001-02-21 | 位相回転検出装置及びそれを備えた無線基地局装置 |
JP2001-45710 | 2001-02-21 |
Publications (1)
Publication Number | Publication Date |
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WO2002021713A1 true WO2002021713A1 (fr) | 2002-03-14 |
Family
ID=26599199
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2001/007586 WO2002021713A1 (fr) | 2000-09-04 | 2001-09-03 | Dispositif de mesure de rotation de phases et dispositif de station de base radio comprenant celui-ci |
Country Status (7)
Country | Link |
---|---|
US (1) | US20040013169A1 (ja) |
EP (1) | EP1233535A4 (ja) |
JP (1) | JP3497480B2 (ja) |
KR (1) | KR20020043261A (ja) |
CN (1) | CN1198404C (ja) |
AU (1) | AU2001282598A1 (ja) |
WO (1) | WO2002021713A1 (ja) |
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KR100575710B1 (ko) * | 2002-07-20 | 2006-05-03 | 엘지전자 주식회사 | 업링크 동기 검출방법 |
JP3877158B2 (ja) * | 2002-10-31 | 2007-02-07 | ソニー・エリクソン・モバイルコミュニケーションズ株式会社 | 周波数偏移検出回路及び周波数偏移検出方法、携帯通信端末 |
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KR100902248B1 (ko) * | 2007-12-13 | 2009-06-11 | 한국전자통신연구원 | 무선 통신 시스템에서 잔류 위상 측정 장치 및 잔류 위상보상 장치 |
CN101814931B (zh) * | 2009-02-19 | 2014-07-02 | 中兴通讯股份有限公司 | Td-scdma系统中多普勒频移估计和补偿的方法 |
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Also Published As
Publication number | Publication date |
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CN1198404C (zh) | 2005-04-20 |
AU2001282598A1 (en) | 2002-03-22 |
US20040013169A1 (en) | 2004-01-22 |
KR20020043261A (ko) | 2002-06-08 |
JP3497480B2 (ja) | 2004-02-16 |
EP1233535A4 (en) | 2003-01-02 |
CN1389024A (zh) | 2003-01-01 |
EP1233535A1 (en) | 2002-08-21 |
JP2002152088A (ja) | 2002-05-24 |
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