WO2001052324A1 - Puce comportant une protection sur tous les cotes d'elements de circuit sensibles, par l'intermediaire de blindages, au moyen d'une puce auxiliaire - Google Patents

Puce comportant une protection sur tous les cotes d'elements de circuit sensibles, par l'intermediaire de blindages, au moyen d'une puce auxiliaire Download PDF

Info

Publication number
WO2001052324A1
WO2001052324A1 PCT/DE2000/004483 DE0004483W WO0152324A1 WO 2001052324 A1 WO2001052324 A1 WO 2001052324A1 DE 0004483 W DE0004483 W DE 0004483W WO 0152324 A1 WO0152324 A1 WO 0152324A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
chip
shielding
arrangement
electronic circuit
Prior art date
Application number
PCT/DE2000/004483
Other languages
German (de)
English (en)
Inventor
Andreas Kux
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001052324A1 publication Critical patent/WO2001052324A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Chip with all-round protection of sensitive circuit parts by shields using an auxiliary chip Chip with all-round protection of sensitive circuit parts by shields using an auxiliary chip
  • the invention relates to a vertically integrated electronic circuit arrangement according to the preamble of claim 1.
  • microelectronics it is becoming increasingly necessary to protect the data stored in integrated circuits or processed there from access by unauthorized persons. To prevent this from happening, it is already known to provide the surface with a shield. In this way, similar to a Faraday cage, the emission of electromagnetic radiation, which indicates the data stored or processed in the integrated circuit, is prevented.
  • the invention is therefore based on the object of providing an integrated electronic circuit arrangement which can be shielded as completely as possible using simple means.
  • connection pads for connections to the outside on the second substrate are located on the larger than the second substrate and can be produced from a less expensive material if only the second electrical shielding arrangement is applied to it. The same applies if line arrangements are still applied to the second substrate.
  • This arrangement can be used not only for the use of the semiconductor technology that is currently mostly used, but also for the polymer technology that is currently in the development stage.
  • These are organic structures that consist of the thin film and are suitable for forming comparable elements such as transistors, diodes, resistors, capacitors, etc.
  • An electrically conductive shielding arrangement 3 is applied to the first substrate 1.
  • An integrated circuit which is not shown, is formed on the surface of the substrate 1 for the shielding arrangement 3.
  • a second electrical shielding arrangement 4 is formed on a second substrate 2, on which the rear side of the first substrate 1 is arranged.
  • the first and the second electrical shielding arrangement are electrically conductively connected to one another via a via 6.
  • the second substrate 2 is larger than the first substrate 1 in at least one direction.
  • a connection contact 5, a so-called pad, is provided on the projecting surface of the second substrate 2. This is connected to the integrated circuit in the first substrate 1 via a line arrangement, not shown, via further vertical plated-through holes, not shown.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un ensemble circuit électronique intégré verticalement comportant au moins un premier substrat (1) sur lequel est intégré un circuit électronique. Au moins un blindage électronique (3) est placé sur une surface dudit substrat. Cet ensemble circuit comporte également un deuxième substrat (2) sur lequel est placé le premier substrat (1). Un deuxième blindage électrique (4) est placé entre le premier et le deuxième substrat.
PCT/DE2000/004483 2000-01-13 2000-12-15 Puce comportant une protection sur tous les cotes d'elements de circuit sensibles, par l'intermediaire de blindages, au moyen d'une puce auxiliaire WO2001052324A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10003112.9 2000-01-13
DE2000103112 DE10003112C1 (de) 2000-01-13 2000-01-13 Chip mit allseitigem Schutz sensitiver Schaltungsteile vor Zugriff durch Nichtberechtigte durch Abschirmanordnungen (Shields) unter Verwendung eines Hilfschips

Publications (1)

Publication Number Publication Date
WO2001052324A1 true WO2001052324A1 (fr) 2001-07-19

Family

ID=7628662

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/004483 WO2001052324A1 (fr) 2000-01-13 2000-12-15 Puce comportant une protection sur tous les cotes d'elements de circuit sensibles, par l'intermediaire de blindages, au moyen d'une puce auxiliaire

Country Status (2)

Country Link
DE (1) DE10003112C1 (fr)
WO (1) WO2001052324A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2232412B1 (fr) * 2007-08-02 2019-03-06 Nxp B.V. Dispositif semi-conducteur inviolable et ses procédés de fabrication

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10105725B4 (de) 2001-02-08 2008-11-13 Infineon Technologies Ag Halbleiterchip mit einem Substrat, einer integrierten Schaltung und einer Abschirmvorrichtung
DE10251317B4 (de) * 2001-12-04 2006-06-14 Infineon Technologies Ag Halbleiterchip
DE10337256A1 (de) * 2002-11-21 2004-06-09 Giesecke & Devrient Gmbh Integrierte Schaltkreisanordnung und Verfahren zur Herstellung derselben

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514785A (en) * 1981-09-11 1985-04-30 U.S. Philips Corporation Method of manufacturing an identification card and an identification manufactured, by this method
US4563575A (en) * 1981-05-08 1986-01-07 Gao Gesellschaft Fur Automation Und Organisation Mbh Identification card having an embedded IC module
FR2609820A1 (fr) * 1987-01-20 1988-07-22 Thomson Semiconducteurs Dispositif de protection electromagnetique et electrostatique pour cartes electroniques et procede de realisation de ce dispositif
EP0547877A2 (fr) * 1991-12-16 1993-06-23 Mitsubishi Denki Kabushiki Kaisha Module semi-conducteur de puissance
DE19716102A1 (de) * 1997-04-17 1998-10-22 Siemens Ag Integrierte Schaltungsanordnung mit mehreren Bauelementen und Verfahren zu deren Herstellung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4242097C2 (de) * 1992-12-14 2001-03-01 Bosch Gmbh Robert Anordnung zum elektromagnetischen Verträglichkeits(EMV)-Schutz von Hybridbauelementen

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4563575A (en) * 1981-05-08 1986-01-07 Gao Gesellschaft Fur Automation Und Organisation Mbh Identification card having an embedded IC module
US4514785A (en) * 1981-09-11 1985-04-30 U.S. Philips Corporation Method of manufacturing an identification card and an identification manufactured, by this method
FR2609820A1 (fr) * 1987-01-20 1988-07-22 Thomson Semiconducteurs Dispositif de protection electromagnetique et electrostatique pour cartes electroniques et procede de realisation de ce dispositif
EP0547877A2 (fr) * 1991-12-16 1993-06-23 Mitsubishi Denki Kabushiki Kaisha Module semi-conducteur de puissance
DE19716102A1 (de) * 1997-04-17 1998-10-22 Siemens Ag Integrierte Schaltungsanordnung mit mehreren Bauelementen und Verfahren zu deren Herstellung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2232412B1 (fr) * 2007-08-02 2019-03-06 Nxp B.V. Dispositif semi-conducteur inviolable et ses procédés de fabrication

Also Published As

Publication number Publication date
DE10003112C1 (de) 2001-07-26

Similar Documents

Publication Publication Date Title
EP0369112B1 (fr) Adaptateur pour appareil électronique de contrôle des circuits imprimés et équipement semblable
DE69016441T2 (de) Mehrschichtleiterplatte, welche hochfrequenzinterferenzen von hochfrequenzsignalen unterdrückt.
DE60314353T2 (de) Leiterplatte und Methode um eine Leiterplatte an einem elektrisch leitenden Gehäuse anzubringen
DE68911958T2 (de) Wählbare Erdungsvorrichtung für elektronische Anlagen.
DE68929486T2 (de) Integrierte Halbleiterschaltungsanordnung mit Leiterschichten
DE3610821C2 (fr)
DE19809509A1 (de) Halbleitervorrichtung
DE19654404A1 (de) Adaptationsvorrichtung zum elektrischen Test von Leiterplatten
DE19911731A1 (de) Gedruckte Leiterplatte
DE10320579A1 (de) Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben
DE102009049848A1 (de) Elektrische Verbindungsvorrichtung
DE4315082C2 (de) Verbinderanordnung zum Testen eines integrierten Schaltungsbausteins
DE102005013270A1 (de) Schaltungsplatine zum Verbinden einer integrierten Schaltung mit einem Träger und einem IC-BGA-Gehäuse, das dieselbe verwendet
WO2001052324A1 (fr) Puce comportant une protection sur tous les cotes d'elements de circuit sensibles, par l'intermediaire de blindages, au moyen d'une puce auxiliaire
DE10105725B4 (de) Halbleiterchip mit einem Substrat, einer integrierten Schaltung und einer Abschirmvorrichtung
EP0875767B1 (fr) Appareil et procédé pour tester des circuits imprimés non pourvus de composants
DE19816794A1 (de) Leiterplattenverbund
WO2024061851A1 (fr) Procédé et dispositif permettant la mise en contact électrique de composants électroniques
EP0221351A1 (fr) Circuit intégré comprenant un élément électroconducteur plan
DE69836606T2 (de) Sicherheitsmerkmal für gedruckte Leiterplatten
DE3810486C2 (fr)
DE10026756C2 (de) Elektrische Schaltung
EP1116420B1 (fr) Plaquette a circuit imprime destinee a etre utilisee pour tester des composants electriques
DE4231180A1 (de) Verfahren zur Erzeugung von Justierstrukturen für Leiterplatten und Justierstruktur
DE102004029200B4 (de) Verfahren zur Herstellung einer elektronischen Schaltung sowie ein Substrat für eine elektronische Schaltung

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): BR CN IN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP