WO2001052324A1 - Chip with all-round protection of sensitive circuit components using shielding by means of an auxiliary chip - Google Patents

Chip with all-round protection of sensitive circuit components using shielding by means of an auxiliary chip Download PDF

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Publication number
WO2001052324A1
WO2001052324A1 PCT/DE2000/004483 DE0004483W WO0152324A1 WO 2001052324 A1 WO2001052324 A1 WO 2001052324A1 DE 0004483 W DE0004483 W DE 0004483W WO 0152324 A1 WO0152324 A1 WO 0152324A1
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WO
WIPO (PCT)
Prior art keywords
substrate
chip
shielding
arrangement
electronic circuit
Prior art date
Application number
PCT/DE2000/004483
Other languages
German (de)
French (fr)
Inventor
Andreas Kux
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001052324A1 publication Critical patent/WO2001052324A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Chip with all-round protection of sensitive circuit parts by shields using an auxiliary chip Chip with all-round protection of sensitive circuit parts by shields using an auxiliary chip
  • the invention relates to a vertically integrated electronic circuit arrangement according to the preamble of claim 1.
  • microelectronics it is becoming increasingly necessary to protect the data stored in integrated circuits or processed there from access by unauthorized persons. To prevent this from happening, it is already known to provide the surface with a shield. In this way, similar to a Faraday cage, the emission of electromagnetic radiation, which indicates the data stored or processed in the integrated circuit, is prevented.
  • the invention is therefore based on the object of providing an integrated electronic circuit arrangement which can be shielded as completely as possible using simple means.
  • connection pads for connections to the outside on the second substrate are located on the larger than the second substrate and can be produced from a less expensive material if only the second electrical shielding arrangement is applied to it. The same applies if line arrangements are still applied to the second substrate.
  • This arrangement can be used not only for the use of the semiconductor technology that is currently mostly used, but also for the polymer technology that is currently in the development stage.
  • These are organic structures that consist of the thin film and are suitable for forming comparable elements such as transistors, diodes, resistors, capacitors, etc.
  • An electrically conductive shielding arrangement 3 is applied to the first substrate 1.
  • An integrated circuit which is not shown, is formed on the surface of the substrate 1 for the shielding arrangement 3.
  • a second electrical shielding arrangement 4 is formed on a second substrate 2, on which the rear side of the first substrate 1 is arranged.
  • the first and the second electrical shielding arrangement are electrically conductively connected to one another via a via 6.
  • the second substrate 2 is larger than the first substrate 1 in at least one direction.
  • a connection contact 5, a so-called pad, is provided on the projecting surface of the second substrate 2. This is connected to the integrated circuit in the first substrate 1 via a line arrangement, not shown, via further vertical plated-through holes, not shown.

Abstract

A vertically integrated electronic circuit arrangement is provided with at least one first substrate (1), upon which an electronic circuit is arranged in an integrated manner. On the one surface thereof at least one first electrical shielding arrangement (3) is mounted. A second substrate (2) is provided, upon which the first substrate (1) is arranged, whereby a second electrical screening arrangement (4) is arranged between the first and the second substrate.

Description

Beschreibungdescription
Chip mit allseitigem Schutz sensitiver Schaltungsteile durch Shields unter Verwendung eines HilfschipsChip with all-round protection of sensitive circuit parts by shields using an auxiliary chip
Die Erfindung betrifft eine vertikal integrierte elektronische Schaltungsanordnung gemäß der Gattungsbezeichnung des Patentanspruchs 1. In der Mikroelektronik wird es zunehmend notwendig, die in integrierten Schaltungen gespeicherten oder auch dort verarbeiteten Daten vor dem Zugriff durch Nichtberechtigte zu schützen. Um zu verhindern, daß dies geschieht ist bereits bekannt, die Oberfläche mit einer Abschirmung zu versehen. Hiermit wird, ähnlich wie bei einem Faraday-Käfig, das Aussenden von elektromagnetischen Strahlung, die auf die in der integrierten Schaltung gespeicherten bzw. verarbeiteten Daten innerhalb der Rückschluß geben, zu verhindern.The invention relates to a vertically integrated electronic circuit arrangement according to the preamble of claim 1. In microelectronics, it is becoming increasingly necessary to protect the data stored in integrated circuits or processed there from access by unauthorized persons. To prevent this from happening, it is already known to provide the surface with a shield. In this way, similar to a Faraday cage, the emission of electromagnetic radiation, which indicates the data stored or processed in the integrated circuit, is prevented.
Einschlägigen Kreisen gelingt es jedoch zunehmend die über die Rückseite von Halbleiterchips abgestrahlte elektro agne- tische Strahlung zu erfassen und auszuwerten. Um dies zu verhindern, ist es notwendig, auch die Rückseite zu schützen, d. h. einen Faraday-Käfig möglichst umfassend aufzubauen. Hierzu wäre es notwendig, die Rückseite eines integrierten Schaltkreises bzw. sogenannte Chips ebenfalls mit einer abschirmen- den elektrisch leitenden Struktur zu versehen. Damit sich ein sogenannter Faraday-Käfig bildet, müßten die abschirmenden Strukturen beider Seiten miteinander elektrisch verbunden werden.Relevant circles, however, are increasingly succeeding in detecting and evaluating the electromagnetic radiation emitted by the back of semiconductor chips. To prevent this, it is also necessary to protect the back, i.e. H. to build a Faraday cage as comprehensively as possible. To do this, it would be necessary to provide the back of an integrated circuit or so-called chips with a shielding, electrically conductive structure. In order for a so-called Faraday cage to form, the shielding structures on both sides would have to be electrically connected to one another.
Hierbei ergibt sich die Schwierigkeit, daß das Vorsehen von vertikal hindurchgehenden Kontaktierungen nur bei sehr dünnen Substratmaterial des Chips leicht zu realisieren ist. Demgegenüber ist es schwierig einen derart dünnen Chip doppelseitig mit derzeit üblicher Technologie zu bearbeiten. Der Erfindung liegt daher die Aufgabe zugrunde, eine integrierte elektronische Schaltungsanordnung vorzusehen, die mit einfachen Mitteln möglichst vollständig abschirmbar ist.The difficulty arises here that the provision of vertical contacts is easy to implement only with very thin substrate material of the chip. In contrast, it is difficult to process such a thin chip on both sides with currently common technology. The invention is therefore based on the object of providing an integrated electronic circuit arrangement which can be shielded as completely as possible using simple means.
Diese Aufgabe wird erfindungsgemäß durch eine Anordnung gelöst, wie sie gemäß Patentanspruch 1 angegeben ist. Durch diese Anordnung ist es möglich, daß das erste Substrat ausreichend dünn gestaltet werden kann, um eine Durchkontaktie- rung zu ermöglichen. Die zweite elektrische Abschirmanordnung kann dann auf dem zweiten Substrat angeordnet werden, und wird mittels einer Durchkontaktierung mit der ersten elektrischen, Abschirmanordnung verbunden. Auf diese Weise läßt sich mit einfachen Mitteln eine ausreichende Abschrimung gewährleisten.This object is achieved according to the invention by an arrangement as specified in claim 1. With this arrangement it is possible that the first substrate can be made sufficiently thin to allow through-plating. The second electrical shielding arrangement can then be arranged on the second substrate and is connected to the first electrical shielding arrangement by means of a via. In this way it is possible to ensure adequate shielding with simple means.
Da erstes und zweites Substrat unterschiedliche Qualität und Größe aufweisen können, ist es möglich, für Anschlüsse nach außen vorzusehene sogenannte Anschlußpads auf dem zweiten Substrat anzuordnen. Dies befindet sich in diesem Fall auf den größeren als zweites Substrat und ist aus einem preisgünstigeren Material herstellbar, wenn auf diesen nur noch die zweite elektrische Abschirmanordnung aufgetragen ist. Gleiches trifft zu, wenn auf dem zweiten Substrat noch Leitungsanordnungen aufgetragen sind.Since the first and second substrates can have different quality and size, it is possible to arrange so-called connection pads for connections to the outside on the second substrate. In this case, this is located on the larger than the second substrate and can be produced from a less expensive material if only the second electrical shielding arrangement is applied to it. The same applies if line arrangements are still applied to the second substrate.
Diese Anordnung ist nicht nur für die Verwendung der derzeit meist gebräuchlichen Halbleitertechnik anwendbar, sondern ebenfalls bei der derzeit sich im Entwicklungsstadium befindlichen Polymertechnik. Hierbei handelt es sich um organische Strukturen, die aus der dünnen Folie bestehen, und geeignet sind, vergleichbare Elemente, wie Transistoren, Dioden, Widerstände, Kondensatoren etc. zu bilden.This arrangement can be used not only for the use of the semiconductor technology that is currently mostly used, but also for the polymer technology that is currently in the development stage. These are organic structures that consist of the thin film and are suitable for forming comparable elements such as transistors, diodes, resistors, capacitors, etc.
Nachfolgend wird die Erfindung unter Bezugnahme auf die Figur an einem Ausführungsbeispiel erläutert. Beim ersten Substrat 1 ist eine elektrisch leitende abschirmende Anordnung 3 aufgetragen. An der Oberfläche des Substrats 1 zur abschirmenden Anordnung 3 ist eine integrierte Schaltung, die nicht dargestellt ist, ausgebildet.The invention is explained below with reference to the figure using an exemplary embodiment. An electrically conductive shielding arrangement 3 is applied to the first substrate 1. An integrated circuit, which is not shown, is formed on the surface of the substrate 1 for the shielding arrangement 3.
Auf einem zweiten Substrat 2 ist eine zweite elektrische Abschirmanordnung 4 ausgebildet, auf der die Rückseite des ersten Substrates 1 angeordnet ist. Die erste und die zweite elektrische Abschirmanordnung sind über eine Durchkontaktie- rung 6 miteinander elektrisch leitend verbunden.A second electrical shielding arrangement 4 is formed on a second substrate 2, on which the rear side of the first substrate 1 is arranged. The first and the second electrical shielding arrangement are electrically conductively connected to one another via a via 6.
Das zweite Substrat 2 ist zumindest in einer Richtung größer als das erste Substrat 1. Auf der überstehenden Fläche des zweiten Substrates 2 ist ein Anschlußkontakt 5, ein sogenann- ter Pad vorgesehen. Dieser ist über eine nicht dargestellte Leitungsanordnung über weitere nicht dargestellte vertikale Durchkontaktierung mit der integrierten Schaltung im ersten Substrat 1 verbunden. The second substrate 2 is larger than the first substrate 1 in at least one direction. A connection contact 5, a so-called pad, is provided on the projecting surface of the second substrate 2. This is connected to the integrated circuit in the first substrate 1 via a line arrangement, not shown, via further vertical plated-through holes, not shown.

Claims

Patentansprüche claims
1. Vertikal integrierte elektronische Schaltungsanordnung mit zumindest einem ersten Substrat (1), auf dem eine elektronische Schaltung integriert angeordnet ist und auf dessen einen Oberfläche zumindest eine erste elektrische Abschirmanordnung (3) aufgetragen ist und einem zweiten Substrat (2), auf dem das erste Substrat (1) angeordnet ist, wobei zwischen dem ersten und dem zweiten Substrat eine zweite elektrische Abschirmanordnung (4) angeordnet ist.1. Vertically integrated electronic circuit arrangement with at least one first substrate (1) on which an electronic circuit is arranged integrated and on the one surface of which at least one first electrical shielding arrangement (3) is applied and a second substrate (2) on which the first The substrate (1) is arranged, a second electrical shielding arrangement (4) being arranged between the first and the second substrate.
2. Vertikal integrierte elektronische Schaltungsanordnung nach Anspruch 1, wobei das zweite Substrat (2) eine größe- re Fläche als das erste Substrat (1) aufweist.2. Vertically integrated electronic circuit arrangement according to claim 1, wherein the second substrate (2) has a larger area than the first substrate (1).
3. Vertikal integrierte elektronische Schaltungsanordnung nach Anspruch 2, wobei auf dem Teil des zweiten Substrates (2), das nicht vom ersten Substrat (1) bedeckt ist, An- schlußkontakte (5) für die vertikal integrierte Schaltungsanordnung angeordnet sind.3. Vertically integrated electronic circuit arrangement according to claim 2, wherein connection contacts (5) for the vertically integrated circuit arrangement are arranged on the part of the second substrate (2) which is not covered by the first substrate (1).
4. Vertikal integrierte elektronische Schaltungsanordnung nach einem der vorhergehenden Ansprüche, wobei die erste und die zweite elektrische Abschirmanordnung miteinander elektrisch verbunden sind. 4. Vertically integrated electronic circuit arrangement according to one of the preceding claims, wherein the first and the second electrical shielding arrangement are electrically connected to one another.
PCT/DE2000/004483 2000-01-13 2000-12-15 Chip with all-round protection of sensitive circuit components using shielding by means of an auxiliary chip WO2001052324A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2000103112 DE10003112C1 (en) 2000-01-13 2000-01-13 Chip with all-round protection of sensitive circuit parts against access by unauthorized persons by means of shielding arrangements (shields) using an auxiliary chip
DE10003112.9 2000-01-13

Publications (1)

Publication Number Publication Date
WO2001052324A1 true WO2001052324A1 (en) 2001-07-19

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2232412B1 (en) * 2007-08-02 2019-03-06 Nxp B.V. Tamper-resistant semiconductor device and methods of manufacturing thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10105725B4 (en) * 2001-02-08 2008-11-13 Infineon Technologies Ag Semiconductor chip with a substrate, an integrated circuit and a shielding device
DE10251317B4 (en) * 2001-12-04 2006-06-14 Infineon Technologies Ag Semiconductor chip
DE10337256A1 (en) * 2002-11-21 2004-06-09 Giesecke & Devrient Gmbh Integrated circuit and production process especially for chip cards has active circuit on substrate surface and deep doped layer to protect against rear interrogation

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Publication number Priority date Publication date Assignee Title
US4514785A (en) * 1981-09-11 1985-04-30 U.S. Philips Corporation Method of manufacturing an identification card and an identification manufactured, by this method
US4563575A (en) * 1981-05-08 1986-01-07 Gao Gesellschaft Fur Automation Und Organisation Mbh Identification card having an embedded IC module
FR2609820A1 (en) * 1987-01-20 1988-07-22 Thomson Semiconducteurs Electromagnetic and electrostatic protection device for electronic cards and method for producing this device
EP0547877A2 (en) * 1991-12-16 1993-06-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor power module
DE19716102A1 (en) * 1997-04-17 1998-10-22 Siemens Ag Integrated circuit arrangement with several components and method for their production

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Publication number Priority date Publication date Assignee Title
DE4242097C2 (en) * 1992-12-14 2001-03-01 Bosch Gmbh Robert Arrangement for the electromagnetic compatibility (EMC) protection of hybrid components

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4563575A (en) * 1981-05-08 1986-01-07 Gao Gesellschaft Fur Automation Und Organisation Mbh Identification card having an embedded IC module
US4514785A (en) * 1981-09-11 1985-04-30 U.S. Philips Corporation Method of manufacturing an identification card and an identification manufactured, by this method
FR2609820A1 (en) * 1987-01-20 1988-07-22 Thomson Semiconducteurs Electromagnetic and electrostatic protection device for electronic cards and method for producing this device
EP0547877A2 (en) * 1991-12-16 1993-06-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor power module
DE19716102A1 (en) * 1997-04-17 1998-10-22 Siemens Ag Integrated circuit arrangement with several components and method for their production

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2232412B1 (en) * 2007-08-02 2019-03-06 Nxp B.V. Tamper-resistant semiconductor device and methods of manufacturing thereof

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Publication number Publication date
DE10003112C1 (en) 2001-07-26

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