WO2001031351A1 - Circuit d'interface de transducteur servant a evaluer une capacite et presentant de nombreuses possibilites de configuration - Google Patents

Circuit d'interface de transducteur servant a evaluer une capacite et presentant de nombreuses possibilites de configuration Download PDF

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Publication number
WO2001031351A1
WO2001031351A1 PCT/US2000/041207 US0041207W WO0131351A1 WO 2001031351 A1 WO2001031351 A1 WO 2001031351A1 US 0041207 W US0041207 W US 0041207W WO 0131351 A1 WO0131351 A1 WO 0131351A1
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WIPO (PCT)
Prior art keywords
capacitive
circuit
capacitor
capacitance
interface circuit
Prior art date
Application number
PCT/US2000/041207
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English (en)
Inventor
Ying Hsu
Christ Saunders
Kirk Su
Original Assignee
Microsensors, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsensors, Inc. filed Critical Microsensors, Inc.
Priority to JP2001533437A priority Critical patent/JP4870889B2/ja
Priority to US10/110,889 priority patent/US6731121B1/en
Priority to EP00982671A priority patent/EP1224478A4/fr
Publication of WO2001031351A1 publication Critical patent/WO2001031351A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing

Definitions

  • This invention relates generally to transducer interface circuits that detect a change in capacitance as a measure of change in a targeted physical quantity and, more particularly, to a highly configurable capacitive transducer interface circuit that is programmable to accommodate a differential or single-ended sensor, to provide a desired gain and offset, and to provide a desired bandwidth.
  • a significant disadvantage with the foregoing circuits is that they can only be optimized for a relatively small range of input parameters. Each circuit must be individually “tuned” to eliminate parasitic capacitance, and changed for different connections. Each type of transducer requires its own electronics, and "universal" signal processing circuit is not possible.
  • the prior art does not address the ability of a single circuit to measure both absolute changes (single-end) and relative changes (differential).
  • the prior art does not address the need to accommodate different bandwidth requirements.
  • the prior art does not address the manufacturing of the integrated circuits wherein processing tolerances often result in variations of on-chip resistors and capacitors which alters the circuit sensitivity. There remains a need, therefore, for a capacitance measurement circuit that accommodates wide differences in connectivity, bandwidths, and capacitance magnitudes.
  • the invention may be regarded as a capacitive transducer interface circuit that produces an output value that is proportional to a change in capacitance of a sense capacitor in a capacitive transducer
  • a capacitive adjustment section that is electrically connected to the sense capacitor, including: (a) a capacitor array circuit; (b) means for configuring the capacitance of the capacitor array circuit such that the sense capacitor and capacitive adjustment section combine to provide a substantially null value when the capacitive transducer is in a null state; and (2) a capacitive trans-impedance amplifier section that is electrically connected to the sense capacitor and the capacitive adjustment section, including: (a) a trans-impedance amplifier means for producing an output signal that is proportional to the change in capacitance of the sense capacitor; and (b) means for configuring the gain of the capacitive trans- impedance amplifier to provide a desired dynamic range.
  • the invention may be regarded as a capacitive transducer interface circuit that produces an output value that is proportional to a difference in capacitance between first and second capacitors that are connected together at a common terminal, comprising: (a) a trans-impedance amplifier means for producing an output signal that is proportional to the difference in capacitance between the first and second capacitors, said trans-impedance amplifier means including an operational amplifier having an inverting input, a non-inverting input, and an output, with the inverting input connected to the common terminal, with the non-inverting input connected to a reference ground, and with a feedback capacitance connected between the output and the non-inverting input; (b) a means for repeatedly (1 ) discharging the feedback capacitance, (2) applying a voltage difference across the first capacitors to charge the first capacitor while applying an equal potential voltage across the second capacitor to discharge the second capacitor; and (3) then reversing the voltages applied to the first and second capacitors such that the first capacitor discharges into the second
  • Figure 1 is a schematic representation of a known-type differential sensor that has a balanced pair of capacitors that vary in opposition to one another in response to an external stimulus;
  • Figure 2 is a schematic representation of a known-type single-ended sensor that has a single capacitor that varies in value in response to an external stimulus;
  • Figure 3 is a schematic block diagram of a first preferred transducer interface circuit 10 with certain details shown, including a capacitive adjustment section 100 and a capacitive trans-impedance amplifier section 200;
  • Figure 4 is a schematic block diagram of the first preferred transducer interface circuit 10 with further details shown, including a low pass filter section 300 and an output buffer section 400;
  • Figure 5 is a schematic block diagram of the first preferred transducer interface circuit 10 of Figure 4 with further details shown;
  • Figure 6 is a schematic diagram of the first and second capacitor circuit arrays in the preferred transducer interface circuit 10;
  • Figures 7 and 8 are abridged versions of the truth tables for the preferred capacitor circuit arrays of Figure 6;
  • Figure 9 is a timing diagram of the control signals that govern the operation of the preferred capacitive trans-impedance amplifier section of Figure 5;
  • FIG. 10 is a schematic block diagram of the preferred capacitive trans-impedance amplifier section of Figure 5, with additional details shown;
  • FIG 11 is a schematic block diagram of the preferred low pass filter section of Figure 5, with additional details shown.
  • Figure 12 is a schematic block diagram of the preferred output buffer section 400 of Figure 5, with additional details shown.
  • transducer interface circuit 10 is specifically designed to interface with a capacitive-type transducer 20 where the physical variation is transferred to a moveable plate that is located adjacent to a fixed plate.
  • the invention is best understood with initial reference to such sensors.
  • Figures 1 and 2 are simplified schematic representations of capacitive sensors 20A, 20B that are three-terminal and two-terminal devices, respectively.
  • Figure 1 shows a differential sensor 20A having a balanced pair of capacitors CS1 , CS2 that share a common plate so that they mechanically vary in opposition to one another in response to an external stimulus (signified by the vertical arrow). The two outer elements may instead move relative to a fixed common plate, but the principle of operation remains the same.
  • the differential sensor 20A of Figure 1 is "balanced" in that the sense capacitor CS1 and CS2 should have equal values in the absence of stimulus.
  • FIG. 2 shows a single-ended sensor 20B that has only one capacitor CS2 that varies in value in response to an external stimulus.
  • transducer interface circuit 10 may be readily configured for use with either type of sensor as explained further below.
  • Capacitive sensors are used in various applications, including pressure sensors, accelerometers, gyros, and so on. Capacitive sensors are often used in Micro Electro-Mechanical Systems (MEMS) where the sensor's nominal capacitance is very small (e.g. picofarads). It is usually difficult to use one transducer interface circuit with multiple makes of transducers because of the variation in capacitance under stimulation will vary greatly from transducer to transducer. In other words, it is usually necessary to customize the interface circuit during the design phase, or by using large external components, to provide a dynamic range and resolution that is appropriate for a particular sensor.
  • MEMS Micro Electro-Mechanical Systems
  • FIG. 3 is a schematic block diagram of a first preferred transducer interface circuit 10 with certain details shown, including a capacitive adjustment section 100 and a capacitive trans-impedance amplifier section 200.
  • the transducer interface circuit 10 is provided as an application specific integrated circuit that interface with a capacitive sensor 20A or 20B and produces an output signal that is proportional to changes in capacitances within the sensor.
  • the output signal in the preferred sensor 10 is a voltage that is likely to be provided to an external A/D converter.
  • the transducer interface circuit itself, however, could include built-in A/D functionality such that the output signal is provided in digital form.
  • the capacitive adjustment section 100 uniquely interfaces with a balanced pair sensor 20A or a single-ended sensor 20B.
  • the capacitive adjustment section 100 is electrically connected to a sense capacitor (e.g. CS1 and/or CS2) in the capacitive sensor 20A, 20B.
  • the capacitive adjustment section 100 includes a capacitor array circuit 105 (shown symbolically by the variable capacitor icon) and means 110 for configuring the capacitance of the capacitor array circuit such that the sense capacitor 20A, 20B and the capacitive adjustment section 100 combined to provide a substantially null value when the capacitive transducer 20A, 20B is in a null state.
  • the capacitor array circuit 105 is in parallel with one of the sense capacitors CS1 , CS2, and the preferred adjustment means 110 varies the capacitor array circuit 105 in order to provide coarse offset trim (i.e. to make sure that the sensor 20A and the capacitive adjustment section 100 have a null value when the sensor is in a null position).
  • the capacitor array circuit 105 is connected in series with the sense capacitor CS2 to serve as a dummy capacitor that makes the two capacitors electrically equivalent to a differential sensor, and the preferred adjustment means 110 varies the capacitor array circuit 105 in order to vary the dummy capacitance such that the sensor 20B and the capacitive adjustment section 100 have a null value when the sensor is in a null position.
  • the preferred adjustment means 110 is explained more fully below.
  • the CTIA 200 is electrically connected to the sense capacitor and to the capacitive adjustment section 100 in order to transform any variation in their collective impedance into the output signal.
  • the CTIA 200 includes an amplifier means 205 for producing an output signal that is proportional to the change in capacitance of the sense capacitor CS1 , CS2.
  • the CTIA 200 is coupled to a means 210 for configuring the gain of the CTIA in order to provide a desired dynamic range, or range of operation.
  • Figure 4 is a schematic block diagram of the first preferred transducer interface circuit 10 with further preferred details shown, including a low pass filter section 300 and an output buffer section 400. As shown, the low pass filter section 300 cooperates with a means 310 for configuring its characteristic bandwidth.
  • the output buffer section 400 includes an amplifier circuit 405 that provides additional gain and a desired DC offset that is set with a reference voltage VREF, and it cooperates with a means 410 for configuring the additional gain and desired DC offset.
  • the details of Figure 4 have been illustrated separately from those of Figure 3 because the latter are considered relatively essential.
  • FIG. 5 is a schematic block diagram of the first preferred transducer interface circuit 10 with even further details shown.
  • the internal circuit details of the functional blocks 100, 200, 300, 400 are now illustrated and will be explained.
  • Capacitive Adjustment Section 100 interfaces with three leads CS1 IN, CSCOM, CS2IN and includes first and second capacitor array circuits CS1JNT and CS2JNT that are electrically disposed between the three leads.
  • the capacitor array circuits uniquely allow for large miss- matches in capacitor sensor values such that the circuit 10 accommodates a wide range in manufacturability.
  • the transducer interface circuit 10 is connected to a balanced-pair sensor 20A (as actually shown), then one or the other of the first and second capacitor array circuits CS1JNT and CS2JNT will be varied by a small amount to trim out any offset that may be present in the sensor 20A. If the transducer interface circuit 10 is connected to a singled-ended sensor 20B having only a single sensor capacitor CS2, however, then the first capacitor array circuit CS1JNT will be set to equal the sense capacitor CS2 and the second capacitor array circuit CS2JNT will be zeroed. In the preferred embodiment, CS1JNT varies from 0-9.709pF while CS2JNT only varies from 0-1.197pF. One or the other will be used in a modest amount to trim a balanced pair sensor 20A, while the larger valued CS1JNT may be set near its full-scale end to provide a suitable dummy capacitance for use with a single-ended sensor 20B.
  • Figure 5 shows that the preferred means 110 for configuring the capacitance of the capacitor array circuits CS1JNT, CS2JNT comprises control registers CS1_INT[8:0], CS2_INT[5:0].
  • the preferred embodiment is designed to accommodate a large range of sense capacitance (0.25-1 OpF) by including programmable capacitor circuit arrays CS1JNT, CS2JNT.
  • the arrays are variable with a resolution of 0.019pF/bit and uniquely enable the transducer circuit 10 to reduce sense capacitor offsets and enable both single-ended and differential mode operation.
  • the circuit 10 in fact, can operate single-ended over the entire 0.2-1 OpF operating range.
  • Figures 7 and 8 are abridged versions of the truth tables for the preferred capacitor circuit arrays are as follows:
  • control registers CS1_INT[8:0], CS2_INT[5:0], like all of the control registers used in the circuit 10, may be loaded over a suitable interface (e.g. by shifting in values using a serial interface) or by storing the values in a ROM and then loading the values into the registers as needed.
  • the preferred circuits provides a serial interface for testing and development and an internal EEPROM for storing final values.
  • Figure 6 shows that the preferred capacitor array circuits CS1JNT, CS2JNT are comprised of parallel arrays of binary weighted capacitances that are switched in according to a suitable logic signals that are derived from the values stored in the control registers CS1_INT[8:0], CS2JNT[5:0].
  • Other circuit arrangements are possible.
  • the CTIA 200 includes unique drive circuitry that is used to sense the capacitive values in the sensor, and the amplifier means 205 mentioned above with reference to Figure 3.
  • the CTIA section 200 senses the difference in capacitance between the two capacitance values on either side of CSCOM then provides an output voltage that is proportional to the difference.
  • the capacitors to be sensed are CS1 and CS2 (see Figure 1 ).
  • the capacitors to be sensed are CS1JNT and CS2 (see Figure 2).
  • the preferred amplifier means 205 is a differential amplifier circuit A1 that has its non-inverting input referenced to 2.25V, and a feedback capacitance CF connected between its output and its inverting input.
  • the value of the feedback capacitance CF determines the overall gain of the amplifier means 205 as more fully explained below.
  • the preferred amplifier A1 has a folded cascade operational amplifier topology, but other known arrangements may be used
  • the preferred amplifier A1 is provided with two bandwidths that are selectable with an "enable bandwidth" bit ENBW.
  • ENBW When ENBW is low, the amplifier's open-loop gain is at a standard level.
  • ENBW is high, the amplifier's open-loop gain is increased by a factor of four and the closed-loop circuit is more responsive, but at the expense of power consumption.
  • the selected bandwidth will largely be a function of power consumption requirements.
  • the CTIA section 200 measures the capacitance by uniquely oscillating a voltage around the two capacitances on either side of CSCOM. As a result, the capacitances are repeatedly charged and then discharged into one another to the extend they are of equal value.
  • CS1T and CS2T are the total capacitances on either side of CSCOM.
  • the values of CS1T and CS2T are a function of the CS1 and CS1JNT, and of CS2 and CS2JNT, i.e.
  • the preferred circuit operates with a single 5 volt supply and it contains an internal 2.25V precision voltage reference for use as a reference ground.
  • the preferred CTIA section 200 includes an internal oscillator 220 that runs at 100KHz.
  • the oscillator 220 governs a timing circuit 230 that drives a pair of switches 231 , 232 that are respectively connected to CS1 IN and CS2IN and, thereby, to the capacitors that lead from those terminals to CSCOM.
  • the oscillator 220, timing circuit 230, and switches 231 , 232 operate to repeatedly oscillate CS1 IN and CS2IN between 2.25V and 0V.
  • CS2T is at 2.25V.
  • a preset switch S1 is provided in the feedback path and controlled by the timing circuit 230.
  • the preset switch S1 is used to discharge the feedback capacitance CF at the beginning of each cycle so that it is ready to sink any excess charge or source any deficiency as a measure of the capacitive difference. If CS1T is smaller than CS2T, then less charge will be in CS1T than in CS2T and current will flow from the feedback capacitance CF such that the output voltage drops below 2.25V.
  • Figure 9 is a timing diagram of the just-described capacitive sampling process.
  • oscillator 220 and timing circuit 230 combine to produce a CLOCK with a period T1.
  • the preset PRST signal is asserted such that the preset switch S1 is closed and the feedback capacitance CF is fully discharged.
  • the amplifier is auto-zeroed during PRST while CS2 is at 2.25V, or VREF.
  • PRST then goes low, resulting in S1 opening for correlated double sampling.
  • the CLOCK goes low, the voltages on the capacitances CS1T, CS2T are reversed.
  • FIG. 10 is a schematic block diagram of the preferred capacitive trans-impedance amplifier section of Figure 5, with additional details shown, that best illustrates the preferred circuitry for varying the feedback capacitance CF according to a value set in the means 210 for configuring the gain of the CTIA 200. As shown, the feedback capacitance CF is varied according to a feedback control register CF[9:0] by selectively connecting some on-chip capacitors to the inverting input of the amplifier A1 , and by connecting other of the on-chip capacitors to the reference ground.
  • the preferred feedback capacitance circuit CF ranges from 0 to 19.437 pF and is controlled with 10 bits of programmability in 19pF steps.
  • the programmable configuration of the feedback capacitance permits the circuit 10 to be optimized for range and performance.
  • An abridge truth table for the control fo the feedback capacitor circuit CF is as follows:
  • the preferred circuit 10 provides a low pass filter section 300 in order to limit the signal and noise bandwidths.
  • the preferred low pass filter section 300 is trimmable over the range of 100Hz to 8KHz, without requiring any external components.
  • the input of the preferred low pass filter section 300 includes switched-capacitor circuits 320, 330 because the preferred CTIA section 200 is auto-zeroes every cycle.
  • the switched-capacitor circuits 320, 330 share many common components as only one or the other is used at any one time.
  • the output of the low pass filter section includes a two pole, continuous time LPF 340 that is trimmable over the range of 500-8000Hz.
  • the first circuit 320 is a one pole, 32KHz, switched-capacitor LPF that functions as a sample/hold circuit 320 when it is the continuous time LPF 340 that governs the bandwidth.
  • the second circuit 330 is a two pole, 100-465Hz, switched-capacitor LPF 330 that is used when the desired bandwidth is lower than can be accomplished with the CT-LPF 340. When used, the output of the lower frequency SC_LPF 330 is still passed through the CT_LPF 340 with the CT-LPF 340 set to its lowest bandwdith (500Hz) in order to provide clock feed-through attenuation.
  • the low pass filter section 300 is characterized by programmable structures.
  • the control registers provided are by a sample/hold enable bit SHEN, a first capacitance selection register CSEL[1 :0], and a second capacitance selection register CSELCT[3:0].
  • SHEN is used to select between the lower and higher bandwidth range.
  • the switched capacitor LPF 330 is enabled and operates to set the bandwidth between 100 and 465 Hz.
  • the 32KHz sample/hold circuit 320 is enabled in order to bypass the LPF functionality of the switched capacitor LPF 330 such that it is the CT_LPF 340 that is used to set the bandwidth between 500Hz and 8KHz.
  • the individual LPFs 330, 340 are trimmable to a desired bandwidth within their respective ranges in accordance with the preferred embodiment of this invention.
  • the first capacitance selection register CSEL[1 :0] is used to set the 3 dB bandwidth of the switched-capacitor LPF 330 to one of four values v:
  • the second capacitance selection register CSELCT[3:0] is used to set the 3dB bandwidth of the continuous-time LPF 340 to one of nine states (11001-11111 are unused states) as shown by the following truth table:
  • the preferred transducer interface circuit 10 further includes an output buffer section 400 that provides a desired output impedance and even more adjustability with regard to gain and offset.
  • the preferred output buffer section 400 includes an inverting voltage amplifier that is implemented with an operational amplifier A2 that is based on a constant-g m rail-to-rail input stage. It includes three programmable features: (1 ) signal path gain; (2) voltage reference level control; and (3) fine VDC offset trim.
  • Figure 12 is a schematic block diagram of the output buffer section 400 that is similar to that shown in Figure 5, but with additional detail.
  • the signal path gain is set by controlling the value of a resistor resistance trim circuit 420 such that the total feedback resistance R2+RT varies relative to an input resistance R1.
  • the nominal signal path gain is set to 2V/V based on R2/R1 where R2 is 2 * R1.
  • the nominal gain of 2V/V may be trimmed in the range of +/- 0.3V/V (+/- 15%) in 0.0024V/V steps by using a resistive circuit control register B[7:0] as suggested by the following abridged truth table:
  • the DC offset voltage and find offset trim are adjusted within a voltage trim circuit 430 that includes a switch S2 and a resistor string 431.
  • the voltage trim circuit 430 operates with a precision voltage reference V2P25, and a current source I that may each be implemented in a known manner.
  • the amplifier A2's voltage reference may be uniquely set to two different set points in order to optimally accommodate a differential sensor 20A and a single-ended sensor 20B.
  • a sensor offset bit SOFF is used to select between a 2.25V set point and a 0.5V set point.
  • a 2.25V set point is selected for use with a balanced-pair sensor 20A so that the output voltage VO ranges between 0.5V and 4.5V, on either side of a 2.25V center.
  • a 0.5V set point is selected for use with a single-ended sensor 20B so that the resulting singled-ended output voltage VO ranges from 0.5V to 4.5V with near-maximal resolution.
  • the fine VDC offset trim is adjusted by finely varying the voltage reference provided to the amplifiers non-inverting input. This is a desirable feature because there may still be some small amount of DC offset even after the coarse offset trim was accomplished by using one of the internal capacitor circuits CS1JNT, CS2JNT to coarsely trim away a mismatch between a balanced-pair of external sense capacitances CS1 , CS2, or by making the internal capacitor circuit CS1JNT coarsely equal to a single-ended external sense capacitance CS2, as described above.
  • the fine trim for DC offset for the output buffer section 400 ranges +/- 10OmV in 6.25 mV steps.
  • An abridged version of the truth table is as follows:
  • the preferred configuring means 110, 210, 310, 410 are further comprised of on-chip EEPROM that sends the user's desired data to the on-chip registers
  • the user has the option of storing the configuration values in the EEPROM (not shown) or of loading the control registers directly using a serial input. The latter feature is useful during test and development stages of a particular application of the capacitive transducer interface circuit, the EEPROM being used to store the final values in a more lasting manner.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Fluid Pressure (AREA)
  • Amplifiers (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)

Abstract

Circuit d'interface de transducteur (10) conçu pour être mis en application avec un détecteur de capacité (20). Ce circuit d'interface (10), situé sur un circuit intégré spécifique à l'invention, comprend de nombreuses possibilités de réglage lui permettant de fonctionner avec des détecteurs différentiels équilibrés par paire (20A) ou un détecteur à extrémité unique (20B). Ce circuit (10), en particulier, comporte une section de réglage capacitif (100) et une section d'amplification de transimpédance capacitive (200) présentant des configurations de commandes de réglage de condensateur (110) et de commandes de réglage d'amplification (210) qui, avec d'autres commandes, se présentent sous la forme de registres de commandes. La section d'amplification de transimpédance capacitive (300) inverse périodiquement les tensions au détecteur (20) et la section de réglage capacitive (200), après avoir annulé une capacitance de rétroaction (CF) utilisée pour intégrer l'excès de charge provoqué par une différence de capacitance. Une section filtre passe-bas (300) effectue le réglage de la largeur de bande sans utiliser de composants extérieurs. Une section tampon de sortie (400) comprend d'autres commandes de réglage d'amplification et de décalage et est également commandée par un bit de sélection de décalage SOFF réglant la plage de sortie afin qu'elle soit adaptée de façon optimale aux détecteurs à paire équilibrée (20A) ou au détecteur à extrémité unique (20B).
PCT/US2000/041207 1999-10-15 2000-10-16 Circuit d'interface de transducteur servant a evaluer une capacite et presentant de nombreuses possibilites de configuration WO2001031351A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001533437A JP4870889B2 (ja) 1999-10-15 2000-10-16 高度に構成可能な容量性トランスデューサインターフェイス回路
US10/110,889 US6731121B1 (en) 1999-10-15 2000-10-16 Highly configurable capacitive transducer interface circuit
EP00982671A EP1224478A4 (fr) 1999-10-15 2000-10-16 Circuit d'interface de transducteur servant a evaluer une capacite et presentant de nombreuses possibilites de configuration

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15983299P 1999-10-15 1999-10-15
US60/159,832 1999-10-15

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EP2177880A1 (fr) * 2008-10-16 2010-04-21 Dialog Imaging Systems GmbH Mesure de la distance à l'aide d'un capteur capacitif
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US9307319B2 (en) 2012-04-18 2016-04-05 Nxp, B.V. Sensor circuit and calibration method
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DE102004052034B4 (de) * 2003-11-07 2013-02-21 Denso Corporation Schaltung zum Erfassen einer Kapazitätsänderung in einem variablen Kondensator
EP1548409A1 (fr) * 2003-12-23 2005-06-29 Dialog Semiconductor GmbH Mesure de capacité différentielle
US6949937B2 (en) 2003-12-23 2005-09-27 Dialog Semiconductor Gmbh Differential capacitance measurement
US8264247B2 (en) 2006-03-21 2012-09-11 University Of Sussex Electric potential sensor
EP2177880A1 (fr) * 2008-10-16 2010-04-21 Dialog Imaging Systems GmbH Mesure de la distance à l'aide d'un capteur capacitif
US8076948B2 (en) 2008-10-16 2011-12-13 Digital Imaging Systems Gmbh Distance measurement with capacitive sensor
DE102009026496B4 (de) 2009-05-27 2022-04-28 Robert Bosch Gmbh Kompensationskapazität für einen kapazitiven Sensor
EP2653846A1 (fr) * 2012-04-18 2013-10-23 Nxp B.V. Circuit de capteur et procédé d'étalonnage
US9307319B2 (en) 2012-04-18 2016-04-05 Nxp, B.V. Sensor circuit and calibration method
CN104335035A (zh) * 2012-06-01 2015-02-04 史密斯探测-沃特福特有限公司 具有偏置的容性跨阻放大器

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JP4870889B2 (ja) 2012-02-08
JP2004500557A (ja) 2004-01-08
EP1224478A4 (fr) 2004-05-19

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