Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/662—Multiplexed conversion systems
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
  • H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation

Definitions

• the invention relates to a D/A-converter according to claim 1, 10, 12 and 14, a method of generating at least one time-modulated output signal according to claim 15 and 18, a multi-stage D/A converter according to claim 20 and use hereof according to claim 22 and 23.
• a high resolution D/A converter must have low differential non-linearity and integral non- linearity. These requirements to linearity have to be maintained over temperature.
• a problem with conventional, fast low-cost D/A converters is that non-linearities are quite prevailing and the nature of these non-linearities do in reality restrict the use of high-bit converters as an increase in the number of bits increases the differential non-linearities of the least significant bits.
• One of several techniques introduced in order to obtain high-resolution and fast D/A-converters basically includes two separate D/A converters of which one establishes the most significant analogue part of the digital input -signal , and the other establishes the less significant part of the analogue signal. Finally, the two analogue signals are added in an analogue summing stage.
• a digital to analogue converting device comprises
• a converting step establishing an upper (UL) and a lower voltage level (LL) in dependency of at least one digital input signal (DIS) ,
• said upper (UL) and lower voltage levels (LL) being time- modulated in dependency of at least said digital input signal (DIS) into a time-modulated output signal (TMOS) ,
• said time-modulated output signal being fed through an output stage comprising at least one integrator (I),
• said integrator (I) being dimensioned in such a way that said time-modulated output signal is filtered and converted into an analogue representation of said digital input signal (DIS) , an advantageous D/A-converter has been obtained.
• said time-modulated output signal (TMOS) is a PWM-signal
• said upper and lower levels (UL, LL) are established by means of a digital MUX controlling a DAC, said MUX being fed parallely or serially by digital input signals in such a way that a digital output of the MUX continuously controls the DAC and establishes a first analogue signal comprising an upper level (UL) and a lower level (LL) based on the output of the DAC, a further advantageous embodiment of the invention has been obtained.
• said upper and lower levels are established by means of dedicated DAC (DAC1, DAC2) each establishing an analogue output signal (UL, LL) in dependency of digital signals fed to said dedicated DACS, said analogue signals being analogue, multiplexed by means of a switch to form said first analogue signal (AS1) , a further advantageous embodiment of the invention has been obtained.
• This sub-resolution may be established by means of e.g. a relative low-bit PWM modulation, as the first part of the signal has already been established by the lower level voltage LL.
• PWM modulation may be executed quite fast due to the fact that the necessary clock-cycles of the PWM modulator decreases by 2 n for each bit resolution being established by the generation of the upper and lower level signals.
• the relatively slow PWM but linear modulator may establish the sub- resolution.
• the upper and lower levels are established by means of a conventional 10 -bit D/A-converter, of which only the upper 8-bits are used to establish the desired levels.
• the two least significant bits are cancelled due to non- acceptable non-linearity.
• the resulting 8-bit signal is PWM modulated between a lower level, i.e. the closest possible approximation of the 8 -bit converter and this signal plus the least significant bit, i.e. plus bit 8.
• the PWM establishes a five-bit resolution signal and adds it to the lower level signal. Consequently, the resulting linearity of a high bit precision converter is significantly improved.
• the dimensioning of a D/A converter according to the invention should be carried out carefully with respect to the current application, as the dimensioning will be a trade-off between parameters such as e.g. acceptable non-linearity, resolution, dynamic range and conversion speed.
• D/A-converters establishing the amplitude modulation should be chosen carefully, as e.g. a high quality D/A-converter may be utilised fully instead of carrying out the above-mentioned cancelling of the least significant bits.
• the MUX is synchronised with the DAC(s), a further advantageous embodiment of the invention has been obtained.
• the synchronisation of the multiplexer and the D/A-converter (s) improves linearity significantly.
• said integrator (I) comprises a low-pass filter
• a further advantageous embodiment of the invention has been obtained.
• a low-pass filter may be established in an attractive manner in regard to costs .
• time-modulated output signal (TMOS) is established as a fractional N-divided signal
• TMOS time-modulated output signal
• said integrator (I) is dimensioned as a low-pass filter having a period (T) « ⁇ , where ⁇ is the time-constant RC of the integrator (I) , R is the resistance and C is the capacitance, a further advantageous embodiment of the invention has been obtained benefiting from the fact that modulation resulting from the coding has been moved to higher frequencies.
• the necessary time-constant of the output filter may be reduced from e.g. ten times the period of time-modulation to approximately one period.
• an integrator within the terms of the invention is a filter having the desired integrating properties, as an ideal integrator is impossible to realise .
• An integrator according to the invention may thus be realised by means of a filter having integrating properties, such as e.g. a low- or band-pass filter.
• time-modulated output signal is not modified in such a way that low frequency components of said time- modulated signal are minimised, a time-constant less than approximately ten times the period would be preferable.
• a digital to analogue converting device comprises a converting step establishing an upper (UL) and a lower voltage level (LL) in dependency of at least one digital input signal (DIS) , said upper voltage level (UL) being fed to an input of a first DAC and said lower voltage level (LL) being fed to an input of a second DAC, where the output signal of said first DAC is fed to a first input of a time-modulated output stage, and the output signal of said second DAC is fed to a second input of said time-modulated output stage, and where the input impedance of said first and second input of said output stage is substantially equal, an advantageous embodiment of the invention has been obtained.
• output stage is meant any type of output circuit which the DACs can be fed into.
• An example could be one or more filters comprising resistive and/or capacitive elements.
• Another example could be any kind of time-modulated switching circuit.
• a digital to analogue converting device comprises a converting step establishing an upper (UL) and a lower voltage level (LL) in dependency of at least one digital input signal (DIS) , said upper voltage level (UL) being fed to an input of a first DAC and said lower voltage level (LL) being fed to an input of a second DAC, where the output signal of said first DAC is fed to a first input of a time-modulated output stage and the output signal of said second DAC is fed to a second input of said time-modulated output stage, and where the difference in input impedance of said first and second input of said output stage is less than +/- 40 % and preferably less than +/- 5 %, a further advantageous embodiment of the invention has been obtained. Especially the possibility of minimising the discontinuity of the output signal is very preferably.
• a digital to analogue converting device comprises a converting step establishing an upper (UL) and a lower voltage level (LL) in dependency of at least one digital input signal (DIS) , said upper voltage level (UL) being fed to an input of a first DAC and said lower voltage level (LL) being fed to an input of a second DAC, where the output signal of said first DAC is fed to an input of a resistive network and the output signal of said second DAC is fed to an input of said resistive network, and where the inputs of said resistive network is common for the output signals of said first and second DAC, it is possible to establish D/A-converters where the monotony in the output signal is assured. This is due to the fact that the two DACs look into impedances being of the same value .
• common is meant that the output signals of the two DACs can be connected to one common input node in the resistive network or two separate nodes being short circuited or substantially short circuited to each other in a known manner.
• a method generates at least one time-modulated output signal (TMOS) in dependency of at least one digital input signal, said digital input signal (DIS) , and said output signal comprising a substantially fixed period (Tp) in which the output amplitude is established as at least an upper voltage level (UL) or a lower voltage level (LL) or a further level, the time-modulated output signal (TMOS) having an output amplitude (OA) being defined by said input digital signal (DIS) , and said time-modulated output signal (TMOS) switching between at least said upper voltage level (UL) and lower voltage level (LL) in dependency of said digital input signal (DIS) at certain switching times (Ts) , an advantageous establishment of a time- modulated output signal with commercially attractive components may be obtained.
• the method provides the possibility of establishing high- resolution D/A- converters having very low non-line
• fig. 1 shows a prior-art linear D/A converter
• fig. 2 shows a first and preferred embodiment of a D/A-converter according to the invention
• fig. 3 shows a further embodiment of a D/A- converter according to the invention
• fig. 4 shows the output waveform of the D/A converter of fig. 2
• fig. 5 shows the feeding of the digital input
• fig. 6 shows the composition of the analogue output signal
• figs. 7a-7c show a method of transforming the output signal.
• Fig. 1 shows an example of a prior-art high n-bit D/A converter .
• the method used to obtain a high number of bits by the illustrated D/A-converter is utilised in a great variety of instrumentation converter applications.
• the converter comprises two D/A-converters, a ten-bit D/A converter 11 and a five-bit D/A converter 12.
• the converters are mutually calibrated in such a way that converter 11 determines the most significant bit component of the signal and converter 12 establishes the least significant bit component of the signal.
• the two signals are matched by means of amplifiers and finally summed in a summing unit 15.
• the above-mentioned technique has the advantage of high- resolution, fast conversion and no time delay.
• a problem with the above-mentioned prior-art converter type is that the two converters have to match each other very carefully, and this matching implies time-consuming calibration. Moreover, careful calibration will not eliminate the non-linearities of each converter unless complicated and costly arrangements are utilised.
• Fig. 2 shows a preferred embodiment of the invention comprising two parallel digital input registers, REG H 21 and REG L 22.
• Digital and serial output signals from registers 21 and 22 are fed to a digital MUX 23.
• the digital output of the MUX 23 is fed to a DAC 24.
• the DAC 24 outputs analogue signals according to the digital input to an analogue low-pass filter 26.
• the converter moreover, comprises a register 27 controlling a PWM modulator 25 controlling both the MUX and DAC 24.
• the function of the D/A-converting device is that a given digital multi-bit signal is fed to the registers 27, 21 and 22.
• the multi-bit signal is divided into sub-segments in such a way that a certain desired resolution is obtained.
• REG 21 determines an upper level (UL) of a pulse established by the D/A-converter 24, and REG 22 determines a lower level (LL) of the pulse established on the basis of the output of the D/A-converter 24.
• the upper and lower level signals (UL) and (LL) will be time-modulated by the PWM 25 according to the contents of REG 27.
• the PWM modulation is implemented as having a fixed time period Tp .
• the waveform of the output of the D/A-converter is illustrated in fig. 4, in which the PWM period is represented by Tp .
• the period Tp is sub-divided into a number of clock cycles, Tclock.
• the fixed period of PWM modulation consist of four clock cycles Tclock. Consequently, the PWM establishes an effective two-bit modulation.
• the output of the D/A-converter 24 consists of amplitude modulated upper and lower signal components established and determined by REG 21 and REG 22, while also being time- modulated by the PWM-modulator 25 according to REG 27.
• the modulation is digitally controlled.
• Fig. 3 shows a further embodiment of the invention in which modulation is analogue, but still digitally controlled.
• the D/A-converter comprises three digital input registers REG 31, REG 32 and REG 33.
• REG 31 controls a D/A- converter 36 and
• REG 32 controls a D/A-converter 37.
• the D/A-converters establish an upper and a lower voltage level UL, LL each.
• REG 33 controls a PWM modulator 38 which controls an analogue multiplexer in the form of an analogue switch 39.
• the two D/A converters establish an upper level UL and a lower level LL under the control of REG 31 and REG 32, and the PWM modulator 38 establishes a PWM time-modulation when switching between the upper level and the lower level under the control of REG 38.
• the switching between the upper and the lower levels over a fixed period Tp establishes a modulation of a signal which is fed to an output low-pass filter 34 in which an analogue signal is generated.
• the LP filter 34 is dimensioned in such a manner that it matches the fixed period Tp and the possible signal levels.
• the signal is modulated between an upper level UL and a lower level LL at each switch of time Ts .
• each modulation period is represented by Tp, and each period Tp contains four clock cycles Tclk.
• each modulation period Tp may contain either one, two, three or four high-level clock cycles, Tclk, resulting in a corresponding modulation level of 25%, 50%, 75% and 100%, respectively.
• the upper level UL and the lower level LL are located quite close, i.e. e.g. 2.755 V and 2, 750 V.
• a thirteen-bit digital number 51 represents a number fed into a thirteen bit D/A-converter according to the invention.
• the thirteen-bit signal is then split up into two eight bit signals and fed into two registers Rl and R2.
• Register R2 contains the eight most significant bits of the thirteen bit input 51.
• Register Rl contains an incremented version of the eight most significant bits of the thirteen-bit input 51, i.e. the value in register Rl has been added to the least significant bit of register 51.
• the least significant bit is taken from the eight most significant bits already in register Rl and added to the contents of register Rl .
• the contents of register Rl establish an upper level signal UL and the contents of register R2 establish a lower level signal LL .
• the PWM signal is shown as a two-bit signal instead of a five-bit signal .
• the diagram illustrates the analogue output of a D/A- converter according to the invention on an axis A as a function of the PWM-modulation of UL and LL according to the PWM bits.
• Registers Rl and R2 establish an upper and a lower level UL, LL.
• the lower level may be regarded as a truncated modification of the thirteen-bit signal 51, i.e. the five least significant bits have been zeroed.
• the analogue equivalent of register R2 is consequently equal to or lower than the desired analogue thirteen-bit signal.
• the analogue signal of the five least significant bits of register R3 has to be added in order to obtain the desired analogue signal.
• this "adding" is carried out by means of PWM modulation of the least significant bit of the eight-bit signal in register R2 with respect to Rl .
• the distance between UL and LL represents the least significant bit of the upper eight bits of the thirteen- bit signal .
• the added signal is then determined by the PWM modulation of UL over LL.
• the five bits of register R3 have been reduced to two in order to be able to show the functionality of this PWM modulation.
• a problem with a traditional PWM signal is that the PWM contains undesirable low-frequency components due to the nature of the PWM-coding of the signal .
• Fig. 7a shows a period, Tp, of a pulse-width modulated PWM signal.
• the signal is established over a period, Tp, having sixteen clock periods. Each clock period is numerated from one to sixteen.
• the shown signal contains a DC- signal which may be fed to the output filter of the converter. Moreover, it will be appreciated that the signal establishes low-frequency modulation with the lowest modulation frequency being 1/Tp. Since Tp is relatively high, the modulation will appear in the low frequencies of the band.
• the cut-off frequency has to be very close to DC and the low- pass characteristics have to be sharp.
• the time constant ⁇ of the integrator should be about 10 times the period of the period Tp of the PWM-signal.
• the requirements to the output filter will be reduced in relation to the frequency spectrum, and the time window may be reduced to as little as Tp, i.e. the ⁇ «Tp .
• the output of the integrator may then be established with a relatively short time-constant.
• V DC V DC over the period Tp is illustrated by means of the dotted line VDC.
• Fig. 7b illustrates the first step of transforming the PWM signal of fig. 7a into a signal having higher frequency components while still preserving the DC value over the period Tp .
• the number of upper levels and lower levels is determined. If the number of lower level signals is less than that of the upper level signals, the first step will be that of fig. 7b, and the last six lower levels in positions 11-16 will be moved from end of the period Tp to positions 2, 4, 6, 8, 10 and 12, respectively. The DC value of the period is maintained. Still, the period contains a high-level pulse in positions 13-16.

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• 1999
  • 1999-07-09 DK DK199901006A patent/DK199901006A/da not_active Application Discontinuation
• 2000
  • 2000-07-10 EP EP00943696A patent/EP1208647A2/en not_active Withdrawn
  • 2000-07-10 WO PCT/DK2000/000381 patent/WO2001005036A2/en not_active Application Discontinuation
  • 2000-07-10 CN CNA008101094A patent/CN1636322A/zh active Pending
  • 2000-07-10 AU AU58065/00A patent/AU5806500A/en not_active Abandoned

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