WO2001001482A1 - Procede de production de cellules de memoire morte - Google Patents

Procede de production de cellules de memoire morte Download PDF

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Publication number
WO2001001482A1
WO2001001482A1 PCT/DE2000/001755 DE0001755W WO0101482A1 WO 2001001482 A1 WO2001001482 A1 WO 2001001482A1 DE 0001755 W DE0001755 W DE 0001755W WO 0101482 A1 WO0101482 A1 WO 0101482A1
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WO
WIPO (PCT)
Prior art keywords
implantation
source
drain
programming
regions
Prior art date
Application number
PCT/DE2000/001755
Other languages
German (de)
English (en)
Inventor
Peter Wawer
Oliver Springmann
Konrad Wolf
Olaf Heitzsch
Kai Huckels
Reinhold Rennekamp
Mayk Röhrich
Elard Stein Von Kamienski
Christoph Kutter
Christoph Ludwig
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2001001482A1 publication Critical patent/WO2001001482A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed

Definitions

  • the present invention relates to a method of manufacturing ROM memory cells and, more particularly, to a method of manufacturing non-volatile read only memory (ROM) cells that can be programmed in a late manufacturing step.
  • ROM read only memory
  • Non-volatile read-only or ROM memory cells are used in a variety of integrated circuits for storing circuit-inherent data. Such non-volatile memory cells are usually used in an integrated circuit in conjunction with electrically erasable memory cells (so-called EPROMs, EEPROMs, FLASH-EPROMs) and read / write memory cells (RAMs).
  • EPROMs electrically erasable memory cells
  • EEPROMs electrically erasable memory cells
  • FLASH-EPROMs FLASH-EPROMs
  • RAMs read / write memory cells
  • FIGS. 6a to 6d show sectional views for illustrating manufacturing steps for conventional ROM memory cells using so-called “metal programming”.
  • an insulating oxide layer 101 is first formed on a semiconductor substrate 100, on which a structured mask layer 102 for masking 6b, a field oxide layer 103, which separates the active regions from one another, is then produced by thermal oxidation, as shown in FIG. 6c, after the formation of control electrodes 104 and a source / drain implantation mask 107, a source / Drain implantation I s / D is carried out, source / drain regions 105 being formed self-aligning in the active region using the control electrodes 104.
  • a multiplicity of transistor memory cells which are not initially programmed, are formed in the semiconductor substrate 100, which are customarily are arranged in a matrix and are controlled via corresponding word and bit lines, not shown.
  • the source and drain region of the right-hand ROM memory cell is short-circuited via a metallization M, as a result of which this ROM memory cell is always evaluated as conductive (logical 1) when read out.
  • the left ROM memory cell has a non-conductive state (logic 0) when read out.
  • FIGS. 7a to 7d Such a conventional manufacturing method for implementing programming by means of a conductive layer in the semiconductor substrate is shown in FIGS. 7a to 7d.
  • an insulating oxide layer 101 with an overlying mask 102 for masking active areas is again provided on a semiconductor substrate 100.
  • a field oxide layer 103 for separating the active regions in the semiconductor substrate 100 is formed thermally.
  • a programming mask 108 is now deposited on the semiconductor substrate 100, the programming mask 108 being etched free on the active regions to be programmed.
  • the active regions thus exposed are doped, as a result of which a conductive implantation region 109 is formed in the semiconductor substrate 100.
  • the control electrodes 104 are formed over the active regions and are generated in a self-aligning manner in the semiconductor substrate 100 using a source / drain implantation (not shown).
  • a passivation or insulating layer 106 protects the ROM memory cells 720 and 721 produced in this way.
  • the source / drain regions 105 in the ROM memory cell 721 are electrically connected by the conductive implantation region 109, which is why when reading this ROM - Memory cell 721 receives the logical value 1.
  • the ROM memory cell 720 has no conductive implantation area 109, which is why it generates the logic value 0 when read out.
  • a ROM memory cell can thus be programmed such that it is very difficult to read out or analyze the memory content.
  • a disadvantage of this conventional production of ROM memory cells is the relatively early point in time for programming. More specifically, the programming of the ROM memory cell according to FIG. 7c takes place in an early process stage, which is followed by a large number of further necessary process steps. Since the implementation of the described manufacturing steps or the production of complex integrated circuits typically takes several months to half a year, this means that the customer must submit the program codes to be implemented relatively early.
  • FIGS. 8a to 8e show sectional views to illustrate the individual method steps for realizing this late programming.
  • the same reference symbols denote the same or corresponding layers or components as in FIGS. 1 and 7, which is why their description is omitted below.
  • an insulating oxide layer 101 with a mask layer 102 for masking active regions is again applied to a semiconductor substrate 100.
  • the active areas are electrically separated from one another by forming a thermal field oxide layer 103.
  • control electrodes 104 are then formed on a gate oxide layer 110 above the active regions, and a source / drain implantation mask 107 for forming source / drain regions is deposited on the surface.
  • the source / drain implant mask 107 in this case acts in conjunction with the control electrode 104 as an implantation mask for a source / drain implant I S / D - Au f this manner, in the semiconductor substrate 100.
  • Source / drain regions 105 formed in a self-aligning manner.
  • a programming mask 108 is deposited over the entire surface and is only etched free above the ROM memory cells to be programmed in such a way that the associated control electrode 104 is exposed.
  • a conductive implantation region 109 is formed between the source / drain regions 105 with a typical energy of approx. 240 keV, whereby, according to FIG. 8e, the programming mask 108 is removed and an insulating layer 106 is deposited the conductive ROM memory cell 821 (logic 1) and the non-conductive ROM memory cell 820 (logic 0) are formed.
  • late programming of ROM Memory cells can be realized, which is also suitable for the production of safety-related circuits.
  • the disadvantage of these conventional production methods is the use of the high-energy programming implantation I * p 2 , in which the implantation region 109 is generated through the control electrode 104.
  • high-energy programming implantation I * p 2 In which the implantation region 109 is generated through the control electrode 104.
  • high-energy implantations cause insulation problems, particularly due to out-diffusion.
  • the invention is therefore based on the object of providing a method for producing ROM memory cells in which late programming can be implemented inexpensively using standard processes.
  • All active areas are preferably selected for the source / drain implantation, while only the active areas to be programmed are selected for the programming implantation are selected, as a result of which a multiply implanted structure is established in the active areas to be programmed, which has a punch-through effect when an operating voltage is applied.
  • a source / drain implantation or a programming implantation can be used for the respective active areas by appropriate mask selection, the programming implantation again being carried out in such a way that the punch-through effect occurs.
  • an LDD (lightly doped drain) implantation can preferably be used to determine the electrical properties of the ROM memory cell, while to form ohmic contacts for the connection lines of the source / drain regions, highly doped connection -Implants are done. In combination with the programming implantation, this results in a triple implantation in the active areas to be programmed.
  • the programming implantation is preferably carried out obliquely under the control electrodes, as a result of which the implantation areas sliding under the control electrode are further improved with regard to the punch-through effect.
  • both p- and n-dopants can also be implanted in such a way that a charge carrier concentration under the control electrode is compensated for or reduced in such a way that a punch-through effect already with a “normal” source / Drain implantation occurs.
  • FIGS. 2a to 2c are sectional views for illustrating a manufacturing method for ROM memory cells according to a second exemplary embodiment
  • FIG. 3 shows a sectional view to illustrate an oblique programming implantation
  • FIG. 4 shows a sectional view for illustrating a production method for ROM memory cells according to a third exemplary embodiment
  • FIG. 5 shows a sectional view for illustrating a production method for ROM memory cells in accordance with a fourth exemplary embodiment
  • FIGS. 6a to 6d are sectional views illustrating a conventional method for manufacturing ROM memory cells
  • FIGS. 7a to 7d are sectional views for illustrating a further conventional method for manufacturing ROM memory cells.
  • FIGS. 8a to 8e are sectional views to illustrate a further production method for ROM memory cells.
  • Figures la to le show sectional views to illustrate the essential method steps for the production of ROM memory cells according to a first embodiment.
  • the same reference numerals designate the same or similar layers or components as in FIGS. 6 to 8, which is why a detailed description is not given below.
  • a semiconductor substrate 100 is first provided, on the surface of which an insulating oxide layer 101 is formed.
  • a mask layer 102 is structured and, according to FIG. 1b, a field oxide layer 103 is formed for separating the active areas by means of thermal oxidation.
  • the field oxide layer 103 can also be produced by shallow trench isolation (STI), an oxide layer being formed in etched-out trenches in a deposition process.
  • STI shallow trench isolation
  • Si is preferably used for the semiconductor substrate, but SOI or a III-V semiconductor can also be used as the substrate.
  • ROM transistor memory cells are formed in the semiconductor substrate 100. These ROM transistor memory cells are preferably arranged in a matrix in the substrate.
  • control electrodes (gate electrodes) 104 are first formed over the respective active areas, only one Gate oxide layer 110 is present between the semiconductor substrate 100 and the control electrode 104.
  • a further source / drain mask layer is then produced photolithographically over the entire surface of the semiconductor substrate 100, so that the control electrodes 104 are completely exposed (source / drain implantation mask 107).
  • a source / drain implantation I s / D is then carried out to form source / drain regions 105 in the semiconductor substrate 100, both the source / drain implantation mask 107 and the control electrodes 104 being used as implantation masks.
  • the source / drain regions 105 are formed laterally under the control electrodes 104 in a self-adjusting manner.
  • the source / drain implantation mask 107 is then removed and a programming mask 108 is applied and structured.
  • the programming mask 108 is etched free on the ROM transistor memory cells to be programmed, and a programming implantation I P is carried out.
  • the control electrodes 104 are also used as a mask in the same way as in the case of the source / drain implantation I s / D.
  • a material is preferably used which has a greater diffusion capacity than the source / drain implantation I s / D with the same conductivity.
  • Ph is preferably used as the programming implantation with a dose of approx. 2 ⁇ 10 and an energy of approx. 30 keV, while As is used as the dopant in the source / drain implantation
  • the programming implantation I P generates a punch-through region 111 in a self-adjusting manner laterally below the control electrode 104 in the semiconductor substrate 100, which extends far below the control electrode 104 and touches almost or completely in a channel area. Accordingly, the programming of the ROM memory cell is essentially achieved by the so-called "punch-through effect", which occurs at the latest when an operating voltage is applied to the transistor cell by collision of the space charge zones of the respective punch-through regions 111.
  • a non-programmed ROM memory cell 120 and a programmed ROM memory cell 121 are produced using implantation and mask steps which are present in any case in standard processes.
  • a late programming of ROM memory cells can be inexpensively produced using standard processes simultaneously with the production of other components of the circuit (EEPROMS, ).
  • FIGS. 2a to 2c show sectional views to illustrate a production method of ROM memory cells according to a second exemplary embodiment, the source / drain implantation furthermore having an LDD implantation (lightly doped drain).
  • FIG. 2a corresponds to a production step according to FIG. 1c, the provision of the semiconductor substrate 100 and the formation of the active areas having already taken place.
  • an LDD implantation of As for example, is first carried out with a dose of 1 ⁇ 10 and an energy of approximately 30 keV.
  • the structure size carries approximately 0.25 microns, ie the width of the control electrode 104 is typically 0.25 microns.
  • LDD regions 112 are accordingly formed over a large area in the entire semiconductor substrate 100 in a self-adjusting manner in the active region.
  • the LDD implantation I LDD for forming the LDD regions 112 essentially determines the electrical properties of the transistor memory cells.
  • a programming mask 108 is generated photolithographically and exposed at the active areas to be programmed in each case.
  • the right ROM memory cell represents a memory cell to be programmed, while the left ROM memory cell is protected by the programming mask 108.
  • I P carried out subsequently, the self-adjusting formation of punch-through regions 111 in the selected active region takes place using the control electrode 104 and the programming mask 108 as masks.
  • I P Ph is preferably used as a dopant with a dose of * 2 ⁇ 10 at an energy of approximately 20 keV. Due to the greater penetration depth of phosphorus and the further diffusion, the punch-through region 111 pushes far below the control electrode 104, whereby it almost or completely touches.
  • the programming mask 108 is then removed and a further source / drain implantation mask 107 is formed, which enables heavily doped source / drain regions 105 to be generated by means of photolithographic structuring over all active regions. More specifically, according to FIG. 2c, after the active areas (source / drain implantation mask 107) have been etched free, spacers or auxiliary layers 113 are respectively formed on the sides of the control electrodes 104 and then a source / drain implantation I s / D is performed. leads.
  • This source / drain implantation I s / D with As is preferably carried out at an energy of approximately 40 keV and a dose of 5 ⁇ 10 15 . In this way, a relatively heavily doped source / drain region 105 is obtained which has an ohmic contact with connecting lines (not shown).
  • the further process steps correspond to the process steps described with FIG. Le, which is why their description is omitted below.
  • ROM memory cells 220 and 221 are thus formed, which can be programmed in a late programming step using standard processes.
  • the strongly diffusing punch-through regions 111 which slide far below the control electrodes 104 of the respective programmed memory cells, contact is made using the "punch-through effect" at the latest when an operating voltage is applied to the ROM memory cells of the respectively programmed source / drain regions 105.
  • the non-programmed ROM memory cells 220 are reliably non-conductive.
  • Sb can also be used in the LDD implantation I LDD , with Ph or / and As preferably being used in the programming implantation I P carried out subsequently. This is particularly due to the fact that both Ph and As penetrate further into the semiconductor substrate than Sb and have a greater diffusion. Accordingly, all dopants which have a greater depth of penetration and a stronger diffusion behavior than the “actual” source / drain implantation (I LDD and I s / D ) are suitable for the programming implantation.
  • a programming implantation I Ps can also be directed obliquely under the control electrode 104 according to FIG Control electrode 104 are sufficient. In this way, the occurrence of the punch-through effect can be achieved even more easily. In particular in standard processes for the production of FLASH EPROMs, such oblique implantations I Ps are present anyway, which is why the programming can be carried out without the use of additional implantation steps in the process.
  • a non-programmed ROM memory cell 320 has only source / drain regions 105, while a programmed ROM memory cell 321 has source / drain regions 105 and the additional punch-through regions 111 '. LDD implantation and the formation of auxiliary layers can therefore also be dispensed with.
  • FIG. 4 shows a sectional view to illustrate a manufacturing method of ROM memory cells according to a third exemplary embodiment, wherein no additional or replacement programming implantation for programming a ROM memory cell is carried out.
  • the method for producing ROM memory cells according to the third exemplary embodiment is particularly suitable when using standard processes with so-called pocket implantation.
  • Pocket implantations of this type are used in particular in the case of highly integrated circuits in which the normally undesired punch-through effect occurs automatically due to short-channel effects.
  • a pocket implantation is therefore created to form pocket regions 113 with opposite conductivity to source / drain regions 112, as a result of which the punch-through effect is reliably prevented becomes.
  • the pocket implantation according to FIG. 4 preferably consists of an oblique implantation with B as the dopant at an angle of approximately 10 degrees.
  • an LDD implantation with As is preferably carried out as the source / drain implantation for forming the source / drain region 112.
  • FIG. 5 shows a sectional view to illustrate a production method for ROM memory cells according to a fourth exemplary embodiment, the implementation of the programming implantation serving less so as to indirectly promote the punch-through effect rather than forming punch-through regions.
  • the manufacturing method according to FIG. 5 is preferably used in the manufacture of CMOS circuits, since in this case both p and n implantations are used to form the complementary MOS structures.
  • these complementary p and n implants which are present anyway, are used for programming ROM memory cells in such a way that the doping concentration in the semiconductor substrate 100 is deliberately reduced on the surface of an active region, as a result of which the space charge zones RLZ of implanted n + source / Automatically spread drain regions 105 more.
  • the dashed region 114 denotes such a lightly doped p ⁇ surface region, which is formed on the surface below the control electrode 104 by implantation of p- and n-dopants in almost the same order of magnitude.
  • the p-substrate 100 is a strongly neutralized p ⁇ region on the surface to the control electrode 104, which is why the space charge zone RLZ of the heavily doped n + - Spread source / drain regions 105 far into these weakly doped p ⁇ regions 114 and finally cause the punch-through effect. Accordingly, a compensation programming implantation is carried out in the production method according to the fourth exemplary embodiment, as a result of which the doping concentration is greatly reduced, in particular in a channel region below the control electrode 104.
  • the invention has been described above using a p-type semiconductor substrate. However, it is not limited to this and can also be implemented in an n-type semiconductor substrate. Only corresponding p and / or n wells are to be provided by the person skilled in the art. Furthermore, the present invention can be applied not only to NMOS but also to PMOS or CMOS circuits, the implantations and dopants being adapted accordingly.

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Abstract

L'invention concerne un procédé de production de cellules de mémoire morte, selon lequel, par la mise en oeuvre de processus standards, il est possible d'effectuer une programmation retardée dans le processus. Cette programmation se fait sensiblement par formation autoréglée de zones de percement (111) dans chaque cellule de mémoire morte (121) à programmer, au moyen d'électrodes de commande (104) servant de masque.
PCT/DE2000/001755 1999-06-28 2000-05-30 Procede de production de cellules de memoire morte WO2001001482A1 (fr)

Applications Claiming Priority (2)

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DE19929675.8 1999-06-28
DE19929675A DE19929675A1 (de) 1999-06-28 1999-06-28 Verfahren zur Herstellung von ROM-Speicherzellen

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0024311A2 (fr) * 1979-08-20 1981-03-04 International Business Machines Corporation Procédé de fabrication de mémoire morte intégrée à haute densité
EP0213983A2 (fr) * 1985-07-29 1987-03-11 STMicroelectronics, Inc. Procédé de personnalisation tardive d'une mémoire morte
DE4311705A1 (de) * 1992-04-13 1993-10-14 Mitsubishi Electric Corp Masken-ROM-Halbleitervorrichtung und Herstellungsverfahren dafür
EP0575688A2 (fr) * 1992-06-26 1993-12-29 STMicroelectronics S.r.l. Programmation des cellules LDD-ROM
US5635417A (en) * 1993-10-25 1997-06-03 Yamaha Corporation Method of making a read only memory device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0478167A (ja) * 1990-07-19 1992-03-12 Nec Corp 半導体記憶装置の製造方法
KR960009994B1 (ko) * 1992-10-07 1996-07-25 삼성전자 주식회사 반도체 메모리 장치 및 그 제조방법
JP2581415B2 (ja) * 1993-10-08 1997-02-12 日本電気株式会社 半導体記憶装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0024311A2 (fr) * 1979-08-20 1981-03-04 International Business Machines Corporation Procédé de fabrication de mémoire morte intégrée à haute densité
EP0213983A2 (fr) * 1985-07-29 1987-03-11 STMicroelectronics, Inc. Procédé de personnalisation tardive d'une mémoire morte
DE4311705A1 (de) * 1992-04-13 1993-10-14 Mitsubishi Electric Corp Masken-ROM-Halbleitervorrichtung und Herstellungsverfahren dafür
EP0575688A2 (fr) * 1992-06-26 1993-12-29 STMicroelectronics S.r.l. Programmation des cellules LDD-ROM
US5635417A (en) * 1993-10-25 1997-06-03 Yamaha Corporation Method of making a read only memory device

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