WO2000070752A1 - Amplificateur numerique - Google Patents

Amplificateur numerique Download PDF

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Publication number
WO2000070752A1
WO2000070752A1 PCT/JP2000/003187 JP0003187W WO0070752A1 WO 2000070752 A1 WO2000070752 A1 WO 2000070752A1 JP 0003187 W JP0003187 W JP 0003187W WO 0070752 A1 WO0070752 A1 WO 0070752A1
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WO
WIPO (PCT)
Prior art keywords
output
supplied
modulator
signal
amplifier
Prior art date
Application number
PCT/JP2000/003187
Other languages
English (en)
Japanese (ja)
Inventor
Hiroyuki Kimura
Original Assignee
Lucent Technologies Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc. filed Critical Lucent Technologies Inc.
Priority to AU47777/00A priority Critical patent/AU4777700A/en
Publication of WO2000070752A1 publication Critical patent/WO2000070752A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/02—Manually-operated control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/331—Sigma delta modulation being used in an amplifying circuit

Definitions

  • the present invention relates to an electronic device, and more particularly, to a digital-amplifier for amplifying and outputting an input signal.
  • class D amplifiers Two types are used. In response to the recent demands for lower power consumption and improved power usage efficiency, low power consumption digital amplifiers and power amplifiers are being considered.
  • a PWM digital amplifier is easier to configure than a ⁇ modulation type. Generally, it is composed of a triangular wave generator and a comparator. It is said that it is difficult to obtain a certain level of accuracy.
  • Fig. 4 shows an example of a modulation-type digital amplifier.
  • Fig. 5 shows an example of the differential output waveform between OP and ON in Fig. 4. The ideal output is a perfect square wave synchronized with the reference clock (Fig. 5a), but the actual output is H level due to delay time, rise and fall time, overshoot, and undershoot. If the output is repeated for several clocks, it will not be an integral multiple of that of one clock, and this will cause distortion (Fig. 5b).
  • FIG. 5d is a diagram for explaining a general error.
  • Modulation digital ⁇ Three methods are known as methods for adjusting the gain of an amplifier. (1) Adjusting the gain or attenuation of the signal before modulation using a variable resistor, etc. (2) Adjusting the signal by digital operation after modulation, (3) Adjusting the power supply voltage of the output stage ( Figure 4).
  • the method (2) has a problem that when a circuit is not prepared in advance for another operation, a new multi-bit digital operation circuit is required.
  • the operation of the modulation circuit has the advantage that it can be designed independently without affecting the power.To improve the efficiency of power use
  • a variable high-efficiency DCZDC comparator 32 (Fig. 4) must be used for the output transistor 33 (Fig. 4) in the power supply circuit, and the output stage of the ⁇ modulation circuit is similar in a wide range of power supply voltage. There is a problem that it is difficult to generate a shaped output wave.
  • DCZDC converters are complex.
  • power transistors must usually be used inside the DCZDC converter.
  • the digital amplifier of the present invention comprises: ( ⁇ ) a modulator (11) to which an input signal and a synchronization signal are supplied; and ( ⁇ ) a PWM to which a gain control input signal and a synchronization signal are supplied and which controls a duty cycle.
  • a pulse amplifier (15) for outputting a plurality of states as a difference output between the two outputs.
  • the digital amplifier according to the present invention comprises: a ⁇ modulator (11) to which an input signal and a synchronization signal are supplied; and ( ⁇ ) a gain control input signal and a synchronization signal.
  • An input signal comprising: a PWM modulation circuit (14) for controlling a duty cycle; and (C) a logic circuit (17) supplied with signals from the ⁇ modulator and the PWM modulation circuit and performing a logical operation on the signals.
  • FIG. 1 is a block diagram showing a configuration of a digital amplifier according to an embodiment of the present invention.
  • FIG. 2 is a digital waveform diagram at each stage of the digital amplifier of FIG.
  • FIG. 1 is a block diagram showing an example of a ternary output type ADC used in a configuration of a digital amplifier according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing an example of a conventional digital amplifier.
  • Example of differential output waveform between ⁇ ⁇ P and ON in Fig. 4. (A) ideal output, (b) actual output, (c) conventional solution, (d) — for explaining general errors.
  • FIG. 1 the signal input V sig to the ⁇ modulator 11 and the synchronization signal CL for timing control are
  • the output of the comparator 22, that is, the output (C) of the PWM type modulation circuit 14 is supplied to one input of the logic circuit 17.
  • the logic circuit 17 receives the ternary quantized signals bitH and bitL from the ⁇ modulator 11 and the signal C from the PWM type modulation circuit 14, and outputs the outputs D and E to the pulse amplifier 15 using AND1 and AND2.
  • Output to The pulse amplifier 15 is provided with driver circuits DR VI and DRV 2 to which the output of the logic circuit 17 is input and which transmits the output to the next-stage output transistor, and output transistors M 1 to M 4 controlled by the driver circuits.
  • the low-pass filter 18 suppresses unnecessary waves at the output of the pulse amplifier 15. Then, the signal amplified by the load LOAD is used.
  • the output of the A ⁇ ADC 11 is composed of two bits, an output bit (bit H) for giving a positive output and an output bit (bit L) for giving a negative output.
  • bit H an output bit
  • bit L an output bit
  • the zero output is obtained by disabling these two bits.
  • a ternary value is generated by two bits, b i tH and b i t L.
  • This PWM type gain control amplifier outputs an H level in synchronization with the clock, and then outputs an L level at a certain time before the next clock signal so that the duty cycle is in accordance with the gain control signal.
  • the maximum value of this duty cycle shall be less than 100%.
  • the output stage control logic circuit 17 uses the logical product of the output bitH of the A ⁇ ADC and the PWM output as the positive-phase output, and calculates the logical product of the output bit L of the A ⁇ ADC 11 and the PWM output. Signals are transmitted to the two driver circuits DRV1 and DRV2 in the next pulse amplifier 15 as outputs on the negative phase side.
  • the driver circuits DRV1 and DRV2 have a two-channel configuration with equivalent performance for positive-phase output and negative-phase output.
  • One channel has a 1-bit logic input followed by an output that controls the transistor connected to the positive power supply (output to Ml and M3) and an output that controls the transistor connected to the negative power supply (output to M2 and M4) ) And two outputs, and the following two output transistor outputs are configured so that the rising and falling of the output can be balanced.
  • the differential output of the two sets of output transistors returns to 0 once per clock, so that the “H” level or “L” level output Even if are consecutive, the output is always an integer multiple of the H level or L level output for one clock, so linearity is maintained and high accuracy is maintained.
  • the non-linearity of PWM does not affect the magnitude of H level, L level, and 0 level for each clock, so it does not affect the distortion of this digital amplifier itself, and is designed separately. There is also the advantage that you can.
  • the SN ratio can be improved by 3.52 dB compared to the binary configuration without impairing the accuracy.
  • the SN ratio is
  • the configuration of FIG. 1 according to the present invention does not require the DCZDC converter 32, and has a simple structure, and uses the DCZDC converter of FIG.
  • the role of the power transistor is shared by the pulse amplifiers 15 M1 to M4.
  • FIG. 2 is a diagram illustrating an example of a waveform at each stage of the digital amplifier in FIG. The operation of the digital amplifier will be described for each waveform.
  • the sawtooth wave generation circuit 16 inside the PWM type modulation circuit 14 generates the sawtooth wave A synchronized with CLOCK.
  • FIG. 3 shows an example of the ternary quantizer 13 of the ternary ADC used in the digital amplifier of the present invention.
  • the reference voltage V REF —H is connected to the inverting input of the comparator COMP 1
  • the reference voltage V REF — L is connected to the non-inverting input of the comparator COMP 2.
  • Input V IN is connected to the non-inverting input of comparator COMP 1 and the inverting input of comparator COMP 2.
  • DFF receives the outputs of comparators COMP1 and COMP2 and the synchronization signal CLOCK for evening control, and outputs a ternary quantization signal at bitH and bitL.
  • the ternary quantized signal output at this bitH, bit L is V IN force (1) V REF — higher than H, (2) V REF- one H and V REF — between, (3) Output three values according to each case when it is lower than VREF_L .
  • V 0P -V s (L level)
  • V 0N -V s (L level)
  • VQP ⁇ Vn OMN "0 0 (0)
  • V 0P— V 0N 0 (0)
  • the present invention is not limited to the configuration described in the above embodiment, and other configurations are possible.
  • the ⁇ ⁇ modulator 11, the PWM modulation circuit 14, the logic circuit 17, and the pulse amplifier 15 may have internally modified forms. Can be changed to be one component.
  • the digital amplifier of the present invention is configured as described above, it solves such disadvantages of the conventional circuit and easily realizes high-output and wide-range gain control with high accuracy and low distortion. It became possible to do.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention se rapporte à un amplificateur numérique à sortie haute tension et à rendement élevé, dont il est facile d'ajuster le gain tout en conservant les caractéristiques de haute précision et de faible distorsion. Cet amplificateur numérique est une combinaison d'un modulateur ΔΣ à sortie ternaire et d'un amplificateur à modulation d'impulsions en durée (PWM) et il permet de régler le gain tout en conservant des caractéristiques de haute précision et de faible distorsion. Cet amplificateur numérique comporte (A) un modulateur ΔΣ (11) recevant un signal d'entrée et un signal de synchronisation, (B) un circuit de modulation PWM (14) recevant un signal d'entrée de commande du gain ainsi que le signal de synchronisation et conçu pour commander le cycle de fonctionnement, (C) un circuit logique (17) recevant les signaux du modulateur ΔΣ et du circuit de modulation PWM et conçu pour effectuer une opération logique de ce circuit, et (D) un amplificateur d'impulsions (15) recevant des signaux du circuit logique et conçu pour délivrer des états représentatifs de la différence entre les deux sorties.
PCT/JP2000/003187 1999-05-18 2000-05-18 Amplificateur numerique WO2000070752A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU47777/00A AU4777700A (en) 1999-05-18 2000-05-18 Digital amplifier

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11/137810 1999-05-18
JP13781099 1999-05-18

Publications (1)

Publication Number Publication Date
WO2000070752A1 true WO2000070752A1 (fr) 2000-11-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/003187 WO2000070752A1 (fr) 1999-05-18 2000-05-18 Amplificateur numerique

Country Status (2)

Country Link
AU (1) AU4777700A (fr)
WO (1) WO2000070752A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005210280A (ja) * 2004-01-21 2005-08-04 Matsushita Electric Ind Co Ltd 電力増幅装置
US7119525B1 (en) 2005-08-29 2006-10-10 Fujitsu Limited Control circuit of DC—DC converter and its control method
CN100344166C (zh) * 2003-04-16 2007-10-17 华为技术有限公司 一种调制解调方法及装置
JP2008522544A (ja) * 2004-12-01 2008-06-26 クリエイティブ テクノロジー リミテッド 電力乗算器装置及び方法
JP2009171450A (ja) * 2008-01-18 2009-07-30 Asahi Kasei Electronics Co Ltd スイッチングアンプ
KR101015724B1 (ko) * 2002-12-20 2011-02-22 소니 주식회사 오디오 앰프
TWI419462B (zh) * 2006-06-16 2013-12-11 Mstar Semiconductor Inc Ｄ類放大器電路
JP2016082338A (ja) * 2014-10-15 2016-05-16 オンキヨー株式会社 デジタルアンプ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06335082A (ja) * 1993-05-18 1994-12-02 Sharp Corp スピーカ駆動装置
JPH10233634A (ja) * 1997-02-20 1998-09-02 Sharp Corp ディジタルスイッチングアンプの駆動方法
JPH10335956A (ja) * 1997-04-02 1998-12-18 Sharp Corp １ビットデジタル信号の音量制御方法および装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06335082A (ja) * 1993-05-18 1994-12-02 Sharp Corp スピーカ駆動装置
JPH10233634A (ja) * 1997-02-20 1998-09-02 Sharp Corp ディジタルスイッチングアンプの駆動方法
JPH10335956A (ja) * 1997-04-02 1998-12-18 Sharp Corp １ビットデジタル信号の音量制御方法および装置

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101015724B1 (ko) * 2002-12-20 2011-02-22 소니 주식회사 오디오 앰프
CN100344166C (zh) * 2003-04-16 2007-10-17 华为技术有限公司 一种调制解调方法及装置
JP2005210280A (ja) * 2004-01-21 2005-08-04 Matsushita Electric Ind Co Ltd 電力増幅装置
JP4566566B2 (ja) * 2004-01-21 2010-10-20 パナソニック株式会社 電力増幅装置
JP2008522544A (ja) * 2004-12-01 2008-06-26 クリエイティブ テクノロジー リミテッド 電力乗算器装置及び方法
US7119525B1 (en) 2005-08-29 2006-10-10 Fujitsu Limited Control circuit of DC—DC converter and its control method
TWI419462B (zh) * 2006-06-16 2013-12-11 Mstar Semiconductor Inc Ｄ類放大器電路
JP2009171450A (ja) * 2008-01-18 2009-07-30 Asahi Kasei Electronics Co Ltd スイッチングアンプ
JP2016082338A (ja) * 2014-10-15 2016-05-16 オンキヨー株式会社 デジタルアンプ

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Publication number Publication date
AU4777700A (en) 2000-12-05

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