WO2000067387A1 - Method for determining the start of a pulse in a spread spectrum system - Google Patents
Method for determining the start of a pulse in a spread spectrum system Download PDFInfo
- Publication number
- WO2000067387A1 WO2000067387A1 PCT/EP2000/004189 EP0004189W WO0067387A1 WO 2000067387 A1 WO2000067387 A1 WO 2000067387A1 EP 0004189 W EP0004189 W EP 0004189W WO 0067387 A1 WO0067387 A1 WO 0067387A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- integration
- symbol
- station
- signal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/7077—Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
- H04B1/70775—Multi-dwell schemes, i.e. multiple accumulation times
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70702—Intercell-related aspects
Definitions
- the invention relates to a station comprising a receiving circuit suitable for a system in which information is transmitted in the form of symbols, which receiving circuit includes a synchronization circuit for producing an indication of the start of a symbol.
- the invention also relates to a synchronization method for determining the start of a symbol.
- the invention finds its application in the industry for cellular radiotelephony networks in which the spread spectrum technique is used, notably the CDMA networks.
- the present invention proposes to simplify to a large extent the synchronization of the receiving stations and to render the synchronization sequences by pilot signal unnecessary.
- such a station is characterized in that said synchronization circuit comprises: a measuring circuit for measuring the energy of the transmitted signal, a first integration circuit for integrating this energy measurement, - a second integration circuit for integrating the output signal of the first integration circuit, a threshold circuit for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
- Fig. 1 represents the diagram of a transmission system comprising a station in accordance with the invention
- Fig. 2 represents the diagram of an adapted filter co-operating with a differential demodulator
- Fig. 3 represents the cascade assembly of the two integrators according to the invention
- Fig. 4 shows the shape of the signals on the input of the first integrator
- Fig. 5 shows the shape of the signals on the output of this first integrator
- Fig. 6 shows the shape of the signals on the output of the second integrator
- Fig. 7 shows a diagram of a processing circuit for establishing the synchronization.
- Fig. 1 represents a transmission system comprising a first station 1 in accordance with the invention communicating with a second station 2.
- the stations 1 and 2 comprise a transmitting part 11 and 12 and a receiving part 14 and 15 respectively.
- Interest particularly goes to the link established by the transmitting part 11 and the receiving part 15.
- This link transmits symbols and uses three paths Tl, T2, and T3, for example.
- Each symbol is formed by one binary element or a group of binary elements interrupted by a spread spectrum code CS formed by chips.
- This code is generated by a code generator 21 at the transmitting end.
- This same code CS is represented in the receiving part 15 by a filter 22 adapted to this code, arranged at the output of the first stages 23 of this receiving part.
- This filter 22 is followed by a differential demodulator 25.
- the adapted filter 22 is formed by two transversal filters 30 and 31 of which each one is assigned to the paths I and Q relating to the in-phase and quadrature phase data respectively, which come from the first stages 23. Only the filter 30 is shown in detail. It comprises a cascade of delay elements 32a, 32b, 32c ... each bringing about a delay equal to one chip period. The various delay elements are multiplied by coefficients C L - ⁇ , C L- , C L - 3 ... Co by means of multipliers 35a, 35b, 35c, ..., 35d. An adder 38 sums the various magnitudes of the outputs of the multipliers 35a, 35b, 35c, ... 35d.
- the value of these coefficients represents the values of the spread-spectrum code CS.
- the two filters produce in-phase signals x2I and quadrature signals x2Q which are applied to the differential demodulator 25 formed by a delay line 40 and 41 respectively, for causing a delay equal to one symbol period.
- Two multipliers 45 and 46 respectively perform the multiplication of the delayed values by the value present on the inputs of the differential demodulator 25. The results produced by these multipliers are then added together by the adder 49 so as to produce the signal A which, for summarizing purposes, is written as:
- A(n) x2I(n-N).x2I(n)+x2Q(n-N).x2Q(n)
- "n" represents the current instant and "N” the length of the delay lines 40 and 41 equal to the length of the spreading code and thus to the duration of one symbol.
- the synchronizing circuit comprises (Fig. 1): a first integration circuit 52 for integrating this energy measurement, a second integration circuit 54 for integrating the output signal of the first integration circuit, a threshold circuit 26 for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
- the structure of the integrators 52 and 54 is shown in Fig. 3. These two integrators integrate the produced values with a value of the demodulator 25. Only the structure of integrator 52 is shown, because that of the integrator 54 may be identical.
- the integrator 52 comprises an accumulator formed by an adder 60 and an accumulation memory 62. This integrator 52 can be re-initialized, the memory 62 is then set to zero under the control of a signal SY.
- the signal SY is also used, but this re-initialization is effected with the output value of the first integrator, one active edge every two active edges of the signal SY.
- the signal SY is processed by a processing circuit 58 (Fig. 1) to provide the synchronization.
- Fig. 4 is shown the shape of the signals A on the output of the demodulator 25.
- the configuration formed by the peaks PI, P2 and P3 described above, which is produced for a symbol SBl that has a first value, will be reproduced for the symbol SB2 that follows and has the same polarity, while it is admitted that the symbol SB2 has the same value as the symbol SBl.
- FIG. 5 shows the signal B on the output of the first integrator 52 whose accumulator is reset to zero with each symbol period, as this has already been described above.
- the signal C present on the output of the integrator 54 it is shown in Fig. 6.
- the accumulator of this integrator 54 is reset to zero every second symbol period and between these two periods the contents of this accumulator are increased by the output value of the first integrator 52. It is thus noticed that a change of polarity of the peaks calls forth a change of the slope of the curve representing the signal C. This is indicated in Fig. 6 by reference BEG.
- This signal is processed by the threshold circuit 56 (Fig. 1).
- Fig. 7 shows the structure of the processing circuit 58.
- This circuit is formed around a counter 80 counting the signals produced by a clock 81 down from D/2+In to -D/2+1.
- the value In is the variable that permits the synchronization, as this will be explained in the following, and D is a function of the capacity of the counter and of the accuracy of the synchronization that one wishes to obtain.
- the active synchronization signal SY appears when the contents of the counter cross zero. It is these contents that in fact prompt the validation of the symbols and thus authorize the re-initialization of the integrators.
- the value Ibt of the counter is sent to the processing unit 90 while passing through a register 91.
- Ibtt Ibt for 0> Ibt > -2b
- Ibtt -2b for Ibt ⁇ -2b
- b represents a stand-by period that is saved before the appearance of the first expected peak that marks the beginning of a symbol.
- This value Ibtt may then be filtered into a magnitude Ibttf as a function of the previous filtered value Ibttf(-1) according to a formula of the type:
- This value In is put in a register 95 to recharge the counter 80 at the end of its count-down cycle, that is to say, after it has reached D/2 - 1.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000616132A JP2002543734A (ja) | 1999-05-04 | 2000-05-01 | スペクトル拡散方式においてパルスの開始を決定する方法 |
EP00931164A EP1095466A1 (en) | 1999-05-04 | 2000-05-01 | Method for determining the start of a pulse in a spread spectrum system |
KR1020017000005A KR20010053361A (ko) | 1999-05-04 | 2000-05-01 | 스펙트럼 확산 시스템 안에서 펄스의 개시를 결정하기위한 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99401088.2 | 1999-05-04 | ||
EP99401088 | 1999-05-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000067387A1 true WO2000067387A1 (en) | 2000-11-09 |
Family
ID=8241967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/004189 WO2000067387A1 (en) | 1999-05-04 | 2000-05-01 | Method for determining the start of a pulse in a spread spectrum system |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1095466A1 (ko) |
JP (1) | JP2002543734A (ko) |
KR (1) | KR20010053361A (ko) |
CN (1) | CN1302483A (ko) |
TW (1) | TW503630B (ko) |
WO (1) | WO2000067387A1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1416638A1 (en) * | 2002-10-30 | 2004-05-06 | Agency for Science, Technology and Research | Method and apparatus for a control signal generating circuit |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI314115B (en) | 2007-09-27 | 2009-09-01 | Ind Tech Res Inst | Method and apparatus for predicting/alarming the moving of hidden objects |
CN102468865A (zh) * | 2010-11-18 | 2012-05-23 | 中兴通讯股份有限公司 | 一种小区搜索粗同步的方法和装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5499273A (en) * | 1995-05-11 | 1996-03-12 | Motorola, Inc. | Method and apparatus for symbol clock recovery from signal having wide frequency possibilities |
US5872808A (en) * | 1995-05-25 | 1999-02-16 | Golden Bridge Technology, Inc. | Apparatus and method for synchronization of direct sequence CDMA signals |
-
2000
- 2000-05-01 EP EP00931164A patent/EP1095466A1/en not_active Withdrawn
- 2000-05-01 WO PCT/EP2000/004189 patent/WO2000067387A1/en not_active Application Discontinuation
- 2000-05-01 CN CN00800762A patent/CN1302483A/zh active Pending
- 2000-05-01 KR KR1020017000005A patent/KR20010053361A/ko not_active Application Discontinuation
- 2000-05-01 JP JP2000616132A patent/JP2002543734A/ja active Pending
- 2000-07-13 TW TW089113989A patent/TW503630B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5499273A (en) * | 1995-05-11 | 1996-03-12 | Motorola, Inc. | Method and apparatus for symbol clock recovery from signal having wide frequency possibilities |
US5872808A (en) * | 1995-05-25 | 1999-02-16 | Golden Bridge Technology, Inc. | Apparatus and method for synchronization of direct sequence CDMA signals |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1416638A1 (en) * | 2002-10-30 | 2004-05-06 | Agency for Science, Technology and Research | Method and apparatus for a control signal generating circuit |
SG121741A1 (en) * | 2002-10-30 | 2006-05-26 | Stmicooelectronics Asia Pacifi | Method and apparatus for a control signal generating circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2002543734A (ja) | 2002-12-17 |
TW503630B (en) | 2002-09-21 |
CN1302483A (zh) | 2001-07-04 |
KR20010053361A (ko) | 2001-06-25 |
EP1095466A1 (en) | 2001-05-02 |
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