TW503630B - Station comprising a receiving circuit for a transmission system working according to a spread spectrum technique and method of determining the start of a pulse - Google Patents
Station comprising a receiving circuit for a transmission system working according to a spread spectrum technique and method of determining the start of a pulse Download PDFInfo
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- TW503630B TW503630B TW089113989A TW89113989A TW503630B TW 503630 B TW503630 B TW 503630B TW 089113989 A TW089113989 A TW 089113989A TW 89113989 A TW89113989 A TW 89113989A TW 503630 B TW503630 B TW 503630B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/7077—Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
- H04B1/70775—Multi-dwell schemes, i.e. multiple accumulation times
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70702—Intercell-related aspects
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- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
503630503630
-- ^~明 本發明與一種包括一接收電路的工作站有 - 適用於以符號形式來傳輸資訊的系統,該接關’該工作站 甩以產生符號起始指^敏風 吹電路包括一 本發明進一步與一種用以決定符號起始 。 、7同步方法有關 本發明適用於使用展頻技術之細胞式無線啦 ,特別是適用於分碼多向近接( CDMi) _級路。電話網路產業 此類型系統浮現的問題在於接收器的同步-^ ~ The present invention and a workstation including a receiving circuit are-suitable for a system for transmitting information in the form of symbols, the connection 'the workstation is thrown to generate a symbol starting finger ^ sensitive wind blowing circuit includes a further invention And one to determine the start of the symbol. 7 and 7 Synchronization Methods The present invention is applicable to cellular wireless using spread spectrum technology, and is especially suitable for code division multi-directional proximity (CDMi) _ class road. Telephone network industry The problem emerging with this type of system is receiver synchronization
號必須經過相位調節成本地時序。因此,必/要接收的符 定傳輸符號的起始。有關此主題,可查閱美^非*精確決 5,712,869。在此專利文件中,藉由前導俨V*專利案號 子15唬來獲得同步No. must pass phase adjustment to local timing. Therefore, the start of the transmitted symbol is required / received. For more information on this subject, see U.S.A., Non-Exact Decisions 5,712,869. In this patent document, synchronization is achieved by the preamble 俨 V * patent case number 15
本發明計劃大幅 信號來再現同步順 因此,此類工作 -一測量電路,用 -一第一積分電路 -一第二積分電路 簡化接收台的同步, 序。 站的特徵在於,該同 以測量傳輸信號的能 ,用以積分該能量測 ,用以積分該第一積 並藉由多餘的前導 步電路包括: 量, 量, 分電路的輸出信號 一 一限定值電路,用以根據該第二積分電路的輸出信號來 產生一收到符號起始。 圖式簡單描述 藉由非限制性範例,參考下文中詳細說明的具體實施例The present invention plans to reproduce the synchronization sequence with a large signal. Therefore, this type of work-a first integration circuit-a second integration circuit-simplifies the synchronization and sequence of the receiving station. The station is characterized by measuring the energy of the transmission signal to integrate the energy measurement, to integrate the first product, and the redundant pre-step circuit includes: the quantity, the quantity, and the output signal of the sub-circuit one by one The limit value circuit is used for generating a received symbol start according to the output signal of the second integration circuit. BRIEF DESCRIPTION OF THE DRAWINGS By way of non-limiting example, reference is made to specific embodiments detailed below.
第5頁 503630Page 5 503630
即可明白本-發明的這些及其他_ 圖式中: 圖Id不包括根據本發明之工作站之傳輸系統的圖式, 圖2顯示與差分解調器合作的適應型遽波器的圖式, 圖3顯不根據本發明之兩個積分電路的串聯组 圖4顯示位於差分解調器之輸入上之信號的形^ , 圖5顯示位於第一積分電路之輸出上之信號的形狀, 圖6顯示位於第二積分電路之輸出上之信號的形狀,以 及 圖7顯示供建立同步之處理電路圖。That is, in these and other drawings of the present invention: Figure Id does not include a diagram of a transmission system of a workstation according to the present invention, Figure 2 shows a diagram of an adaptive chirper in cooperation with a differential demodulator, FIG. 3 shows a series combination of two integrating circuits according to the present invention. FIG. 4 shows the shape of a signal on the input of a differential demodulator. FIG. 5 shows the shape of a signal on the output of a first integrating circuit. The shape of the signal on the output of the second integrating circuit is shown, and FIG. 7 shows a processing circuit diagram for establishing synchronization.
Hiigj兒明 圖1顯示包括與第二工作站2通訊之根據本發明之第一工 作站1的傳輸系統。工作站1及2分別包括傳輪部份丨丨與1 2 ’及接收部份1 4與1 5。請特別注意傳輸部份丨丨及接收部份 15所建立的鏈結。此鏈結傳輸符號並使用三條路徑(例如 T1、T2及T3。每個符號都是由一個二進位元素或一袓二進 位元素所構成,而二進位元素被晶片(chip)所構成的^頻 碼CS中斷。展頻碼CS係由位於傳輸端的碼產生器21所彦生 :相同的展頻碼CS代表由位於接收部份15中的遽、波器2一2節 调此展頻碼,該濾波器2 2位於此接收部份1 5之第一級2 3的 輸出。濾波器2 2接在差分解調器2 5之後。下列的文章中可 能找到有關元件22及25的資料報告: - 1980年3月電氣和電子工程師協會會議記錄第“卷宗第3 號第 328 到 35 3 頁中發表的「Introduct on to spfead_ 503630 五、發明說明(3)Hiigj Fig. 1 shows a transmission system including a first workstation 1 according to the present invention in communication with a second workstation 2. The workstations 1 and 2 include the transfer parts 丨 丨 and 1 2 ′ and the receiving parts 1 4 and 15 respectively. Pay particular attention to the links established in the transmitting section and receiving section 15. This link transmits symbols and uses three paths (such as T1, T2, and T3. Each symbol is composed of a binary element or a binary element, and the binary element is formed by a chip.) The code CS is interrupted. The spreading code CS is generated by a code generator 21 located at the transmitting end: the same spreading code CS represents that the spreading code is adjusted by the chirp and waver 2 to 2 in the receiving section 15, The filter 22 is located at the output of the first stage 23 of this receiving section 15. The filter 22 is connected after the differential demodulator 25. The following articles may find information reports on components 22 and 25: -"Introduct on to spfead_ 503630" in Proceedings of the Institute of Electrical and Electronics Engineers Meeting, March 1980, Volume 3, pages 328 to 353, V. Description of Invention (3)
Spectrum A-R-t i m u 11 i p a t h Techniques and their -Spectrum A-R-t i m u 11 i p a t h Techniques and their-
Application to Urban Digital Radio」,作者是G.L· TURIN 。 -於 VTC 1 9 94 第 36 7 到 370 頁中發表的「An Integrated All Digital Diversity Receiver for Spread Spectrum Communications over Mu 11ipath Fading Channe1s」, 作者是C. MOULEC等。 圖2顯示這些元件的結構。適應型濾波器2 2係由兩個橫 向濾波器3 0及3 1所構成,每個橫向濾波器都被指定給來自 第一階2 3的相位I及Q (其分別與同相及正交相位有關)。圖 中只有詳細顯示濾波器30。其包括串聯的延遲元件32a, 3 2 b,3 2 c ···,每個元件都會引起等於一個晶片週期的-延 遲。藉由乘法器35a,35b,35c,··· ,35d將各種延遲元 件乘係數CL_i,CL_2,CL_3· · · CQ。加法器38計算乘法器35a, 3 5b ’ 3 5c ’…· 35d輸出強度的總和。這些係數值代表展頻 碼CS值。這兩個濾波器產生同相信號χ2ί及正交信號x2Q, 這兩個信號分別被傳送到由延遲線4 〇及4 1所構成的差分解 _益2 5 ’用以導致等於一個符號週期的延遲。兩個乘法器 45及46分別執行延遲值乘差分解調器25輸入上出現之數值 的乘法運异。然後,加法器4 9將這些乘法器產生的結果加 起來,以便產生信號A,基於概述目的,其可以寫成·· A(n)=x2I(n-N).x2I(n)+x2Q(n-N).x2Q(n) 在此公式中,’’ η"代表目前的瞬間,而” N"代表等於擴展碼 長度之延遲線40及4 1的長度,因此等於一個符號的持續時Application to Urban Digital Radio "by G.L.TURIN. -"An Integrated All Digital Diversity Receiver for Spread Spectrum Communications over Mu 11ipath Fading Channe1s" published by VTC 1 9 94 pages 36 7 to 370 by C. MOULEC and others. Figure 2 shows the structure of these elements. The adaptive filter 2 2 is composed of two transversal filters 3 0 and 31, each transversal filter is assigned to the phases I and Q from the first order 2 3 (which are respectively in phase and quadrature phase) related). Only the filter 30 is shown in detail in the figure. It includes delay elements 32a, 3 2 b, 3 2 c ··· in series, each of which causes a delay equal to one wafer period. The multipliers 35a, 35b, 35c, ..., 35d multiply the various delay elements by the coefficients CL_i, CL_2, CL_3 ... CQ. The adder 38 calculates the sum of the output intensities of the multipliers 35a, 3 5b '3 5c' ... 35d. These coefficient values represent the CS value of the spreading code. These two filters generate an in-phase signal χ2ί and a quadrature signal x2Q. These two signals are respectively transmitted to the differential decomposition consisting of delay lines 4 0 and 4 1 _ 2 5 'to result in a signal equal to one symbol period. delay. The two multipliers 45 and 46 respectively perform a multiplication of the delay value by the value appearing at the input of the differential demodulator 25. Then, the adder 4 9 adds up the results produced by these multipliers to generate a signal A, which for the purpose of overview can be written as A (n) = x2I (nN) .x2I (n) + x2Q (nN). x2Q (n) In this formula, "η " represents the current moment, and" N " represents the length of the delay lines 40 and 4 1 equal to the length of the spreading code, and therefore equals the duration of a symbol
503630 五、發明說明(4) 間。根據差〜分解調器2 5產生的資料,並經過處理之後,於 使用者電路2 6中建立有用的資料。 由於多重路徑ΤΙ,T2,T3· · ·及其他的干擾,使得接收 資料的接收難以與本機產生的擴展碼同步。為了協助同步 化’同步電路包括(圖1): -一第一積分電路5 2,用以積分該能量測量, -一第二積分電路54,用以積分該第一積分電路的輸出信 號, 一 一限定值電路26,用以根據該第二積分電路的輸出信號 來產生一收到符號起始信號。 因此,根據脈衝起始信號,可根據處理電路5 8來確定接 收器的同步。 圖3顯示積分電路52及54的結構。這兩個積體電路整合 產生值與差分解調器25值。因為積分電路5 2及54的結構完 全一樣’所以只有顯示積分電路52。積分電路52包括由加 法器6 0及累加記憶體6 2所構成的累加器。積分電路5 2可經 過重新初始化,然後在信號SY的控制下,將記憶體設為 零。為了重新初始化積分電路54,也會使用信號SY,但是 其重新初始化係由第一積分電路5 2的輸出所產生的作用, 每隔兩個信號SY主動邊緣(active edge)產生一個主動邊 緣。信號SY經過處理電路58(圖1)處理後產生同步 。 圖4顯示位於差分解調器25輸出上之信號A的形狀。路徑 丁1、T2及T3分別提供關聯波峰PI、P2及P3,其容許傳播參 數不會太快變更。前述關聯波峰PI、P2及P3所構成的組態503630 V. Description of the invention (4). The data generated by the modulator 25 are decomposed and processed according to the difference to create useful data in the user circuit 26. Due to multiple paths Ti, T2, T3, and other interference, it is difficult to synchronize the reception of the received data with the spreading code generated by the machine. To assist in synchronization, the synchronization circuit includes (Figure 1):-a first integration circuit 5 2 to integrate the energy measurement,-a second integration circuit 54 to integrate the output signal of the first integration circuit,- A limiting value circuit 26 is configured to generate a received symbol start signal according to the output signal of the second integrating circuit. Therefore, based on the pulse start signal, the synchronization of the receiver can be determined according to the processing circuit 58. FIG. 3 shows the structure of the integrating circuits 52 and 54. The integration of these two integrated circuits produces a value of 25 with the differential demodulator. Since the structures of the integrating circuits 52 and 54 are completely the same, only the integrating circuit 52 is displayed. The integrating circuit 52 includes an accumulator composed of an adder 60 and an accumulation memory 62. The integrating circuit 5 2 can be re-initialized, and then the memory is set to zero under the control of the signal SY. In order to re-initialize the integrating circuit 54, the signal SY is also used, but its re-initialization is due to the effect of the output of the first integrating circuit 52, and an active edge is generated every two active edges of the signal SY. The signal SY is processed by the processing circuit 58 (FIG. 1) to generate synchronization. FIG. 4 shows the shape of the signal A on the output of the differential demodulator 25. Paths T1, T2, and T3 provide associated peaks PI, P2, and P3, respectively, which allow the propagation parameters to not change too quickly. The configuration of the aforementioned correlation peaks PI, P2 and P3
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DUJOJU 五、發明說明(5) 係用於產生〜具有第μ 產生具有相同極ί的寸伽,並在符號SB1之後再 SB1的數值相同。因的同時容許符號SB2與符號 ,所以具有負波峰組為態接在之後的符細具有不同的數值 圖5顯示第一接八兩 x 週期都會將第路52出上的信號B ’其中每個符號 迥會將第—積分電路52的累加器重置為零,如前文中 =個圖人顯示第二積分電路54之輸出上出現的信號C。 :::”週期都會將第二積分電路54的累加器重置為 :值ϋ第;兩個符號週期之間,卜積分電路52的輸 立曰、一積分電路54之累加器的内容遞增。因此,往 注思园/皮^峰的極性變化會導致代表信號c之曲線的斜率變月 圖7』示處理電路58的結構。處理電路在計數器別 附近構成,其中計數器8〇&D/2Hn到一 D/2 + l倒數 81產,的信號。數值In是允許同步化的變數,下文t = 一步就明,而β是計數器容量及想要獲得之同步準確度的 函數。$計數器的内容跨越零值時,會出現主動同步X信號 n二^Iw些内合提不符號的確認、,並以此方法授權 積刀,路的重新初始化。當偵測到斜率BEG的變化時,則 會將計數器的Ibt在通過暫存器91時,同時傳送到處理單 元90。於苐一步驟中,處理單元9〇決定數值以讨,所以: 如果 I b t ^ 0,則 i b 11 = 0 如果0$ibt^-2b,則 lbtt = IbtDUJOJU 5. Description of the invention (5) is used to produce ~ with the μ to produce inch-gamma with the same pole, and the value of SB1 is the same after SB1. Because the symbol SB2 and the symbol are allowed at the same time, the negative crest group is in the state. The symbols connected after it have different values. Figure 5 shows that the first period of two x periods will signal 52 on the 52nd path. The sign symbol resets the accumulator of the first-integration circuit 52 to zero, as shown in the figure above. The figure C shows the signal C appearing on the output of the second integration circuit 54. ::: "period will reset the accumulator of the second integration circuit 54 to: the value of the first; between the two symbol periods, the input of the integration circuit 52, the content of the accumulator of an integration circuit 54 is incremented. Therefore, the change in polarity of the peak to the peak of thinking, will lead to the slope of the curve representing the signal c. Fig. 7 "shows the structure of the processing circuit 58. The processing circuit is formed near a counter, where the counter 80 & D / A signal from 2Hn to a D / 2 + l countdown of 81. The value In is a variable that allows synchronization. The following t = one step, and β is a function of the counter capacity and the synchronization accuracy you want to obtain. When the content crosses a zero value, there will be a confirmation of the active synchronization X signal n ^ Iw some internal mention of non-symbols, and this method authorizes the product knife to re-initialize the path. When the change in the slope BEG is detected, then When the Ibt of the counter passes the register 91, it is simultaneously transmitted to the processing unit 90. In the first step, the processing unit 90 determines the value to discuss, so: If I bt ^ 0, then ib 11 = 0 if 0 $ ibt ^ -2b, then lbtt = Ibt
503630 五、發明說明(6) 如〜果 Ibt $-2b,則 Ibtt = — 2b . 其中b表示在標示符號開始的第一預期波峰出現之前所保 留的待命週期。 ; 然後,可根據下列方程式,將數值I bt t過濾成強度 Ibttf,作為前一過濾值1)的函數:503630 V. Description of the invention (6) If ~ Ibt $ -2b, then Ibtt = — 2b. Where b represents the standby period reserved before the first expected peak at the beginning of the marker symbol appears. ; Then, the value I bt t can be filtered into the intensity Ibttf as a function of the previous filtering value 1) according to the following equation:
Ibttf=Ibtt· a+(1- a ) Ibttf(-1) 其中α是小於1的濾波常數。 然後計算數值I η,這是倒數計數器所要採用的關聯值··Ibttf = Ibtt · a + (1- a) Ibttf (-1) where α is a filter constant less than 1. Then calculate the value I η, which is the associated value to be used by the countdown counter ...
IbttxTIbttxT
In: + Γ b 其中Γ數值可媲美同步所構成之迴路的增益。 如果不使用過遽功能’則Iη可具有下列的數值· 如果lbtt=0,則 Ιη=Γ < 如果Ibtt=Ibt,則 IbtxP -f Γ b 如杲Ibtt=-2b,則 In=- Γ 於倒數循環結束時(也就是說,計數值到達D/H $ 則會將數值In放入暫存器95中,以便爯,殖χ 後)’ 1之丹-人填入計數器8 〇中In: + Γ b where Γ is comparable to the gain of a loop formed by synchronization. If you have not used the 遽 function, then Iη can have the following values: If lbtt = 0, Iη = Γ < If Ibtt = Ibt, then IbtxP -f Γ b If 杲 Ibtt = -2b, then In =-Γ is At the end of the countdown cycle (that is, when the count value reaches D / H $, the value In will be placed in the register 95 so that, after the colony χ) '1, the person-fills in the counter 8 〇
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TW089113989A TW503630B (en) | 1999-05-04 | 2000-07-13 | Station comprising a receiving circuit for a transmission system working according to a spread spectrum technique and method of determining the start of a pulse |
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EP (1) | EP1095466A1 (en) |
JP (1) | JP2002543734A (en) |
KR (1) | KR20010053361A (en) |
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TW (1) | TW503630B (en) |
WO (1) | WO2000067387A1 (en) |
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US8044780B2 (en) | 2007-09-27 | 2011-10-25 | Industrial Technology Research Institute | Method and apparatus for predicting/alarming the moving of hidden objects |
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SG121741A1 (en) * | 2002-10-30 | 2006-05-26 | Stmicooelectronics Asia Pacifi | Method and apparatus for a control signal generating circuit |
CN102468865A (en) * | 2010-11-18 | 2012-05-23 | 中兴通讯股份有限公司 | Method and device of cell search coarse synchronization |
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US5499273A (en) * | 1995-05-11 | 1996-03-12 | Motorola, Inc. | Method and apparatus for symbol clock recovery from signal having wide frequency possibilities |
US5627855A (en) * | 1995-05-25 | 1997-05-06 | Golden Bridge Technology, Inc. | Programmable two-part matched filter for spread spectrum |
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2000
- 2000-05-01 EP EP00931164A patent/EP1095466A1/en not_active Withdrawn
- 2000-05-01 WO PCT/EP2000/004189 patent/WO2000067387A1/en not_active Application Discontinuation
- 2000-05-01 CN CN00800762A patent/CN1302483A/en active Pending
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US8044780B2 (en) | 2007-09-27 | 2011-10-25 | Industrial Technology Research Institute | Method and apparatus for predicting/alarming the moving of hidden objects |
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JP2002543734A (en) | 2002-12-17 |
CN1302483A (en) | 2001-07-04 |
KR20010053361A (en) | 2001-06-25 |
WO2000067387A1 (en) | 2000-11-09 |
EP1095466A1 (en) | 2001-05-02 |
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