WO2000054282A1 - Microcontroleur a bit de validation d'ecriture - Google Patents

Microcontroleur a bit de validation d'ecriture Download PDF

Info

Publication number
WO2000054282A1
WO2000054282A1 PCT/US2000/006165 US0006165W WO0054282A1 WO 2000054282 A1 WO2000054282 A1 WO 2000054282A1 US 0006165 W US0006165 W US 0006165W WO 0054282 A1 WO0054282 A1 WO 0054282A1
Authority
WO
WIPO (PCT)
Prior art keywords
programming
microcontroller
memory
recited
circuit
Prior art date
Application number
PCT/US2000/006165
Other languages
English (en)
Inventor
Igor Wojewoda
Joseph W. Triece
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to EP00917817A priority Critical patent/EP1086466A1/fr
Priority to KR1020007012551A priority patent/KR20010071231A/ko
Priority to JP2000604421A priority patent/JP2002539542A/ja
Publication of WO2000054282A1 publication Critical patent/WO2000054282A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G11C16/225—Preventing erasure, programming or reading when power supply voltages are outside the required ranges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Definitions

  • the present invention relates to microcontrollers, and in particular to microcontrollers having internal memory allowing programming of the memory in user mode using a write enable bit.
  • Description of the Background Microcontrollers have been designed having on-chip non- volatile memory, typically in electrically erasable programmable read only memory form (EEPROM and EPROM).
  • EEPROM electrically erasable programmable read only memory form
  • the EEPROM allows the microcontroller to be programmed according to the requirements of an application.
  • the EEPROM also allows revision or complete erasure of the programming. It is important to protect the non-volatile memory in a microcontroller from being accidentally or intentionally programmed or reprogrammed. There have been many approaches in addressing this problem.
  • a microcontroller 100 includes security logic 116 outputting a ROM control signal on the conductor 118 coupled to ROM 110 and an EEPROM control signal on conductor 120 coupled to EEPROM 109.
  • Security logic 116 disables access to EEPROM 109 when the CPU is attempting to program EEPROM 109 while executing code external to the internal ROM 110. Access to the ROM is disabled whenever code is being executed outside of ROM 110.
  • ROM security logic is included in security logic 116 and contains a current address comparator 202 which compares the current address in the program counter 204 to the first and second addresses in a secured address range register. If the program counter address is greater than the first address and less than the second address, the current address is determined to be in the secured address range.
  • the current address comparator outputs a high level logic signal if the current address is in the secured address range and otherwise outputs a low logic level.
  • the circuit monitors when a main power supply voltage is switched to a backup power supply voltage. When the switching occurs, a data protection set released discriminating circuit detects this break in the power supply and enables a data protection control signal to protect the data.
  • This microcontroller includes a low voltage program inhibit (LVPI) circuit which monitors the supply voltage. If the supply voltage falls below a predetermined voltage level, the LNPl circuit inhibits the use of the EEPROM programming register, preventing programming or erasing of the EEPROM.
  • LVPI low voltage program inhibit
  • Another system such as the PIC17C42 manufactured by the assignee of this application contains a separate pin, TEST, for test mode selection control.
  • Another pin, MCLR/V pp acts as the master clear reset input and also accepts the programming voltage during programming mode. In this device programming of the memory occurs during a special mode and is not possible during a normal user mode, and a separate pin is allocated for the test mode selection signal.
  • a reset circuit may also be connected to the register and the detector circuit.
  • the reset circuit may output a signal resetting the register.
  • the reset circuit may also comprise a means for resetting a register only when resetting the microcontroller.
  • the microcontroller may also have an input pin connected to the reset circuit and to the detector circuit.
  • the decoder circuit may also comprise a first input connected to receive an output of the detector circuit and a second input connected to receive an output of the register.
  • the decoder circuit may also include means for outputting a test mode enable signal and a program memory enable signal based upon the outputs of the detector circuit and register.
  • the microcontroller may include a data memory and the register may comprise a memory location in the data memory.
  • the register may also be implemented as a separate register or as a fuse.
  • a method of programming a memory in a microcontroller including the steps of detecting a programming level voltage, determining whether programming of the memory is enabled, and programming the memory after detecting the voltage and determining that the memory has been enabled for programming.
  • the method may also include a step of entering a test mode when a voltage is detected and the memory is not enabled for programming.
  • the invention may further include entering the test mode, enabling the memory for programming and programming the memory while in the test mode.
  • the determining of whether to enter the test mode could be done internally by the microcontroller. Internally determining whether to enter the test mode may be accomplished using the programming level voltage.
  • the microcontroller can be operated in a normal user mode and the memory may be programmed during the normal user mode.
  • the method may also include detecting a program level voltage on an input pin of the microcontroller and multiplexing at least one other signal on the pin, such as a reset signal.
  • a method for increasing functionality in a microcontroller including the steps of identifying first and second input signals required to carry out respective first and second predetermined functions.
  • the first signal is used to carry out the first function and is internally used to determine whether to carry out the second function.
  • the second input signal is eliminated as an input to the microcontroller.
  • This method may also include the step of identifying the first signal as a programming level voltage for programming a memory in the microcontroller, identifying the second signal as a test mode signal and determining whether to enter the test mode using the program level voltage.
  • the test mode select signal may be eliminated as an input signal.
  • Internally using the first signal may include detecting the programming level voltage, determining whether to enable programming of the program memory in the microcontroller, and entering a programming mode when detecting the programming level voltage and determining if programming of the memory is enabled.
  • the program mode may be entered during a normal user mode of the microcontroller, and after entering the test mode.
  • FIG. I is a pin diagram of a microcontroller according to the invention.
  • FIG. 2 is a schematic block diagram of the microcontroller according to the invention.
  • FIG. 3 is a diagram of circuitry in the microcontroller according to the invention.
  • FIG. 4 is a diagram of data memory in the microcontroller according to the invention.
  • FIG. 5 is a timing diagram illustrating operation of the microcontroller according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. I shows a pin diagram of the present invention applied to a microcontroller.
  • This microcontroller is used as an example of a device to which the invention can be applied, and is not to be construed as limiting the invention.
  • reference numeral 10 designates the pin diagram of the microcontroller packaged in a DIP.
  • the microcontroller could also be packaged in other configurations such as a plastic leaded chip carrier or a plastic surface mount package.
  • the pin designations RA0-RA5 correspond to a bidirectional I/O port A. Similar designations are indicated for the bidirectional I/O ports B, C, D and E.
  • the package 10 also includes pins for the power supply (V DD and V ss ), oscillator input and output (OSC1 and OSC2) and a master clear/programming voltage input pin MCLR/ypp.
  • Voltage switch 11 through which either a 5V or 12V power supply is fed to the MCLR/ PP pin.
  • Voltage switch 11 can be implemented with well known circuitry.
  • Switch control line 12 controls switching between the 5V and 12V power sources, and is shown connected to pin RA4 of I/O port A. It is also possible to use another appropriate pin for switching control. The voltage switching is performed under the control of the CPU.
  • the 5V power supply is also fed to the V DD pins and ground is applied to the V ss pins.
  • An oscillator 13 is connected between the OSCI and OSC2 pins to provide the clock input. Oscillator 13 can be a crystal resonator.
  • FIG. 2 also includes PORTA 20, PORTB 21, PORTC 23, PORTD 23 and PORTE 24 each connected to data bus 25.
  • PORTA 20 in this example is a 6-bit wide data port and may be multiplexed with peripheral features of the microcontroller.
  • PORTB 21 and PORTC 22 are 8-bit wide bidirectional ports and may also be multiplexed with peripheral features of the microcontroller.
  • PORTD 23 is also an 8-bit bidirectional port and may also be used as a system bus address/data port.
  • PORTE 24 is a 3 -bit bidirectional port and its pins may be used for such functions as address latch enable, output enable or write.
  • the circuit of FIG. 2 also includes arithmetic logic unit 26 and peripheral devices in block 27.
  • Block 28 includes a number of circuit elements such as the power- up timer, oscillator start-up timer, power-on reset, watch dog timer, brown-out reset and test mode select.
  • MCLR, V DD and V ss pins are connected to block 28. The function of these elements is believed to be well understood and their description are omitted here.
  • the OSC1 and OSC2 pins are input through a buffer 32 to timing generation circuit 31, which is also connected to block 28.
  • Timing generation circuit 31 is also connected to a 4XPLL circuit 30, with circuit 30 being connected to block 28.
  • Precision bandgap reference 29 is connected to block 28. Instructions are decoded using instruction decode and control circuit 33.
  • the memory of the microcontroller consists of two components.
  • the first is program memory 37 which may contain approximately 2M bytes and address and data latches.
  • the program memory may be implemented as either a ROM or EEPROM and holds the software programs executed by the microcontroller. Addresses are input to memory 37 from program counter 40 and table pointer 39 through multiplexer 38. N- level stack 41 is connected to program counter 40.
  • the microcontroller also includes data RAM 44 for storing data used by the microcontroller. Addresses are fed to the data RAM via address multiplexer 43. Selection of the addresses is carried out by register select logic 42.
  • FIG. 2 also shows other latches and registers used in the system such as table latch 36, ROM latch 35 and IR register 34.
  • FIG. 3 A more detailed view of the circuitry in circuit 28 connected to the MCLR pin is shown in FIG. 3.
  • the MCLR signal and the programming voltage levels are applied through pin 50.
  • Arrow 51 indicates the connection of the program voltage to the appropriate circuitry for programming information into the program memory.
  • a high voltage detection circuit 52 connected to pin 50 detects the programming voltage level. This can be performed any number of ways. For example, the detect circuit 52 can look for an absolute voltage level (i.e, greater than, for example, 12 volts) or cart look at a voltage difference between two voltages. In this case the voltage could be compared to the supply voltage and if the difference is greater than a certain amount, the input voltage can be detected as the programming voltage.
  • This circuitry is typically comprised of a mix of analog and digital components such as simple comparators and voltage references and consisting of transistor threshold and/or resistor dividers.
  • Reset logic 53 Also connected to pin 50 is reset logic 53.
  • Reset logic carries out resetting of the microcontroller when an appropriate signal is applied to pin 50. For example, during normal operation the power supply voltage could be applied to pin 50. If the voltage on pin 50 is dropped to the ground level, the reset logic could detect this as the appropriate reset signal and carry out resetting.
  • decode logic 54 Connected to the output of high voltage detect circuit 52 is decode logic 54.
  • Decode logic may be implemented with basic digital circuitry. This circuit generates two outputs: Test_Enable and Longwrite_Enable. These signals are generated based upon the inputs from high voltage detect circuit 52 and longwrite enable register 55. Activating the Test_Enable signal places the microcontroller in the test mode while activating the Longwrite_Enable signal allows programming of the program memory 37.
  • decode logic 54 activates the Test Enable signal. Once the test mode is enabled, if the Longwrite bit (LWRT) is activated, decode circuit 54 will maintain the test enable signal active and the Longwrite enable signal will also become active.
  • LWRT Longwrite bit
  • the device allows programming of program memory 37 in test mode.
  • the Longwrite_Enable signal becomes active but the test enable does not activate.
  • Programming of memory 37 can thus take place while the microcontroller is in normal user mode, i.e., when executing instructions in the program memory. In both cases, the Longwrite_Enable will not be active if either the LWRT bit or the high voltage is not present.
  • the normal user mode is where code execution is strictly based upon instructions fetched from the user's program memory (in this example memory 37). In the case of a microcontroller with only internal memory, this mode would be limited to memory 37. When the microcontroller has external code execution capability, an external memory bus may also be present.
  • decode logic 54 where if the test mode is already initiated, activating the LWRT bit does not allow programming in test mode.
  • the programming mode is entered by first activating the LWRT bit and subsequently detecting the high voltage using circuit 52.
  • Longwrite enable register 55 contains the LWRT bit which is set by the user code in the microcontroller to indicate the user desires to program the nonvolatile memory in the program memory. Once the LWRT bit is set, raising the voltage on pin 50 will cause the microcontroller to enter a mode allowing the user to program the program memory while the microcontroller is operating in a normal execution mode.
  • the register which contains the LWRT bit may be implemented in several ways. A separate register may be included in the microcontroller and controlled by the user code executed by the CPU. The existing code of the microcontroller is used to direct information into or read information out of longwrite register 55.
  • the register could also be part of the user data memory, in this case art SRAM cell, where the user can freely read and write the cell.
  • the register could further be implemented as a fuse.
  • Data RAM 44 contains a data latch 46, an address latch 48, and data area 49.
  • a section 47 of data area 49 is designated for special function registers (SFRs).
  • SFRs special function registers
  • the LWRT register resides as part of the user's data RAM area 49 in SFR space 47.
  • the SFRs are used to perform specific functions, such as controlling I/O ports, and any peripherals which are part of the microcontroller.
  • the configuration of the watchdog timer, brown-out reset, etc. can also be controller by the SFRs.
  • Program memory 37 contains a series of instructions specific to the microcontroller's instruction set. These instructions are fetched by the CPU 45 from program memory 37 and are decoded/interpreted by instruction register 34 and instruction decode 33. The specific sequence of instructions will contain directives to present the correct values onto data bus 25 while enabling the LWRT register, indicated as 56 in FIG. 3.
  • register select logic 42 enables the LWRT register in the SFR space 47 and, based upon register select logic 42, an address is presented to memory 44 enabling the SFR which contains the LWRT register. Once the LWRT register is enabled for writing, the value from data bus 25 is transferred into the register.
  • Reset logic 53 is connected to Longwrite enable register 55, Once the LWRT bit is set, it can only be cleared by a physical chip reset. This guards the user from accidentally clearing the bit while the programming voltage levels are present on pin 50, which may cause an undesired change in the execution mode.
  • FIG. 5 A timing diagram illustrating the operation of the device is illustrated in FIG. 5.
  • the MCLR signal is raised from OV to the power supply voltage (in this case 5V), allowing the microcontroller to enter the normal execution mode.
  • the microcontroller is reset by reset logic 53, as described above.
  • the Longwrite enable register is activated. This is indicated by raising the LWRT signal to a high logic level. This signal also represents the case where this value is written into the register or the data memory and is recognized as enabling programming of the program memory 37.
  • the Longwrite enable register 55 indicates to decode logic 54 that the LWRT bit has been activated.
  • the switch line is activated to apply the program level voltage to the MCLR pin 50. As, discussed above, activating the switch line could occur before the LWRT bit is set, or during test mode. As shown in FIG. 5, the MCLR signal is then raised to 12V. This causes high voltage detect circuit 52 to indicate to decode logic 52 the presence of the programming level voltage. The Longwrite_Enable signal is thus activated, in this case being set to a high level. Programming of the program memory 37 is now possible.
  • the MCLR signal is returned to OV to reset the LWRT bit. Both the LWRT and the Longwrite Enable voltages will then return to OV.
  • a signal the programming voltage, is required for carrying out a predetermined function, in this case programming the program memory. This signal may also be used to instruct the microcontroller to enter either the test enable mode. Such instruction in the past has been carried with a separate test mode select signal.
  • the Longwrite enable mode is detected by circuitry attached to the pin to which the signal is applied indicate to the chip to enter a particular mode, or carry out separate functions. The present invention thus allows a reduction in the number of pins necessary in order to allow the microprocessor to carry out all intended functions.
  • the reduction of pin count is especially advantageous in the case where one is developing a family of pin-compatible devices.
  • a user has designed a footprint for a microcontroller, freeing up additional pins to allow additional functionality offers the ability to supply more powerful microcontrollers having greater functionality while adhering to the constraints imposed by the user of maintaining pin footprint compatibility.
  • Having upward compatibility is a significant advantage since a user does not have to undertake costly and time-consuming redesign activities when incorporating the newest version of a family of chips, or when he wants or needs the extra functionality.
  • feature upgrades which can be used by modifying the software/firmware rather than hardware are usually preferred.
  • the present invention allows a user to modify the software/firmware in user mode without having to stop normal mode and enter a separate programming mode. Both the functionality of a microcontroller is improved or increased by freeing up a pin and the ability to upgrade or modify the software is improved and made more flexible.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne un microcontrôleur pourvu d'une mémoire programmable en mode utilisateur. Ledit microcontrôleur renferme des circuits permettant de détecter sur une tension de niveau de programmation a été activée. Le microcontrôleur comprend également un registre de validation d'écriture longue renfermant un bit de validation destiné à autoriser ou non la programmation de la mémoire. Lorsque le registre renferme le bit indiquant la validation de la programmation, et lorsque la tension de niveau de programmation est détectée, le microcontrôleur autorise la programmation de la mémoire programme. Cette programmation peut s'effectuer en mode utilisateur. Le signal de tension du niveau de programmation est également détecté pour déterminer si l'on doit passer en mode test. La programmation de la mémoire programme peut également s'effectuer en mode test. L'invention concerne également un procédé de mise en oeuvre d'un microcontrôleur pour la commande de la programmation de la mémoire programme. Le microcontrôleur selon l'invention offre des fonctionnalités améliorées dans la mesure où il détermine s'il faut passer en mode test sans qu'il soit besoin d'un signal d'entrée sélection de mode test.
PCT/US2000/006165 1999-03-09 2000-03-09 Microcontroleur a bit de validation d'ecriture WO2000054282A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00917817A EP1086466A1 (fr) 1999-03-09 2000-03-09 Microcontroleur a bit de validation d'ecriture
KR1020007012551A KR20010071231A (ko) 1999-03-09 2000-03-09 쓰기 인에이블 비트를 갖는 마이크로 컨트롤러
JP2000604421A JP2002539542A (ja) 1999-03-09 2000-03-09 書き込みイネーブルビットを有するマイクロコントローラ

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26470799A 1999-03-09 1999-03-09
US09/264,707 1999-03-09

Publications (1)

Publication Number Publication Date
WO2000054282A1 true WO2000054282A1 (fr) 2000-09-14

Family

ID=23007269

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/006165 WO2000054282A1 (fr) 1999-03-09 2000-03-09 Microcontroleur a bit de validation d'ecriture

Country Status (6)

Country Link
EP (1) EP1086466A1 (fr)
JP (1) JP2002539542A (fr)
KR (1) KR20010071231A (fr)
CN (1) CN1300432A (fr)
TW (1) TW490670B (fr)
WO (1) WO2000054282A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994310B2 (en) 2013-01-21 2015-03-31 Richtek Technology Corporation Motor controller having multi-functional pin and control method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003032089A (ja) * 2001-07-18 2003-01-31 Matsushita Electric Ind Co Ltd リセット機能内蔵マイクロコンピュータ
TWI397855B (zh) * 2008-05-07 2013-06-01 Sunplus Mmedia Inc 減少接腳數之方法以及使用其之微處理器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444664A (en) * 1993-07-13 1995-08-22 Hitachi, Ltd. Flash memory and a microcomputer
US5615159A (en) * 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same
JPH09282302A (ja) * 1996-04-10 1997-10-31 Sanyo Electric Co Ltd マイクロコンピュータ
FR2766594A1 (fr) * 1997-07-24 1999-01-29 Sgs Thomson Microelectronics Dispositif de re-initialisation a commande externe pour une memoire non volatile en circuit integre
US5991849A (en) * 1996-04-10 1999-11-23 Sanyo Electric Co., Ltd Rewriting protection of a size varying first region of a reprogrammable non-volatile memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444664A (en) * 1993-07-13 1995-08-22 Hitachi, Ltd. Flash memory and a microcomputer
US5615159A (en) * 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same
JPH09282302A (ja) * 1996-04-10 1997-10-31 Sanyo Electric Co Ltd マイクロコンピュータ
US5991849A (en) * 1996-04-10 1999-11-23 Sanyo Electric Co., Ltd Rewriting protection of a size varying first region of a reprogrammable non-volatile memory
FR2766594A1 (fr) * 1997-07-24 1999-01-29 Sgs Thomson Microelectronics Dispositif de re-initialisation a commande externe pour une memoire non volatile en circuit integre

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 02 30 January 1998 (1998-01-30) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994310B2 (en) 2013-01-21 2015-03-31 Richtek Technology Corporation Motor controller having multi-functional pin and control method thereof

Also Published As

Publication number Publication date
CN1300432A (zh) 2001-06-20
TW490670B (en) 2002-06-11
KR20010071231A (ko) 2001-07-28
JP2002539542A (ja) 2002-11-19
EP1086466A1 (fr) 2001-03-28

Similar Documents

Publication Publication Date Title
KR100489757B1 (ko) 프로그램 가능한 액세스 보호 기능을 갖는 메모리 장치 및 그 메모리 장치의 동작 방법
JP3277475B2 (ja) 自動電源構成による不揮発性メモリ・カード
EP0912939B1 (fr) Carte a memoire flash
US5826007A (en) Memory data protection circuit
CN100594551C (zh) 保护集成电路免于错误操作的方法和装置
KR100444537B1 (ko) 데이타처리장치
US6505279B1 (en) Microcontroller system having security circuitry to selectively lock portions of a program memory address space
EP0402683B1 (fr) Procédé et appareil de mise à jour de microprogramme résident dans une mémoire EEPROM
US8190840B2 (en) Memory devices with data protection
US5890191A (en) Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory
US6115814A (en) Memory paging scheme for 8051 class microcontrollers
US20060005005A1 (en) Method and apparatus for executing the boot code of embedded systems
US5991849A (en) Rewriting protection of a size varying first region of a reprogrammable non-volatile memory
US5594686A (en) Method and apparatus for protecting data stored in flash memory
US5642480A (en) Method and apparatus for enhanced security of a data processor
US20070133280A1 (en) Semiconductor integrated circuit apparatus and electronic system
US20040186947A1 (en) Access control system for nonvolatile memory
EP1086466A1 (fr) Microcontroleur a bit de validation d'ecriture
US6813191B2 (en) Microcomputer with nonvolatile memory protected against false erasing or writing
KR19990078265A (ko) 마이크로컴퓨터
JPH11507164A (ja) 半導体メモリ装置
JP3695931B2 (ja) マイクロコンピュータ
JP3824295B2 (ja) 不揮発性半導体記憶装置
JP2006277012A (ja) 半導体集積回路
JPS63266562A (ja) 半導体集積回路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 00800556.7

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 2000917817

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020007012551

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2000917817

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020007012551

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1020007012551

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 2000917817

Country of ref document: EP