490670 五、發明說明（1) 〔發明領域〕 本發明係有關於微控制器，更加明確地說明是有關於 具有内部記憶體之微控制器， 〔發明背景〕 是已經設計微控制器為具有晶片上不揮發記憶體 (on-chip non-volatile memory)，在標準上，其呈電可抹 除可粒式化唯讀記憶體（electrically erasable pr〇grarnmable read-only memory，EEPROM 和 EPROM)。EEPROM 是 能使該微處理器依照一個應用例子之規格來程式化。該 EEPROM亦能修正或完全抹除該程式化。保護在一個微控 制器之不揮發記憶體免於意外地或無目的地程式化或再程 式化是很重要。在說明這種問題上，是已經有許多方法。 在美國專利5,808,544是說明一種方法。只當該中央 處理單元（CPU)在執行於該内部之唯讀記憶體（R〇M) 之指令時，在這個微處理器之EEPROM _是可程式化。一 個微處理裔100是含有安全邏輯裝置（security l〇gic) 116 ’其在與ROM 110耦合之導線118上輸出一個R〇m 控制信號，和在與EEPROM 109耦合之導線120上輸出一 個EEPROM控制信號。當該CPU正在使EEPROM 109程 式化，同時執行與該内部ROM 110外接之程式碼時，安， 全邏輯裝置116會使存取到EEPROM 109失效。無論何時 在ROM 110外部執行程式碼，是會使存取到該R〇M失 效。又’ ROM安全邏輯裝置是位於安全邏輯裝置116内 部’並且内含一個目前位址比較器2〇2，該比較器i〇2是 (請先閱讀背面之注意事項再填寫本頁} · •線· 經濟部智慧財產局員工消費合作社印製490670 V. Description of the invention (1) [Field of invention] The present invention relates to a microcontroller, and more specifically to a microcontroller with an internal memory. [Background of the Invention] The microcontroller has been designed to have a chip. On-chip non-volatile memory, on the standard, it is electrically erasable prmgramnmable read-only memory (EEPROM and EPROM). EEPROM enables the microprocessor to be programmed according to the specifications of an application example. The EEPROM can also modify or completely erase the programming. It is important to protect nonvolatile memory in a microcontroller from accidental or unintentional programming or reprogramming. There are many ways to explain this problem. One method is illustrated in U.S. Patent 5,808,544. Only when the central processing unit (CPU) executes the instructions of the internal read-only memory (ROM), the EEPROM of the microprocessor is programmable. A microprocessor 100 includes a security logic device 116 'which outputs a ROM control signal on a wire 118 coupled to the ROM 110 and an EEPROM control on a wire 120 coupled to the EEPROM 109. signal. When the CPU is programming the EEPROM 109 while executing the code externally connected to the internal ROM 110, the safety and full logic device 116 will invalidate the access to the EEPROM 109. Whenever the code is executed outside the ROM 110, access to the ROM is invalidated. Also, 'ROM safety logic device is located inside the safety logic device 116' and contains a current address comparator 200, which is a comparator (Please read the precautions on the back before filling out this page} · • Line Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公爱） 89135A 490670 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 比較在該程式計數器204之目前位址和在一個安全位址範 圍暫存器之第1及第2位址。如果該程式計數器位址是大 於第1位址並且小於第2位址，是決定該目前位址是位於 安全位址範圍。如果該目前位址是位於安全位址範圍，該 目前位址比較器是輸出一個高位準邏輯信號，反之，則輸 出一個低邏輯位準。 其他方法是集中在避免再程式化，其是與供應電源電 壓所不需要之電壓降有關。在美國專利5,349,669是說明 一個如此方法。在此，該電路會監控當一個主供應電源電 壓是轉換到一個備用供應電源電壓。當發生該轉換時，一 個資料保善没疋解除區別電路是會偵測到這個在供應電源 之中斷，並會啟動一個資料保護控制信號來保護該資料。 在美國專利5，199,032是說明另一個例子。這個微控制器 是含有一個低電壓程式禁止（l〇w v〇ltage pr〇gram inhibit ’ LVPI)電路，其會監控該供應電壓。如果該供應 電壓是低於一個預定電壓位準，該LV；RI電路會禁止使用 讓EEPROM程式化暫存器，來防止該EEpR〇M之程式化 或抹除。 > 另一種系統，諸如該PIC17C42，其是由這個申請案 之讓渡者所製成，是内含一個分離端子，測試 (TEST)，來用於測試模式選擇控制。在程式化模式期 間，另一個料，MCLR/Vpp是作為該主要消除重設輸 入，並亦能接收該程式化電壓。在一個特定模式期間，於 這個裝置是使該記憶體程式化，而在一個正常使用相式 -4- ‘紙張尺度適用中國國家標準（CNS)A4 ^Γ?210 X 297公爱 ----------------l·---訂----------線· (請先閱讀背面之注意事項再填寫本頁) A7 B7 該 其 發明說明（ 期間就無法程式化，並分配―個分離端子來用於該測試模 式選擇信號。 〔發明概要〕 本發明之-個目的是提供—個能在使用者模式程式化 之微處理器。 本發明之另-個目的是增加該微處理器之功能，其經 由使輸入端子夕工化，來用於模式選擇之内部偵測，並且 不需要分配-個分離端子來用於模式選擇控制。 本發明之又-個目的是增加一個相容端子系列之諸如 微處理器的裝置之功能。 這些和其他目的是以—個電路來達成，該電路 程式記憶體之微處理器，其具有-個程式記憶 暫存一個電壓偵測器電路，及-個與該暫 予。。U貞測益電路連接之解碼器電路。—個重設電路 ^ eifeuit)亦⑯與《暫存器和該彳貞測n電路相連接。 該重設電路是可以輸出一個信號來重新設定該暫存器 :::路亦可以含有一個裝置來重新設定一個暫存器六 是田在重新设定該微處理器時。該微處理器亦可以具有 -個輸人端子，其是與該重設電路和該_㈣路。 ★該ί碼器電路亦可以含有第^輸入端，其是用來接收 -亥，測益之-個輸出，和第2輪人端，其是用來接收該暫 存σ°之—個輪出。依照該偵測器電路和暫存器之輸出， 解碼器電路亦可以含有裝置綠出—侧試 和-個程式記憶體致能㈣。 ' ^ -----------------^----訂—^-----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 該 號 竹 U670 A7This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) 89135A 490670 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Comparison in the current position of the program counter 204 Address and first and second addresses in a secure address range register. If the program counter address is greater than the first address and less than the second address, it is determined that the current address is in the safe address range. If the current address is in the safe address range, the current address comparator outputs a high-level logic signal, otherwise, it outputs a low-level logic level. The other approach is to focus on avoiding reprogramming, which is related to the voltage drop that is not needed to supply the power supply voltage. One such method is illustrated in U.S. Patent 5,349,669. Here, the circuit monitors when a mains supply voltage is converted to a backup supply voltage. When the conversion occurs, a data protection circuit that does not discriminate the difference will detect this interruption in the power supply and will activate a data protection control signal to protect the data. Another example is illustrated in U.S. Patent 5,199,032. This microcontroller contains a low voltage program inhibit (LVPI) circuit that monitors the supply voltage. If the supply voltage is lower than a predetermined voltage level, the LV; RI circuit will prohibit the use of EEPROM-programmed registers to prevent the programming or erasure of the EEPROM. > Another system, such as the PIC17C42, which is made by the assignor of this application, contains a separate terminal, Test (TEST), for test mode selection control. During the programming mode, another material, MCLR / Vpp is used as the main reset reset input and can also receive the programming voltage. During a specific mode, the memory is stylized in this device, and in a normal use phase -4- 'paper size applies Chinese National Standard (CNS) A4 ^ Γ? 210 X 297 public love ---- ------------ l · --- Order ---------- Line · (Please read the notes on the back before filling out this page) A7 B7 This invention description ( During this period, it cannot be programmed, and a separate terminal is allocated for the test mode selection signal. [Summary of the Invention] One object of the present invention is to provide a microprocessor that can be programmed in the user mode. Another purpose is to increase the function of the microprocessor, which is used to internally detect the mode selection by industrializing the input terminals, and does not need to allocate a separate terminal for the mode selection control. Another purpose is to add the functionality of a device such as a microprocessor that is compatible with a series of terminals. These and other objectives are achieved by a circuit, a microprocessor of the circuit program memory, which has a program memory temporarily. Save a voltage detector circuit, and one with this temporary ... The decoder circuit connected to the gain circuit. A reset circuit ^ eifeuit) is also connected to the "register and the circuit". The reset circuit can output a signal to reset the register. ::: The path can also contain a device to reset a register. Six is when resetting the microprocessor. The microprocessor may also have an input terminal, which is connected to the reset circuit and the circuit. ★ The encoder circuit can also contain a ^ input terminal, which is used to receive-Hai, measured benefit-an output, and the second round of the human terminal, which is used to receive the temporary σ °-a round Out. According to the output of the detector circuit and the register, the decoder circuit may also include the device green-out-side test and a program memory enable. '^ ----------------- ^ ---- Order-^ ----- line (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs Bureau Consumer Consumption Cooperative printed the number of bamboo U670 A7
經濟部智慧財產局員工消費合作社印製 在一個實施例，該微處理器是可以含有一個資料纪情 體，而該暫存器是可以在該資料記憶體含有_個二憶 置。該暫存器亦可以作為-個A離暫存器或作為—健 絲（fuse)。 、双 上述之目的亦可以經由一種下列之方法來達成：使在 一個微控制器之一記憶體程式化之方法，其含有下列之+ 驟：偵測一個程式化位準電壓，決定是否使該記憶體程^ 化’及在偵測該電壓並決定已經啟動該記憶體來程式化: 後使該記憶體程式化。該方法亦可以含有一個下列之步 驟：當偵測到一個電壓且不會啟動該記憶體來程式化時， 是進入一個測試模式。本發明是可以進一步含有：進入該 測試模式，啟動該記憶體來程式化，及使該記憶體程式 化，同時是處於測試模式下。 決定是否進入該測試模式是經由該微處理器在内部處 理。在内部決定是否進入該測試模式是可以使用該程式化 位準電壓來完成。 是能在一個正常使用者模式下運作該微處理器，並在 該正常使用者模式期間是可以使該記憶體程式化。 該方法亦可以含有：在該微處理器之一個輸入端子偵 測一個程式位準電壓，並在該端子使至少一個其他信號多， 工化，諸如一個重設信號。 上述目的亦可以經由一個下列之方法來達成··在一個 微處理器增加功能之方法，其含有下列之步驟··識別第1 和第2輸入信號，其是實施各別之第1和第2預定功能所 -6- 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公爱） ------------------r---訂----；-----線 (請先閱讀背面之注咅？事項再填寫本頁) 490670 經濟部智慧財產局員工消費合作社印製 圖 A7 五、發明說明（5 ) 必需者。是使用第1信號來執行第1功能，並在内部使用 來決定是否執行第2功能。不使用第2輸入信號來作為該 微處理器之-個輸入。這個方法亦可以含有下列之步驟： 識別第1信號來作為一個程式位準電壓，以便使在該微處 理器=個記憶體程式化；識別第2信號來作為一個測試 模式L 5虎並决定疋否使用該程式位準電廢來進入該測試 模式。是可以不使用該測試模式選擇信號來作為一輸入信 號。 在内部使用第1信號是可以含有：债測該程式位準電 壓；決定是否啟動在該微處理器之程式記憶體來程式化； 及當偵測該程式位準電壓和決定是否啟動該記憶體來程式 化0^ 7C進入個転式化模式。在該微處理器之一個正 使用者模式期間’和在進入該測試模式之後，是可以進入 該程式化模式。 〔附圖簡述〕 本發明之更加完整說明及其許多所具有之優點是能很 容易地發現，在參考下列之詳細說明並借助附圖，是能充 分了解相同者，其中： H兄 圖1是-個依照本發明之微處理器的接腳圖. 圖2是-個依照本發明之微處理器的電路方塊圖. 圖3是-個依照本發明之微處理器的電路圖. 圖；Γ是一個依照本發明之在該微處理器的資料記憶體 5是-個時序圖，其朗依照本判之微處理器的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） ----------------l· — (請先閱讀背面之注意事項再填寫本頁) 訂----------線_ 490670 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6) 運作。 〔較佳實施例說明〕 現今參考_，特减圖1，是說明依照本發明之料 處理器。圖1是圖示本發明之一個接腳圖，盆3 /、尺· /¾用到— 個微處理器。是使用這個微處理器來作氣.^ 卬馮一個裝置之伽 子’其是應用本發明者，並且不會形成本發明之限制。 圖1，參考號碼10是設定為該微處理器，复 :°在 /、ί装疋呈一個 DIP，之接腳圖。又，該微處理器是能封裝成其他型式 諸如一個塑膠導線晶片載體或一個塑膠表面安裝=裂 (plastic surface mount package)。該端子指定編號 RA5是對應到一個雙向I/O埠a。類似指定編號是表示該 雙向I/O埠B，C，D及E。是將資訊轉移到和從該雙向Λ I/O埠之端子輸出。該封裝1〇亦含有：供應電源端子 (VDD* Vss)，振盪器輸入和輸出（〇SCl和〇SC2)及 一個主要清除/程式化電壓輸入端子MCLR/VPP 〇 在圖1亦圖示一個電壓開關（voltage switch) u，藉 此，一個5V和12V供應電源是輸入到該MCLR/ 乂叩端 子。是能以習知電路來實施電壓開關u。開關控制線路 12是控制界於該5v和uv電源之間的轉換 (switching) ’且其是圖示連接到〗/〇埠a之rA4端 子。亦可以使用另一個適當端子來用於轉換控制。是在該 CPU之控制下進行該電壓轉換。 亦將該5V供應電源輸入到該vDD端子，且該Vss端 子是與接地連接。在該〇SCi和〇SC2端子之間連接一個 本紙張尺度適用中國國家標準(CNSM4規格（21〇 x 297公爱） -----------------r---訂----；-----線 (請先閱讀背面之注意事項再填寫本頁) A7Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. In one embodiment, the microprocessor may contain a data record, and the register may contain _ two memories in the data memory. This register can also be used as an A-off register or as a fuse. The above-mentioned purpose can also be achieved by a method of programming the memory in a microcontroller, which contains the following + steps: detecting a programmed level voltage and determining whether to make the Program the memory and program the memory after detecting the voltage and determining that the memory has been activated: The method may also include the following steps: When a voltage is detected and the memory is not activated for programming, it enters a test mode. The present invention may further include: entering the test mode, starting the memory to be programmed, and programming the memory while being in the test mode. The decision whether to enter the test mode is handled internally by the microprocessor. Internally determining whether to enter the test mode can be done using the programmed level voltage. It is possible to operate the microprocessor in a normal user mode and to program the memory during the normal user mode. The method may also include: detecting a program level voltage at an input terminal of the microprocessor, and causing at least one other signal to be multiplied and industrialized at the terminal, such as a reset signal. The above purpose can also be achieved by a method of adding functions to a microprocessor, which includes the following steps: identifying the first and second input signals, which are implemented by the respective first and second Book function office-6- This paper size applies to China National Standard (CNS) A4 specification (21〇X 297 public love) ------------------ r --- Order ----; ----- line (Please read the note on the back? Matters before filling out this page) 490670 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of Invention (5) Necessary. The first signal is used to perform the first function, and it is used internally to determine whether to execute the second function. The second input signal is not used as an input to the microprocessor. This method can also include the following steps: identify the first signal as a program level voltage so that the microprocessor = a memory is programmed; identify the second signal as a test mode L 5 tiger and decide 疋No Use this program to level the electrical waste to enter the test mode. It is not necessary to use the test mode selection signal as an input signal. The internal use of the first signal may include: measuring the program level voltage; determining whether to activate the program memory of the microprocessor for programming; and when detecting the program level voltage and determining whether to activate the memory To program 0 ^ 7C into a stylized mode. It is possible to enter the stylized mode during a positive user mode of the microprocessor 'and after entering the test mode. [Brief Description of the Drawings] A more complete description of the present invention and many of its advantages can be easily found. With reference to the following detailed description and the accompanying drawings, one can fully understand the same, of which: Hung Figure 1 Is a pin diagram of a microprocessor according to the present invention. FIG. 2 is a circuit block diagram of a microprocessor according to the present invention. FIG. 3 is a circuit diagram of a microprocessor according to the present invention. It is a timing diagram of the data memory 5 of the microprocessor according to the present invention, which is based on the paper size of the microprocessor in accordance with this judgment. The Chinese National Standard (CNS) A4 specification (210 X 297) is issued. ) ---------------- l · — (Please read the notes on the back before filling this page) Order ---------- Line _490670 A7 Ministry of Economy Printed by the Intellectual Property Bureau Staff Consumer Cooperatives V. Invention Description (6) Operation. [Explanation of the preferred embodiment] Referring now to Fig. 1, a special subtraction is used to illustrate a processor according to the present invention. FIG. 1 is a pin diagram illustrating the present invention. A microprocessor is used in the basin 3, and the ruler. It is this microprocessor that is used to make qi. ^ Feng Feng of a device 'is an inventor of the present invention, and does not form the limitation of the present invention. In Figure 1, the reference number 10 is set to the microprocessor, and:: is a pin map of / and 疋 equipment. In addition, the microprocessor can be packaged into other types such as a plastic wire chip carrier or a plastic surface mount package. This terminal designation number RA5 corresponds to a bidirectional I / O port a. Similar designated numbers indicate the bidirectional I / O ports B, C, D, and E. It is used to transfer information to and output from the bidirectional Λ I / O port terminal. The package 10 also contains: power supply terminals (VDD * Vss), oscillator input and output (〇SCl and 〇SC2) and a main clear / programmed voltage input terminal MCLR / VPP 〇 A voltage is also shown in Figure 1 A voltage switch u, whereby a 5V and 12V supply is input to the MCLR / 乂 叩 terminal. It is possible to implement the voltage switch u with a conventional circuit. The switching control circuit 12 is a control circuit for switching between the 5v and the UV power source, and it is the rA4 terminal connected to the port A as shown in the figure. Another suitable terminal can also be used for switching control. The voltage conversion is performed under the control of the CPU. The 5V supply power is also input to the vDD terminal, and the Vss terminal is connected to ground. Connect a paper standard between the 〇SCi and 〇SC2 terminals to the Chinese national standard (CNSM4 specification (21 × 297 public love) ----------------- r-- -Order ----; ----- line (Please read the precautions on the back before filling this page) A7
經濟部智慧財產局員工消費合作社印製 振湯1， ΑU，以便提供該時鐘脈波輸入。振盪器13是一個 日日體共振器（crystal resonator ) 〇The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed Zhentang 1, ΑU to provide this clock pulse input. The oscillator 13 is a crystal resonator.
、在圖2是圖示一個微控制器ι〇之某些相關元件的更 $詳細方塊圖。從這個附圖是已經忽略元件，其只是為了 簡化。一個CPU 45，其是以虛線來表示，是内容會在下 面更加詳細說明之元件33-36和38-43，並控制該微處理 器之運作。圖2亦含有：p〇RTA 2〇，pR〇TB 2卜p〇RTC 22 ’ P〇RTD 23，及p〇RTC 24，每一者是連接到資料匯流 排25。在這個例子，P〇rTA 20是一個6位元寬資料埠， 且可以經由該微控制器之週邊特性來多工化。P0RTB 21 和P0RTC 22是8位元寬雙向埠，且可以經由該微控制器 之週邊特性來多工化。P0RTD 23亦是一個8位元雙向 埠’且可以用來作為一個系統匯流排位址/資料埠。 ΡΟΙΟΈ 24是一個3位元雙向埠，且其端子是可以用於諸 如位址鎖存致能（address latch enable)，輸出致能或寫入 之功能。 圖2之電路亦含有算術邏輯單元（arithmetic logic unit) 26，和方塊27之週邊裝置。方塊28是含有許多電 路元件，諸如啟動定時器，振盪器啟動定時器，啟動重 没’監控定時器（watch dog timer )，警戒重設（brown: out reset)，及測試模式選擇。MCLR，VDD和Vss端子是 連接到方塊28。是能完全了解這些元件之功能，並在此忽 略它們的說明。該OSC1和0SC2端子是經由一個緩衝器 32來輸入到時序產生電路（timing generation circuit ) -9- 本紙張尺度適用中國國家標準(CNS)A4規格（210 χ 297公爱) " -----------------r---訂----；-----線 (請先閱讀背面之注咅？事項再填寫本頁) 490670 A7 B7 五、發明說明（8) 31，其亦是連接到方塊28。時序產生電路31亦連接到一 個4Xpll電路30，經由電路33來與方塊28連接。精密頻 帶間隙參考（precision bandgap reference) 29 是與方塊 28 連接。是使用指令解碼和控制電路33來使指令解碼。 該微控制器之記憶體是由2個零件所組成。第丨者是 程式記憶體37,其可内含幾乎為2M位元組，和位址及資 料鎖存。該程式記憶體是可以作為一個r〇m和 EEPR0M，並轉㈣微控制||職狀籠程式。是從 程式計數器4G和表格指標器39經由多工器％來將位址 輸入到記憶體37。N層次堆疊（N_levd stad〇 41是連接 到程式計數4〇。該微控制器亦含有資料ram Μ，以便 儲存由該微控制器所使用之資料。歧由位址多工器们 來將位址輸人龍資料RAM。是以暫存器選擇邏輯裝置 42來執行位址之選擇。圖2亦圖示在該系統所使用之其他 鎖存器和暫存器，諸如表格鎖存器36，R〇M鎖存器 IR暫存器34。 f圖3是圖示-個更加詳細之附圖，其是與該mclr 如子連接之電路28的電路。在圖3，是經由端子％來施 加该MCLR信號和_式化電壓位準。箭頭5ι是表 =料化電壓輸人到適當電路之連接，以便將資訊 =到該程式記憶體。與端子5G連接之—壓 是能制到該程式化電壓位準。這是能以任 ^理如’該_電路52是能搜尋_個絕對電壓^ 準（例如，是大於，例如，12v〇lts)，或者注意—個界於 -10- 本紙張尺度適斤關家標準（CNS)XTi^rx 297公^· -----------------r---訂---------線 (請先閱讀背面之注意事項再填寫本頁) 490670 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（9) 2個電壓之間的電壓差。在這個情況下，該電壓是能盘該 供應電壓相比較，如果該電壓差是大於一定量，所偵測到 之輸入電塵是能作為程式化電壓。標準上，這個電路是含 有混合之類比和權位零件，諸如簡易比較器和電壓參考: 並由電晶體臨界及/或電阻分壓器所組成。 重設邏輯裝置53亦是連接到端子5〇。當一個適當電 壓施加到端子50時，重設邏輯裝置是執行該微控制器之 重新設定。例如，在正常運作期間，該供應電源電壓是施 加到端子5()。如果在端子50之電壓是下降到接地位準， 該重設邏輯裝置會偵測到這個情況來作為適當之重設信號 並且重新設定之。 解碼邏輯裝置54是連接到高壓偵測電路52之輸出 端。是可以經由基本權位電路來實施解碼邏輯。這個電路 是產生 2 個輸出· Test-Enable 和 Longwrite-Enable。是依 照來自高壓偵測電路52和長時間寫入致能暫存器55之輸 入來產生這些信號。啟動該Test-Enable信號是會使該微 控制器處於邊測試模式’同時，啟動該Longwrite-Enable 信號是能使該程式記憶體37程式化。當經由電路52偵測 到該高壓位準且尚未啟動該長時間寫入致能暫存器時，解 碼邏輯裝置54是啟動該Test-Enable信號。一旦啟動該測 試模式，如果是啟動該長時間寫入位元（LWRT)，解碼 電路54將維持該測試致能信號為啟動狀態，並且該長時 間寫入致能信號亦將會啟動。在測試模式下，該裝置是能 程式記憶體37程式化。在該情況下，即在該端子50上出 -11- _本紙張尺度適用中ΐ國家標準（CNS)A4規格（210 x 297公釐1 " -----^^ ^-----^ (請先閱讀背面之注意事項再填寫本頁) 490670 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（1〇) 現δ亥南壓之啟動遠LWRT位元’該Longwrite-Enable信 號是啟動，但是不會啟動該測試致能。則會產生記憶體37 之程式化。同時，該微控制器是處於正常使用者模式，例 如’當下在執行在該程式記憶體之指令時。在兩種情況 下，如果不出現該LWRT位元和該高壓，將不會啟動該 Longwrite-Enable 〇 該正常使用者模式，即程式碼執行是嚴格依照從該使 用者之程式記憶體（在這個例子是記憶體)所取得 (fetch)之指令。在一個只具有内部記憶體之微控制器的 情況’這個模式是限制在記憶體37。當該微控制器是具有 外部程式碼執行能力時，是可以設置一個外部記憶體匯流 排。 亦是能夠設置解碼邏輯裝置54’即如果已經啟動該 測試模式，啟動該LWRT位元是不會在測試模式下程式 化。是經由首纽動該LWRT位元並且隨後制電路％ 來偵測該高壓，以便進入該程式化模式。 - 長時間寫人致能暫存器55是内含該LWRT位元，里 是能經由該微控制器之使用者程式碼來設定，表示該使用 者是想使該程式記憶體之不揮發記憶體程式化。一旦設定 該LWRT位元，提昇在端子5〇之電壓是會使該微控制器 進入-個下狀使該使財料化雜式記憶體， 同時，該微控制器是在一個正常執行槿々 _ 吼仃杈式下運作該微控制 益。是能以許多方式來實施内含該LWRT位元之暫存器。 在該微控制H是可以含有-個分離暫存器，並且由該^ 本紙張尺度關家標準（CNS)A4規格io x 297公釐γ (請先閱讀背面之注意事項再填寫本頁) 訂---------線| 五、發明說明（u) 所執打之使用者程式竭來控制。是使用該微控制器之現存 程式碼來將資訊寫入到長時間致能暫存器55或者從長時 2能暫存11 55讀取資訊。該暫存H亦能是部分之使用 貝料記憶體，在這個情況下，是-個SRAM晶胞 (cell)即該使用者是能自由讀取和寫人到該晶胞。該 暫存器是能進-步作條紐絲（fuse)。 在圖4是圖示下列之情況，即在資料RAM 44實施該 WRT暫存A。資料RAM 44是內含—個資料鎖存器46， ^個位址鎖存器48，及資料區域49。資料區域49之一個 區羧（section) 47是指定為特定功能暫存器（SFRs)。在 SFR空間47’該⑽灯暫存以駐留在部分之使用者資 料RAM區域49。是使用該舰來處理特定功能，諸如 控制I/O埠’和任何週邊裝置，其是部分之微控制器。亦 月bk由該SFRs來控制該監控定時器，警戒重設，等等之 組悲（configuration )。 現今說明寫入該LWRT位元。程式記憶體37是内含 串列針對該微控制器之指令組的指令。是經由該cpu 45攸程式5己憶體37取得這些指令，並以指令暫存器％和 指令解碼器33來解碼/解讀（dec〇de/interpret)。該特定 序列之才曰+是内含指示方肖（directives)纟使該正確值顯， 示在資料匯流排25，同時啟動該LWRT暫存器，如同在 圖3之56所表示般。在該lWRT暫存器是駐留在記憶體 44暫存為選擇邏輯裝置42會使在該证尺空間47之 LWRT暫存器啟動，並且依照暫存器選擇邏輯裝置42，記 -13- 本紙張尺度適ffl巾關家標準（CNS)A4規格（210 X 297公爱) 490670 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（12) 憶體44是顯示一個位址，其會使内含該LWRT暫存器之 SFR啟動。一旦啟動該LWRT暫存器來用於寫入，來自資 料匯流排25之數值是轉移到該暫存器。 重設邏輯裝置Μ是連接到長時間寫入致能暫存器 55。一旦設定該LWRT位元，是只能以一個實體晶片重新 設定來清除。這個會保護該使用暫免於意外清除該位元， 同時在端子50上顯示該程式化電壓位準，其會在該執行 模式造成一個不需要之變動。 圖5是說明一個時序圖，其是說明該裝置之運作。在 啟動該晶片之後，該MCLR信號是從〇V提昇到該供應電 源電壓（在這個情況為5V)，其能使該微控制器進入該 正常執行模式。最初，當該MCLR信號是在OV時，是以 重设邏輯裝置53來重新設定該微控制器，就如同上述 般。在某些時刻，當運作時，是啟動該長時間寫入致能暫 存器。這是經由使該LWRT信號提昇到一個高邏輯位準來 表示。這個信號亦表示下列之情況：將這個數值寫入到兮 暫存器或該資料記憶體，並確認為啟動該程式記憶體 之程式化。 在這個時刻，該長時間寫入致能暫存器55會指示解 碼邏輯裝置54已經啟動該LWRT位元。在下一個執行， 微控制器之程式的時刻，是啟動該開關線路，以便將今^ 式位準電壓施加到該MCLR端子50。如同上述所^曰 般，在設定該LWRT位元之前，或在測試模式期間，是會 啟動该開關線路。如同圖5所示般，接著是將該广 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公髮） -----------------r---tl---------線41^* (請先閱讀背面之注意事項再填寫本頁：> 490670 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（Π) 號提昇到12V。這會使高壓偵測電路52指示解碼邏輯裝 置52是存在該程式化位準電壓。在這個設定為一個高位 準之情況下，則啟動該Longwrite-Enable信號。現今是可 以使該程式記憶體37程式化。 雖然在圖5並無圖示如此，依照該Longwrite-Enable 信號之啟動，會使該MCLR信回到〇V，以便重新設定該 LWRT位元。接者’該LWRT和該Longwrite-Enable電壓 會回到OV。 在本發明，在使該程式記憶體程式化之情況下，是需 要一個信號，該程式化電壓，來執行一個預定功能。亦可 以使用這個信號來指示該微控制器進入該測試致能模式。 過去之如此指令是已經具有一個不同之測試模式選擇信 號。經由與該信號所施加之端子連接的電路，來偵測該長 時間寫入致能模式，其指示該晶片進入一個特定模式，或 執行不同之功能。本發明則會減少所需端子數目，以便使 該微控制器執行所有想要的功能。 在下列之情況下，即有人想發展一個相容接腳裝置之 私群’減少接腳數目是特別有用。一旦一位使用者是已柄 設計一個用於一微控制器之接腳配置（f〇〇tprint)，空出 額外接腳來使額外功能能提供下列之能力：提供更多具有 更佳功能之強大微控制器，同時附加經由該使用者所添加 之維持端子零件尺寸相容性的限制。具有向上相容性 (upward compatibility)是一個實質優點，因為一位使用 者並不需要從事高成本和浪費時間之重新設計行為，當與 (請先閱讀背面之注意事項再填寫本頁) 訂-------！線^ -15-Fig. 2 is a more detailed block diagram illustrating some related components of a microcontroller. Elements have been omitted from this drawing, they are just for simplicity. A CPU 45, which is indicated by a dotted line, is an element 33-36 and 38-43 whose content will be described in more detail below, and controls the operation of the microprocessor. Figure 2 also contains: PORTA 20, pROTB 2 and PORTC 22 'PORTD 23, and PORTC 24, each of which is connected to a data bus 25. In this example, Porta 20 is a 6-bit wide data port and can be multiplexed via the peripheral features of the microcontroller. P0RTB 21 and P0RTC 22 are 8-bit wide bidirectional ports and can be multiplexed by the peripheral features of the microcontroller. P0RTD 23 is also an 8-bit bidirectional port ’and can be used as a system bus address / data port. ΡΟΙΟΈ 24 is a 3-bit bidirectional port, and its terminals can be used for functions such as address latch enable, output enable or write. The circuit of FIG. 2 also includes an arithmetic logic unit 26 and peripheral devices of block 27. Block 28 contains many circuit components, such as a start timer, an oscillator start timer, a watch dog timer, a brown: out reset, and a test mode selection. The MCLR, VDD and Vss terminals are connected to block 28. You can fully understand the functions of these components and ignore their description here. The OSC1 and 0SC2 terminals are input to the timing generation circuit through a buffer 32. -9- This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 public love) " ---- ------------- r --- Order ----; ----- line (Please read the note on the back? Matters before filling out this page) 490670 A7 B7 V. Invention Explanation (8) 31, which is also connected to block 28. The timing generation circuit 31 is also connected to a 4Xpll circuit 30, and is connected to the block 28 via the circuit 33. A precision bandgap reference 29 is connected to block 28. The instruction decoding and control circuit 33 is used to decode the instructions. The memory of the microcontroller is composed of 2 parts. The first is program memory 37, which can contain almost 2M bytes, and address and data latches. The program memory can be used as a ROM and EEPR0M, and can be transferred to the micro control || The address is input to the memory 37 from the program counter 4G and the table pointer 39 via the multiplexer%. N-level stacking (N_levd stad〇41 is connected to the program count 40. The microcontroller also contains data ram M in order to store the data used by the microcontroller. The address multiplexers will assign the address The input data RAM. The address selection is performed by the register selection logic device 42. Figure 2 also illustrates other latches and registers used in the system, such as table latch 36, R 〇M latch IR register 34. f FIG. 3 is a more detailed drawing, which is a circuit of a circuit 28 connected to the mclr such as a sub. In FIG. 3, this is applied via terminal%. MCLR signal and _-type voltage level. The arrow 5m is the connection between the input voltage and the appropriate circuit, so that information = to the program memory. The connection to the terminal 5G-the voltage can be made to the program Voltage level. This can be used for any reason such as' The _ circuit 52 is able to search for _ absolute voltage standards (for example, is greater than, for example, 12v〇lts), or note-a boundary in -10- this paper Standards suitable for home care standards (CNS) XTi ^ rx 297 public ^ · ----------------- r --- order --------- line (please Read first Please note this page, please fill in this page again) 490670 Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs, V. Description of Invention (9) The voltage difference between two voltages. In this case, the voltage can be compared with the supply voltage phase. In comparison, if the voltage difference is greater than a certain amount, the detected input dust can be used as a stylized voltage. Standardly, this circuit contains mixed analog and weight parts such as a simple comparator and a voltage reference: The transistor threshold and / or resistance voltage divider is composed. The reset logic device 53 is also connected to the terminal 50. When an appropriate voltage is applied to the terminal 50, the reset logic device performs a reset of the microcontroller. For example, during normal operation, the supply voltage is applied to terminal 5 (). If the voltage at terminal 50 drops to the ground level, the reset logic device will detect this as a proper reset signal And reset it. The decoding logic device 54 is connected to the output of the high-voltage detection circuit 52. The decoding logic can be implemented through the basic weight circuit. This circuit It generates 2 outputs. Test-Enable and Longwrite-Enable. These signals are generated according to the input from the high-voltage detection circuit 52 and the long-time write enable register 55. Enabling the Test-Enable signal causes the The microcontroller is in the edge test mode. At the same time, activating the Longwrite-Enable signal can program the program memory 37. When the high voltage level is detected by the circuit 52 and the long-time write enable temporary storage has not been activated The decoder logic device 54 activates the Test-Enable signal. Once the test mode is activated, if the long-time write bit (LWRT) is activated, the decoding circuit 54 will maintain the test enable signal in the enable state, and the long-time write enable signal will also be activated. In test mode, the device can be programmed with Program Memory 37. In this case, that is to say on the terminal 50 -11- _ This paper size applies the China National Standard (CNS) A4 specification (210 x 297 mm 1 " ----- ^^ ^ ---- -^ (Please read the precautions on the back before filling this page) 490670 A7 B7 Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (1) Now δ Hainan Press's start-up far LWRT bit' The Longwrite -Enable signal is enabled, but the test will not be enabled. The programming of memory 37 will be generated. At the same time, the microcontroller is in normal user mode, such as 'currently executing instructions in the program memory' In both cases, if the LWRT bit and the high voltage are not present, the Longwrite-Enable will not be activated. The normal user mode, that is, the code execution is strictly in accordance with the program memory of the user ( In this example, the instructions are fetched. In the case of a microcontroller with only internal memory, this mode is limited to memory 37. When the microcontroller has external code execution capabilities When, yes Set an external memory bus. It is also able to set the decoding logic device 54 ', that is, if the test mode has been activated, the LWRT bit is not programmed in the test mode. The LWRT bit is moved through the first button and Then the circuit% is detected to detect the high voltage in order to enter the programming mode.-The long-time write enable register 55 contains the LWRT bit, which can be accessed by the user code of the microcontroller. The setting indicates that the user wants to program the non-volatile memory of the program memory. Once the LWRT bit is set, increasing the voltage at terminal 50 will cause the microcontroller to enter the following state to make the program In addition, the micro-controller operates the micro-controller under a normal implementation mode. It is a register that can implement the LWRT bit in many ways. The micro-controller H can contain a separate register, and the paper standard (CNS) A4 size io x 297 mm γ (Please read the precautions on the back before filling this page) Order --------- Line | V. Invention The user program executed by Ming (u) is exhausted to control. It uses the existing code of the microcontroller to write information to the long-term enable register 55 or read from long-term 2 to 11 55. Take the information. The temporary storage H can also be part of the shell material memory. In this case, it is an SRAM cell (that is, the user can read and write people to the cell freely.) The register can be further used as a fuse. FIG. 4 is a diagram illustrating a case where the WRT temporary storage A is implemented in the data RAM 44. The data RAM 44 includes a data latch 46, an address latch 48, and a data area 49. A section 47 of the data area 49 is designated as a special function register (SFRs). In the SFR space 47 ', the lamp is temporarily stored to reside in part of the user information RAM area 49. This ship is used to handle specific functions, such as controlling I / O ports' and any peripheral devices, which are part of the microcontroller. In addition, the SFRs control the monitoring timer, alert reset, and so on. Now write the LWRT bit. The program memory 37 contains instructions serialized to the instruction set of the microcontroller. These instructions are obtained via the CPU 45, the program 5 and the memory 37, and are decoded / interpreted by the instruction register% and the instruction decoder 33 (decor / interpret). The specific sequence of + is the inclusion of directives, so that the correct value is displayed on the data bus 25, and the LWRT register is activated at the same time as shown in Figure 3 56. The lWRT register is temporarily stored in the memory 44 as the selection logic device 42. The LWRT register in the caliper space 47 is activated, and the logic device 42 is selected according to the register. The standard is suitable for the FFL towel family standard (CNS) A4 specification (210 X 297 public love) 490670 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (12) Memories 44 shows an address, which will cause The SFR containing the LWRT register is started. Once the LWRT register is activated for writing, the value from the data bus 25 is transferred to the register. The reset logic device M is connected to the long write enable register 55. Once the LWRT bit is set, it can only be cleared by a physical chip reset. This will protect the use temporarily from accidentally clearing the bit, while displaying the stylized voltage level on terminal 50, which will cause an unwanted change in the execution mode. FIG. 5 is a timing diagram illustrating the operation of the device. After starting the chip, the MCLR signal is boosted from 0V to the supply voltage (5V in this case), which enables the microcontroller to enter the normal execution mode. Initially, when the MCLR signal is at OV, the microcontroller is reset by the reset logic device 53 as described above. At certain times, when in operation, the long write enable register is enabled. This is indicated by raising the LWRT signal to a high logic level. This signal also indicates the following situation: Write this value to the Xi register or the data memory, and confirm that the programming of the program memory is started. At this moment, the long write enable register 55 will indicate that the decoding logic device 54 has activated the LWRT bit. At the next execution of the program of the microcontroller, the switching circuit is activated to apply the current level voltage to the MCLR terminal 50. As mentioned above, the switch circuit is activated before the LWRT bit is set or during the test mode. As shown in Figure 5, the next step is to apply this paper to the 14th paper standard of China National Standards (CNS) A4 (21 × 297). --------------- --r --- tl --------- line 41 ^ * (Please read the notes on the back before filling out this page: > 490670 Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs The description of the invention (Π) is increased to 12V. This will cause the high-voltage detection circuit 52 to indicate that the programmed logic voltage is present at the programmed level voltage. In the case of this setting being a high level, the Longwrite-Enable signal is activated. At present, the program memory 37 can be programmed. Although it is not shown in Fig. 5, activation of the Longwrite-Enable signal will return the MCLR signal to 0V in order to reset the LWRT bit. The 'the LWRT and the Longwrite-Enable voltage will return to OV. In the present invention, when the program memory is programmed, a signal is required to perform a predetermined function. The programmed voltage can also be used. This signal is used to instruct the microcontroller to enter the test enable mode. The command is to have a different test mode selection signal. The long-time write enable mode is detected by a circuit connected to the terminal to which the signal is applied, which instructs the chip to enter a specific mode or perform different functions. The present invention reduces the number of terminals required in order for the microcontroller to perform all desired functions. In the following cases, someone would like to develop a private group of pin-compatible devices. Useful. Once a user has designed a pin configuration (f〇tprint) for a microcontroller, the extra pins are freed to allow the additional functions to provide the following capabilities: Provide more and better A powerful microcontroller with additional restrictions on maintaining terminal component size compatibility added by the user. Upward compatibility is a substantial advantage because a user does not need to engage in high Cost and time wasted redesign, when and (Please read the precautions on the back before filling this page) Order -------! Line ^ -15-
490670 A7490670 A7
490670490670
第0891(H215號專利申請案 中文說明書修正頁（91年4月1J 五、發明説明（14a ) [元件 符號說明] 10 封裝 12 開關控制線路 • 11 電壓開關 13 振盪器 20、21 、22、23、24 PORTA 、PORTB 、PORTC、P〇RTD、PORTE 25 資料匯流排 45 CPU 26 算術邏輯單元 46 資料鎖存器 一 27 週邊裝置 47 特定功能暫存器(SFR)空間 28 電路元件 48 位址鎖存器 29 頻帶 49 資料區域 30 4xpll電路 50 端子 31 時序產生電路 51 連接 32 緩衝器 52 高壓偵測電路 33 指令解碼和控制電路 53 重設邏輯裝置 34 暫存器 54 解碼邏輯裝置 35 ROM鎖存器 55 長時間寫入致能暫存器 36 表格鎖存器 56 LWRT暫存器啟動 37 程式記憶體 100 微處理器 38 多工器 109 EEPROM 39 表格指標器 116 安全邏輯裝置 40 # 呈式計數器 118 導線 41 N層次堆疊 120 導線 42 暫存器選擇邏輯裝置 202 目前位址比較器 43 位址多工器 204 程式計數器 44 資料RAM -16a- 本紙張尺度適用中國國家標準((：；1^3) A4規格(210 X 297公釐)No. 0891 (H215 Patent Application Chinese Specification Revision Page (April 91, 1J V. Description of the Invention (14a)) [Element Symbol Description] 10 Package 12 Switch Control Circuit 11 Voltage Switch 13 Oscillator 20, 21, 22, 23 , 24 PORTA, PORTB, PORTC, PORTD, PORTE 25 Data bus 45 CPU 26 Arithmetic logic unit 46 Data latch one 27 Peripheral device 47 Special function register (SFR) space 28 Circuit element 48 Address latch Device 29 frequency band 49 data area 30 4xpll circuit 50 terminal 31 timing generation circuit 51 connection 32 buffer 52 high voltage detection circuit 33 instruction decoding and control circuit 53 reset logic device 34 register 54 decoding logic device 35 ROM latch 55 Long-time write enable register 36 Table latch 56 LWRT register enable 37 Program memory 100 Microprocessor 38 Multiplexer 109 EEPROM 39 Table indicator 116 Safety logic device 40 # Presentation counter 118 Wire 41 N-level stacking 120 wires 42 register selection logic device 202 current address comparator 43 address multiplexer 204 process Counter 44 data RAM -16a- This paper size applies to Chinese national standards ((:; 1 ^ 3) A4 size (210 X 297 mm)