Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
  • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
  • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Definitions

• This invention relates to semiconductor memories and in particular to semiconductor memories having a flexible and efficient circuit for substituting redundant columns for defective columns.
• DRAMs Semiconductor dynamic random access memories
• DRAMs are typically formed of wordlines and columns crossing the wordlines. Capacitors adjacent each crossing of the rowlines and columns store charge, designating the data to be stored. The capacitors are coupled to the columns by an access transistor in order to receive or discharge charge upon receipt of an appropriate voltage on the rowlines.
• the rowlines and columns are selected so as to read and write to particular capacitors by means of row (or X) decoders and column (or Y) decoders.
• RAMs usually contain redundant (spare) columns which involve the provision of extra memory elements and column circuitry.
• the extra memory and required redundant decoders to access that memory in place of defective columns uses valuable semiconductor chip area and decreases the area efficiency of the memory.
• Various techniques have been implemented to provide column redundancy schemes in synchronous dynamic random access memories (SDRAMs). Amongst these are the address compare approach, the address detector approach, the shifter approach, and the address or data steering approach as well as combinations thereof. For example, in a first of these techniques utilizes an Y address comparator, wherein predecoded Y address signals (PY1 :N) pass through fuses to generate redundant column enable signals (RCE) as illustrated in figure 1.
• RCE redundant column enable signals
• a second technique involves an Y address detector 4 wherein Y address signals (AY(N-1 :0)) control NMOS gates that connect to a pre-charged node through fuses and each can generate redundant column enable signals as shown in figure 2.
• Y address signals AY(N-1 :0)
• a column redundant enable signal COL_RED_EN
• timing between the normal and the redundant column path is usually different. Additional logic circuits are required to adjust the timing difference, i.e. a time delay circuit must be employed in the normal address signal path in order to compensate for the slower redundant path.
• a further technique known as a shift replacement Y decoder utilizes fuses in the Y decoders but not connected in the signal path.
• two Y select lines share one group of fuses.
• the column is disabled by blowing the fuse inside the Y decoder. Shifting the Y driver access for the defective block over to an adjacent driver completes replacement.
• An advantage of this system is that since fuses are not connected in the column address path, no difference in timing between the normal and redundant path exists. Furthermore, block replacement is possible (failed columns can be repaired in each block with different decoding of each block).
• a disadvantage of this system is that two adjacent Y select lines must be replaced at the same time making this technique less flexible than other techniques. Furthermore, one directional shifting is required of the columns.
• each Y decoder consists of an NMOS multiplexer 12 which steers the column select signal either down the normal or redundant paths according to the information programmed in the fuse circuit 14.
• NMOS transistors are used in conjunction with an on-chip boosted voltage supply VPP to select the appropriate path since the NMOS transistors in the multiplexer require a voltage larger than VDD to fully turn them on.
• the redundant select line RYSEL 16 is long and exhibits considerable RC delay.
• This invention seeks to provide a column redundancy method and apparatus in a semiconductor memory that minimizes the timing difference between a normal address path and a redundant column address path and which minimizes the number of fuses required to be blown in repairing faulty columns.
• a semiconductor memory device comprising: a) a plurality of normal memory columns selectively enabled by normal column decoders; b) redundant memory columns selectively enabled by redundant column decoders, the normal and redundant decoders being responsive to a column clock signal; and c) local signal distribution circuitry for switching the column clock signal to either a normal driver or to the corresponding redundancy driver in response to an output from the redundant column decoder.
• Figure 2 indicates a further redundancy programming circuit according to the prior art
• Figure 3 is a schematic diagram of a redundancy address steering scheme according to the prior art
• Figure 4 is a plan view showing a layout for part of a semiconductor memory with a column redundancy scheme according to an embodiment of the present invention
• Figure 5(a) is a schematic diagram of a normal column decoder according to an embodiment of the present invention
• Figure 5(b) is a schematic diagram of a column driver according to an embodiment of the present invention
• Figure 6 is a schematic diagram of a redundant column decoder according to an embodiment of the present invention
• Figure 7 is a schematic diagram of an address compare circuit according to an embodiment of the present invention.
• Figure 9 is a schematic diagram of a column clock distribution circuit according to an embodiment of the present invention.
• Figure 10 is a schematic diagram of a redundant decoder latch according to an embodiment of the present invention.
• FIG. 60 the layout of a section of an SDRAM implementing a column redundancy scheme according to a general embodiment of the present invention, is shown by numeral 60. More specifically, the column redundancy scheme illustrated is that for a 256M (Mbit) SDRAM in which the memory chip is divided into four banks, with 16x32 blocks per bank, i.e. 16 blocks of rowlines and 32 blocks of columns. Each bank is physically separated into two half banks in the column direction by row decoders, with each half bank having sixteen (16) column blocks. Each block comprises sixty-four (64) normal columns 62 and one (1) redundant column.
• the section 60 shown has blocks numbered BLOCK1, BLOCK2, BLOCK3 and BLOCK4, and this layout is repeated four times for a half bank and eight times for an entire bank.
• the redundant column 64 associated with each block is shown at the right hand side thereof.
• Each block has a core Y decoder driver circuit YDEC 66 and (Note: core circuitry refers to circuitry that is physically and functionally associated with the memory array; the terms column and Y are used interchangeably) and a single core redundant decoder RY 68 and driver RYDEC 70.
• the core Y decoders 66 are the second stage of the overall Y decoding for the chip.
• the core Y decoder 66 gets its input from Y predecoder (not shown) outputs PY and completes the column decoding.
• the first stage of column decoding is performed by the Y predecoders which, from global column address signals ACL[0:8] (not shown), generate the following predecoded Y addresses: PY0_1_2(7:0), PY3_4(3:0), PY5_6(3:0), PY7_8(3:0). All of these addresses are shown generally in Figure 4 as bus PY that carries the predecoded address signals to the core Y decoder 60 and core Y redundancy circuitry 70.
• each block has one Y redundancy column 64 and decoder RY
• the Y redundancy decoder and its corresponding BLOCK core Y decoder share the same block selection signal (BSEL).
• BSEL block selection signal
• the core Y decoders 66 and the redundant column 64 are clocked by a common Y select clock signal YSG.
• the overall structure of the four related redundant Y decoders, their relations to the core Y decoders and core-I/Os are illustrated in Figure 4.
• the YSG signals are distributed locally.
• the YSG signal drivers at the center of the bank pass YSG signals throughout an entire bank.
• Local YSG signal distribution circuitry indicated as YSGl, YSG2, YSG3 etc., and shown in detail in figure 10, are provided for each block.
• Each of the local YSG signal distribution circuitry 72 switch and drive the YSG signal to either a normal core Y decoder 66 or to the corresponding Y redundancy decoder 68 in response to the output RDEC from the redundant Y decoder.
• YSG signals are switched to redundant Y decoder to drive the redundancy column 64. If the latched logic value is low, the YSG signals are switched to core Y decoder to drive the normal column.
• the BSEL signal goes high.
• the corresponding core-I/O needs to be enabled so core-I/O control signal DBSW CTL goes high.
• the selected normal column is bad, it can be replaced by a redundant Y decoder, either within or outside the current block. Under this failure case even if BSEL is still high, whether DBSW_CTL goes high or not depends on the position of the failure replacement.
• the DBSW_CTL signal is responsible for switching the appropriate data bus pass gates 67 for coupling the selected column data to the data bus.
• BSEL and DB_CTL are all inputs to the redundant decoder described in figure 6, used to determine the output DBSW_CTL, which controls the core I/O switch.
• the core-I/O switch rule is shown in the following table:
• BUSL signals schedule the toggling between BO and Bl signals.
• FIG. 5(a) and 5(b) a schematic diagram of the core Y decoder 66a and a Y driver 66b is shown.
• the combined circuit is shown schematically in block 66 of figure 4.
• the core Y decoder 66a comprises a pair of NAND gates 72 and 74 for receiving the Y predecoder outputs PY0_1_2, PY3_4, PY5_6 and PY7_8.
• the outputs from the NAND gates 72 and 74 are combined in a NOR gate 76 to provide decoded output signal DEC.
• the decoder circuit 66a is equivalent to a four input AND gate.
• the output from the core Y decoder DEC is coupled to the column driver circuit 66b as shown in figure 5(a).
• the normal or redundant column driver 66b receives the Y clock enable signals
• CMOS pass gates 82 and 84 which are controlled by the output signal DEC in conjunction with signals BUSL and BUSL .
• the clock signals YSG_B0 and YSG_B1 are passed through the CMOS gates at the appropriate time to an inverter 86 which then drives the corresponding column with the signal Y_B0 or Y_B1, depending on the state of the BUSL or the BUSL signals.
• the decoded signal DEC controls the pass gates 82 and 84.
• the overall core Y decoder YDEC 66 shown in figure 4 may be built with the two components shown in figures 5(a) and 5(b). For example, if the Y address has nine bits, it then has 512 different decoding outputs. The even bits and odd bits may be separated to drive four even blocks and four odd blocks respectively. The arrangement will then repeat itself two times to realize a complete core wide decoder for a half bank or four times for a whole bank.
• each memory block has one redundant column located at the side of the block.
• the redundancy decoder RY and its corresponding core Y decoder YDEC share the same block selection signal (BSEL).
• the redundancy decoder RY shown in figure 6 includes a pair of address-compare circuits 90 which receive the predecoded addresses PY0_1_2, PY3_4, PY5_6 and PY7_8.
• Each address-compare circuit 90 is capable of being programmed with a single address thus the redundant Y decoder is capable of being programmed to two redundant addresses. Details " of the address compare circuitry 92 and 94 will be discussed with reference to figure 8. Because normal columns may have separately addressed upper or lower portions within a block, a row address signal AX12 is provided to the redundant Y decoder to perform the upper or lower column portion selection. The row address signal AX 12 is coupled to the control inputs of a pair of CMOS pass gates 96 and 98 which receive the respective outputs from the address-compare circuits 92 and 94. Thus, one redundant column can be used to replace an upper half of a normal column and a lower half of a normal column of two different addresses or vice versa. The RY signal is coupled to an inverter 99 to drive the RDEC signal, which in turn drives the column driver 66b shown in figure 5(b) and the YSG signal distribution circuit 72 shown in figure 4.
• the circuit also includes the INI1 and INIO generation circuitry.
• the circuit comprises a chain of series connected inverters 100 driven from a main INI signal line, and the INIO and INI1 signals taken as taps along the chain.
• the address compare circuit 90 of figure 6 is shown in detail. Since the predecoder (figure 4) has four groups of predecoded outputs: PY0_1_2, PY3_4, PY5_6 and PY7_8, the address-compare circuit comprises four groups of programmable fuse circuits 142. Each group 142 of fuse circuits includes four fuses with an associated fuse state evaluation circuit 180 shown in figure 8. The inputs to each of the constituent fuse evaluation circuits in a group are derived from the predecoded column address signals in each group, i.e., PY0_1_2, PY3_4, PY5_6 or PY7_8.
• the outputs PY_OUT from each of the fuses in a group 142 are combined to provide respective signals PY_OUTl, PY_OUT2, PY_OUT3 and PY_OUT4. These signals are passed through an initialization circuit 144 before being combined in an address combiner circuit 146.
• the address combiner circuit is essentially a four input NAND gate which outputs the redundant select signal RY shown in figure 6.
• the operation of the circuit 90 is as follows. If there are no defective columns and no need for redundancy, then no fuse circuits are blown, and the PY_OUT lines are all initialized to a logic low due to the initialization portion 144 of the circuit. This is in contrast with some of the prior art address-compare implementations where fuses of defective addresses were left intact while fuses of all non-defective columns were blown. That approach complicates the redundancy programming process considerably.
• the initialization circuit 144 is comprised of a pair of NOR gates 148 and 150, each connected to receive at its inputs a respective PY_OUT signal. Each of the NOR gate inputs are coupled to a respective NMOS transistor 152 and 154.
• the gates of these transistors are connected to their respective NOR gate output.
• the outputs of the NOR gates are logic high while the feedback connections via the feedback transistors further latch the inputs to logic low.
• the same logic low signals on lines PY_OUT are fed into NAND gates 155 and 156 thus producing logic highs at their outputs.
• the signal CST_BLK is a block redundancy test signal which is normally high, thus enabling NAND gates 157 and 158.
• both outputs from NAND gates 157 and 158 are logic low, which in turn produce a logic high out of NAND gate 160, indicating that redundancy is not being used, i.e., RY is logic high.
• the circuit 180 receives one of the predecoded address signals on its PY_LN terminal which is in turn connected to a CMOS pass gate 182 formed by a NMOS and PMOS transistor 183 and 184 respectively.
• the output of the CMOS pass gate 182 is the signal PY_OUT.
• the pass gates 183 and 184 are controlled by a fuse element 186.
• the initial conditions for the pass gate 182 are set by a NAND gate 188, which in turn has its initial conditions determined by its inputs received from signals INIO and INIl.
• the INIO and INIl signals are slightly delayed versions of one another with INIO preceding INIl, as shown in figure 6.
• a feedback PMOS transistor 190 has its gate connected to output of NAND gate
• the feedback transistor 190 is used to latch the programmed redundancy address.
• the INIl signal is applied directly to the other input 188a of the NAND gate 188 and to the gate of an NMOS transistor 192 having its source connected to one end of the fuse 186 the other end of which is connected to ground.
• the drain terminal of the NMOS transistor 192 is connected to the drain terminal of a PMOS transistor 194 which in turn has its source connected to the V DD supply.
• the INIO signal is applied to the gate of the PMOS transistor 194.
• the common drain connection between the PMOS transistor 194 and the NMOS transistor 192 is connected to the first input 188b of the NAND gate 188.
• the output from the NAND gate 188 is connected via an inverter 196 to drive one of the pass gate transistors 183.
• the fuse state is evaluated as follows. Signal INIO and INIl are generated from the POWER_OK signal and INIl is delayed from INIO. Initially, both INIO and INIl are low and the CMOS transmission gate is open and the predecoded signal cannot be passed. In general operation, if the fuse is not blown, once both INIO and INIl have become high, the CMOS transmission gate keeps its open state. On the other hand, if the fuse is blown, the CMOS transmission gate is closed and the predecoded signal PY_IN is passed as a redundant predecoded address signal PY OUT.
• the feedback transistor 190 is used to latch the redundant state of the fuse circuit for the pass gate 182.
• this PMOS device 190 is fairly long to allow easy resetability of the half latch.
• long channel transistors tend to consume more power and take up more area than ones with shorter channels.
• the role of the delayed initialization signals INTO and INIl also serves to reduce the size of the feedback transistor 190 to a normal size. This implementation therefore reduces the current consumption during fuse evaluation.
• the delayed activation of the INIO and INIl signals avoids a race condition is avoided as follows: if INIO and INIl were one and the same signal, during the transition from a low to a high, both devices 194 and 192 would be conducting. Since device 194 could achieve a faster pull-up than the pull-down through 192 due to the resistance of the fuse, node
• This logic low output is latched through the turning on of transistor 190 and enables the CMOS pass gate 182.
• the pass gate 182 allows the signal PY_IN to pass through as signal PY_OUT and override the precharge value on the corresponding precharge line shown in figure 7. It is important to note that only fuses of faulty addresses need to be blown and not those of non-defective addresses.
• the YSG switching circuit 72 (figure 4) is shown in detail.
• the switching circuit includes a pair of YSG latches 200 coupled to latch and delay the input RDEC signal.
• the YSG signal is held for two clock cycles due to the dual data bus architecture.
• the output RYSG_B( ⁇ : 0) and YSG _ R(l : 0) are coupled to the redundant driver 70 and the normal Y drivers respectively.
• the RCTL (redundant decoder control) output from the latches 200 are coupled to an input of respective gates 202 and 204, while a CTL (decoder control) output is coupled to the inputs of a second pair of NAND gates 206 and 208.
• Both sets of NAND gates 202, 204 and 206, 208 receive the YSG signal on one of their other inputs.
• the YSG latches 200 have their outputs RCTL and CTL of complementary polarity.
• the NAND gates 202, 204 and 206, 208 are responsible for switching the YSG signal to either RYSG_B or YSG_B.
• the number of redundant Y drivers associated with a group of normal Y drivers may be varied.
• the column redundancy system may be applied to all types of RAMs such as DRAMs, SDRAMs, SGRAMs, and the like.
• the redundancy system described herein could also be adapted to implement row redundancy.

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