WO2000017922A1 - PROCEDE POUR AMINCIR CHIMIQUEMENT, PAR VOIE HUMIDE, DES COUCHES DE Si DANS UNE REGION EMETTEUR ACTIF D'UN TRANSISTOR BIPOLAIRE - Google Patents

PROCEDE POUR AMINCIR CHIMIQUEMENT, PAR VOIE HUMIDE, DES COUCHES DE Si DANS UNE REGION EMETTEUR ACTIF D'UN TRANSISTOR BIPOLAIRE Download PDF

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Publication number
WO2000017922A1
WO2000017922A1 PCT/DE1999/003068 DE9903068W WO0017922A1 WO 2000017922 A1 WO2000017922 A1 WO 2000017922A1 DE 9903068 W DE9903068 W DE 9903068W WO 0017922 A1 WO0017922 A1 WO 0017922A1
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WO
WIPO (PCT)
Prior art keywords
layer
silicon
base
bipolar transistor
wet
Prior art date
Application number
PCT/DE1999/003068
Other languages
German (de)
English (en)
Inventor
Jürgen Drews
Bernd Tillack
Bernd Heinemann
Original Assignee
Institut für Halbleiterphysik Frankfurt (Oder) GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institut für Halbleiterphysik Frankfurt (Oder) GmbH filed Critical Institut für Halbleiterphysik Frankfurt (Oder) GmbH
Publication of WO2000017922A1 publication Critical patent/WO2000017922A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Definitions

  • the invention relates to a method for wet chemical thinning of Si layers in the active emitter region of a bipolar transistor.
  • the high-speed properties of bipolar transistors can be further improved with the aid of epitaxial processes for producing the base and the base connection.
  • the option of in-situ doping is used to achieve lower base widths and layer resistances.
  • the deposition of heterolayers has a favorable effect on the setting of base layer resistance and current gain.
  • the method of differential epitaxy was used to generate epitaxial base layers. Differential epitaxy means that epitaxial growth takes place in both semiconductor and insulator areas. In this way, the inner base and the base connection can be created on the isolator area at the same time.
  • the disadvantage here is that the thickness of the epitaxial layer of the inner base cannot be set independently of that of the base connection on the insulator region.
  • the object of the invention is to propose a method for wet chemical thinning of the epitaxial silicon layer in the active emitter region of a bipolar transistor, which
  • a sufficiently small epitaxial layer thickness in the area of the active base-emitter junction A thicker epitaxial layer between the emitter and base and in the outer base region enables the lowest possible base connection resistances.
  • the epitaxial layer thickness above the base is generally increased and subsequently made within the active emitter region by means of suitable methods, such as, for example, B. wet chemical etching, reduced.
  • this object is achieved by generating a wet chemical surface relief in the area of the active emitter.
  • an additional in-situ doping epitaxially in the cover layer above the deposited base.
  • ALD atomic layer Doping
  • the metering and the vertical positioning of the dopant layer are adjusted with atomic layer accuracy.
  • This atomic layer accuracy of introducing the doping as an etch stop layer offers the advantage to adjust the thickness of the emitter layer to be etched with atomic layer accuracy
  • the atomic layer doping is introduced during the deposition of the emitter layer.
  • FIG. 1 Schematic representation of a bipolar transistor during the manufacture vers
  • a Fig. 2 Schematic representation of a bipolar transistor during the manufacture vers
  • Example 1 The invention will now be described using the example of the production of a bipolar transistor.
  • 1 shows the implementation of the wet chemical thinning of the silicon cover layer 3 + 9 in the active emitter region 7 of a bipolar transistor with a base connection in the field insulation region.
  • An epitaxial layer sequence consisting of buffer layer 1, in-situ doped base layer 2 and cover layer 3 + 9, in which there is an etching stop layer 5, covers the area of the future emitter as a single-crystal layer stack 1; 2; 3; 5; 9 and part of the field isolation region 6 as a polycrystalline layer stack 1/1; 2/1; 3/1; 5/1; 9/1.
  • the structured epitaxial layer is covered with a dielectric 4, which was only removed in the area of the active emitter region 7.
  • the doping dose of the etch stop layer 5 in the lid produced by means of ALD, is smaller than a monolayer of the respective dopant, so that the lid layer 9 lying above it has grown single-crystal.
  • the cover layer is partially removed in the active emitter region.
  • the etching stop layer 5 can be removed by means of likewise known wet chemical etching agents.
  • An epitaxial layer sequence consisting of buffer layer 1, in-situ doped base layer 2 and cover layer 3, in which there is a dopant layer 10 which, due to the nature of its production, causes the cover layer 8 after the formation of the dopant layer 10 continues to grow polycrystalline, covers the area of the future emitter and part of the field isolation area 6 as a polycrystalline layer stack 1/1; 2/1; 3/1; 10/1; 8/1.
  • the structured epitaxial layer is covered with a dielectric 4, which was only removed in the area of the active emitter region 7.
  • the doping dose of the dopant layer 10 in the cover is greater than a monolayer of the respective dopant with a thickness of less than 3 nm, so that the cover layer 8 lying above it grows polycrystalline.
  • the polycrystalline part of the cover layer 8, including the dopant layer 10 is removed in the active emitter region 7 with the aid of known wet chemical etching agents which remove polysilicon highly selectively with respect to the dielectric 4 and the crystalline silicon 3.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un procédé pour amincir chimiquement, par voie humide, des couches de Si dans une région émetteur d'un transistor bipolaire. L'invention a pour but de fournir un procédé permettant d'amincir chimiquement par voie humide la couche épitaxiée de silicium dans une région émetteur actif d'un transistor bipolaire, améliorant les propriétés de vitesse élevée du transistor bipolaire et permettant d'obtenir, en particulier dans la région de transition active base-émetteur, une épaisseur de couche épitaxiée suffisamment faible entre l'émetteur et la base et, dans la région de base extérieure, une couche épitaxiée plus épaisse, en vue de réaliser des résistances de connexion de base aussi faibles que possible. Ce but est atteint, conformément à l'invention, grâce à une production en relief en surface, chimiquement par voie humide, dans la région de l'émetteur actif. Pour obtenir des érosions déterminées de silicium dans la région de l'émetteur actif, il est avantageux de réaliser un dopage in situ supplémentaire, par épitaxie, dans la couche du couvercle, au-dessus de la base séparée. Ces dopages in situ servent de couches d'arrêt de gravure permettant un enlèvement déterminé de silicium, de façon bien reproductible, avec des agents d'attaque chimique par voie humide de types connus. Comme procédé de production de la couche d'arrêt d'attaque, on utilise l''Atomic Layer Doping' (dopage par couche atomique) (ALD).
PCT/DE1999/003068 1998-09-21 1999-09-20 PROCEDE POUR AMINCIR CHIMIQUEMENT, PAR VOIE HUMIDE, DES COUCHES DE Si DANS UNE REGION EMETTEUR ACTIF D'UN TRANSISTOR BIPOLAIRE WO2000017922A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1998145790 DE19845790B4 (de) 1998-09-21 1998-09-21 Verfahren zur naßchemischen Abdünnung von Si-Schichten im aktiven Emittergebiet eines Bipolartransistors
DE19845790.1 1998-09-21

Publications (1)

Publication Number Publication Date
WO2000017922A1 true WO2000017922A1 (fr) 2000-03-30

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Application Number Title Priority Date Filing Date
PCT/DE1999/003068 WO2000017922A1 (fr) 1998-09-21 1999-09-20 PROCEDE POUR AMINCIR CHIMIQUEMENT, PAR VOIE HUMIDE, DES COUCHES DE Si DANS UNE REGION EMETTEUR ACTIF D'UN TRANSISTOR BIPOLAIRE

Country Status (2)

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DE (1) DE19845790B4 (fr)
WO (1) WO2000017922A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004053393B4 (de) 2004-11-05 2007-01-11 Atmel Germany Gmbh Verfahren zur Herstellung einer vertikal integrierten Kaskodenstruktur und vertikal integrierte Kaskodenstruktur
DE102004053394B4 (de) 2004-11-05 2010-08-19 Atmel Automotive Gmbh Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung
DE102004055213B4 (de) * 2004-11-16 2009-04-09 Atmel Germany Gmbh Verfahren zur Herstellung einer integrierten Schaltung auf einem Halbleiterplättchen

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0483487A1 (fr) * 1990-10-31 1992-05-06 International Business Machines Corporation Transistor à base epitaxiale auto-aligné et sa méthode de fabrication

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US5198372A (en) * 1986-01-30 1993-03-30 Texas Instruments Incorporated Method for making a shallow junction bipolar transistor and transistor formed thereby
US5096842A (en) * 1988-05-16 1992-03-17 Kabushiki Kaisha Toshiba Method of fabricating bipolar transistor using self-aligned polysilicon technology
JPH06101473B2 (ja) * 1988-12-05 1994-12-12 日本電気株式会社 半導体装置
US5024957A (en) * 1989-02-13 1991-06-18 International Business Machines Corporation Method of fabricating a bipolar transistor with ultra-thin epitaxial base
US5648294A (en) * 1989-11-29 1997-07-15 Texas Instruments Incorp. Integrated circuit and method
US5160994A (en) * 1990-02-19 1992-11-03 Nec Corporation Heterojunction bipolar transistor with improved base layer
JPH0669227A (ja) * 1992-05-29 1994-03-11 Texas Instr Inc <Ti> 化合物半導体のヘテロ接合バイポーラトランジスタ及びその製造方法
JPH06132298A (ja) * 1992-10-14 1994-05-13 Mitsubishi Electric Corp 半導体装置の製造方法
US5593905A (en) * 1995-02-23 1997-01-14 Texas Instruments Incorporated Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link
DE19533677A1 (de) * 1995-09-12 1997-03-13 Daimler Benz Ag Verfahren zur Herstellung eines Heterobipolartransistors
US5640025A (en) * 1995-12-01 1997-06-17 Motorola High frequency semiconductor transistor
WO1997024757A1 (fr) * 1995-12-28 1997-07-10 Philips Electronics N.V. Procede de production d'un transistor bipolaire vertical a alignement automatique sur un dispositif du type silicium sur isolant
DE19609933A1 (de) * 1996-03-14 1997-09-18 Daimler Benz Ag Verfahren zur Herstellung eines Heterobipolartransistors
US5773350A (en) * 1997-01-28 1998-06-30 National Semiconductor Corporation Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0483487A1 (fr) * 1990-10-31 1992-05-06 International Business Machines Corporation Transistor à base epitaxiale auto-aligné et sa méthode de fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LAN W H ET AL: "RECESSED-GATE ALGAAS/INGAAS/GAAS PSEUDORPMORPHIC HEMT WITH SI- PLANAR-DOPED ETCH STOP LAYER", ELECTRONICS LETTERS,GB,IEE STEVENAGE, vol. 31, no. 7, 30 March 1995 (1995-03-30), pages 592 - 594, XP000504333, ISSN: 0013-5194 *

Also Published As

Publication number Publication date
DE19845790A1 (de) 2000-03-23
DE19845790B4 (de) 2008-12-04

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