WO2000017922A1 - METHOD FOR THE WET-CHEMICAL THINNING OF Si-LAYERS IN THE ACTIVE EMITTER REGION OF A BIPOLAR TRANSISTOR - Google Patents
METHOD FOR THE WET-CHEMICAL THINNING OF Si-LAYERS IN THE ACTIVE EMITTER REGION OF A BIPOLAR TRANSISTOR Download PDFInfo
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- WO2000017922A1 WO2000017922A1 PCT/DE1999/003068 DE9903068W WO0017922A1 WO 2000017922 A1 WO2000017922 A1 WO 2000017922A1 DE 9903068 W DE9903068 W DE 9903068W WO 0017922 A1 WO0017922 A1 WO 0017922A1
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- bipolar transistor
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- 239000000126 substance Substances 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 76
- 239000002019 doping agent Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 2
- 238000011065 in-situ storage Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000003631 wet chemical etching Methods 0.000 abstract description 4
- 239000003795 chemical substances by application Substances 0.000 abstract description 3
- 230000007704 transition Effects 0.000 abstract 1
- 238000007704 wet chemistry method Methods 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
Definitions
- the invention relates to a method for wet chemical thinning of Si layers in the active emitter region of a bipolar transistor.
- the high-speed properties of bipolar transistors can be further improved with the aid of epitaxial processes for producing the base and the base connection.
- the option of in-situ doping is used to achieve lower base widths and layer resistances.
- the deposition of heterolayers has a favorable effect on the setting of base layer resistance and current gain.
- the method of differential epitaxy was used to generate epitaxial base layers. Differential epitaxy means that epitaxial growth takes place in both semiconductor and insulator areas. In this way, the inner base and the base connection can be created on the isolator area at the same time.
- the disadvantage here is that the thickness of the epitaxial layer of the inner base cannot be set independently of that of the base connection on the insulator region.
- the object of the invention is to propose a method for wet chemical thinning of the epitaxial silicon layer in the active emitter region of a bipolar transistor, which
- a sufficiently small epitaxial layer thickness in the area of the active base-emitter junction A thicker epitaxial layer between the emitter and base and in the outer base region enables the lowest possible base connection resistances.
- the epitaxial layer thickness above the base is generally increased and subsequently made within the active emitter region by means of suitable methods, such as, for example, B. wet chemical etching, reduced.
- this object is achieved by generating a wet chemical surface relief in the area of the active emitter.
- an additional in-situ doping epitaxially in the cover layer above the deposited base.
- ALD atomic layer Doping
- the metering and the vertical positioning of the dopant layer are adjusted with atomic layer accuracy.
- This atomic layer accuracy of introducing the doping as an etch stop layer offers the advantage to adjust the thickness of the emitter layer to be etched with atomic layer accuracy
- the atomic layer doping is introduced during the deposition of the emitter layer.
- FIG. 1 Schematic representation of a bipolar transistor during the manufacture vers
- a Fig. 2 Schematic representation of a bipolar transistor during the manufacture vers
- Example 1 The invention will now be described using the example of the production of a bipolar transistor.
- 1 shows the implementation of the wet chemical thinning of the silicon cover layer 3 + 9 in the active emitter region 7 of a bipolar transistor with a base connection in the field insulation region.
- An epitaxial layer sequence consisting of buffer layer 1, in-situ doped base layer 2 and cover layer 3 + 9, in which there is an etching stop layer 5, covers the area of the future emitter as a single-crystal layer stack 1; 2; 3; 5; 9 and part of the field isolation region 6 as a polycrystalline layer stack 1/1; 2/1; 3/1; 5/1; 9/1.
- the structured epitaxial layer is covered with a dielectric 4, which was only removed in the area of the active emitter region 7.
- the doping dose of the etch stop layer 5 in the lid produced by means of ALD, is smaller than a monolayer of the respective dopant, so that the lid layer 9 lying above it has grown single-crystal.
- the cover layer is partially removed in the active emitter region.
- the etching stop layer 5 can be removed by means of likewise known wet chemical etching agents.
- An epitaxial layer sequence consisting of buffer layer 1, in-situ doped base layer 2 and cover layer 3, in which there is a dopant layer 10 which, due to the nature of its production, causes the cover layer 8 after the formation of the dopant layer 10 continues to grow polycrystalline, covers the area of the future emitter and part of the field isolation area 6 as a polycrystalline layer stack 1/1; 2/1; 3/1; 10/1; 8/1.
- the structured epitaxial layer is covered with a dielectric 4, which was only removed in the area of the active emitter region 7.
- the doping dose of the dopant layer 10 in the cover is greater than a monolayer of the respective dopant with a thickness of less than 3 nm, so that the cover layer 8 lying above it grows polycrystalline.
- the polycrystalline part of the cover layer 8, including the dopant layer 10 is removed in the active emitter region 7 with the aid of known wet chemical etching agents which remove polysilicon highly selectively with respect to the dielectric 4 and the crystalline silicon 3.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention relates to a method for the wet-chemical thinning of Si-layers in the active emitter region of a bipolar transistor. The aim of the invention is to provide a method for the wet-chemical thinning of the epitactic silicon layer in the active emitter region of a bipolar transistor, which improves the high-speed properties of the bipolar transistor, notably in the region of the active base-emitter transition allows for a sufficiently thin epitaxis layer between emitter and base, and in the outer base area permits the production of a thicker epitaxis layer to achieve the lowest possible base connection resistances. To this end a surface relief is produced by a wet-chemical process in the area of the active emitter. To achieve a defined removal of silicon in the area of said active emitter, additional in-situ dopage is carried out by epitaxis in the cover layer above the deposited base. The in-situ dopages serve as etch stop layers which allow for the readily reproducible and defined removal of silicon using known wet-chemical etching agents. Atomic layer doping (ALD) was used to produce the etch stop layer.
Description
Verfahren zur naßchemischen Abdunnung von Si-Schichten im aktiven Emittergebiet eines BipolartransistorsProcess for the wet chemical thinning of Si layers in the active emitter region of a bipolar transistor
Die Erfindung bezieht sich auf ein Verfahren zur naßchemischen Abdunnung von Si-Schichten im aktiven Emittergebiet eines Bipolartransistors.The invention relates to a method for wet chemical thinning of Si layers in the active emitter region of a bipolar transistor.
Mit Hilfe epitaktischer Prozesse zur Erzeugung der Basis und des Basisanschlusses lassen sich die Hochgeschwindigkeitseigenschaften von Bipolartransistoren weiter verbessern. Dabei wird die Möglichkeit der insitu-Dotierung genutzt, um geringere Basisweiten und -schichtwiderstände zu realisieren. Günstig auf die Einstellung von Basisschichtwiderstand und Stromverstärkung wirkt sich bekanntermaßen die Abscheidung von Heteroschichten aus. In einer speziellen Einfach-Polysilizium-Technologie mit Ätzstoppschicht wurde das Verfahren der differentiellen Epitaxie zur Erzeugung epitaktischer Basisschichten verwendet. Differentielle Epitaxie bedeutet, daß epitaktisches Wachstum sowohl auf Halbleiter- als auch auf Isolatorgebieten stattfindet. So können gleichzeitig die innere Basis und der Basisanschluß auf dem Isolatorgebiet entstehen. Nachteilig dabei ist, daß die Dicke der Epitaxieschicht der inneren Basis nicht unabhängig von der des Basisanschlusses auf dem Isolatorgebiet eingestellt werden kann. In Bezug auf Hochgeschwindigkeitsanwendungen wäre es von Vorteil, im Bereich des aktiven Basis-Emitter-Überganges eine hinreichend geringe Epitaxieschichtdicke zwischen Emitter und Basis, im äußeren Basisgebiet zur Realisierung von möglichst geringen Basisanschluß-Widerständen eine dickere Epitaxieschicht zu realisieren.The high-speed properties of bipolar transistors can be further improved with the aid of epitaxial processes for producing the base and the base connection. The option of in-situ doping is used to achieve lower base widths and layer resistances. As is known, the deposition of heterolayers has a favorable effect on the setting of base layer resistance and current gain. In a special single polysilicon technology with an etch stop layer, the method of differential epitaxy was used to generate epitaxial base layers. Differential epitaxy means that epitaxial growth takes place in both semiconductor and insulator areas. In this way, the inner base and the base connection can be created on the isolator area at the same time. The disadvantage here is that the thickness of the epitaxial layer of the inner base cannot be set independently of that of the base connection on the insulator region. With regard to high-speed applications, it would be advantageous to have a sufficiently small epitaxial layer thickness between emitter and base in the area of the active base-emitter junction, and a thicker epitaxial layer in the outer base region to achieve the lowest possible base connection resistances.
Aufgabe der Erfindung ist es, ein Verfahren zur naßchemischen Abdunnung der epitaktischen Siliziumschicht im aktiven Emittergebiet eines Bipolartransistors vorzuschlagen, das dieThe object of the invention is to propose a method for wet chemical thinning of the epitaxial silicon layer in the active emitter region of a bipolar transistor, which
Hochgeschwindigkeitseigenschaften des Bipolartransisors verbessert und insbesondere imHigh-speed properties of the bipolar transistor improved and especially in
Bereich des aktiven Basis-Emitter-Übergangs eine hinreichend geringe Epitaxieschichtdicke
zwischen Emitter und Basis und im äußeren Basisgebiet zur Realisierung von möglichst geringen Basisanschluß-Widerständen eine dickere Epitaxieschicht ermöglicht.A sufficiently small epitaxial layer thickness in the area of the active base-emitter junction A thicker epitaxial layer between the emitter and base and in the outer base region enables the lowest possible base connection resistances.
Zur Realisierung dieser gegensätzlichen Anforderungen an die Epitaxieschichtdicke wird die Epitaxieschichtdicke über der Basis, bekannt als Deckeldicke, generell erhöht und innerhalb des aktiven Emitterbereiches nachträglich mittels geeigneter Verfahren, wie z. B. naßchemischem Rückätzen, reduziert.To meet these conflicting requirements for the epitaxial layer thickness, the epitaxial layer thickness above the base, known as the lid thickness, is generally increased and subsequently made within the active emitter region by means of suitable methods, such as, for example, B. wet chemical etching, reduced.
Erfindungsgemäß wird diese Aufgabe durch eine naßchemische Oberflächenrelief-Erzeugung im Bereich des aktiven Emitters gelöst. Um definierte Silizium- Abträge im Bereich des aktiven Emitters zu erzielen, ist es zweckmäßig, eine zusätzliche in-situ Dotierung epitaktisch in der Deckelschicht über der abgeschiedenen Basis zu realisieren. Diese in-situ Dotierungen dienen als Ätzstoppschichten, die es ermöglichen, gut reproduzierbar mit bekannten naßchemischen Ätzmitteln definiertAccording to the invention, this object is achieved by generating a wet chemical surface relief in the area of the active emitter. In order to achieve defined silicon abrasion in the area of the active emitter, it is expedient to implement an additional in-situ doping epitaxially in the cover layer above the deposited base. These in-situ dopings serve as etch stop layers, which make it possible to reproduce them in a well reproducible manner using known wet chemical etchants
Silizium abzutragen. Als Dotanden werden verschiedene chemische Elemente wie Bor, Germanium oderRemove silicon. Various chemical elements such as boron, germanium or
Kohlenstoff eingesetzt, die einen Ätzstopp bewirken.Carbon used, which cause an etch stop.
Bei Verwendung von Bor als Ätzstopp- bzw. Dotandenschicht liegt es im Bereich derWhen using boron as an etch stop or dopant layer, it is in the range of
Erfindung, zwischen hochdotierter Ätzstopp- bzw. Dotandenschicht und Deckelschicht einerseits und der Emitterdotierung andererseits einen Inside-Poly-Silizium-Spacer zu bilden, um einen ausreichenden seitlichen Abstand zwischen diesen unterschiedlichen Dotierungen zu realisieren.Invention to form an inside poly silicon spacer between the highly doped etch stop or dopant layer and the cover layer on the one hand and the emitter doping on the other hand in order to realize a sufficient lateral distance between these different dopings.
Als Verfahren zur Erzeugung der Ätzstoppschicht wurde das „Atomic Layer Doping", im folgenden als ALD bezeichnet, angewandt. Beim Atomic Layer Doping wird die Dosierung und die vertikale Positionierung der Dotierstoffschicht mit Atomlagengenauigkeit eingestellt. Diese Atomlagengenauigkeit der Einbringung der Dotierung als Ätzstoppschicht bietet den Vorteil, die Dicke der zu ätzenden Emitterschicht mit Atomlagengenauigkeit einzustellen. Erfindungsgemäß wird die Atomlagendotierung während der Abscheidung der Emitterschicht eingebracht."Atomic Layer Doping", hereinafter referred to as ALD, was used as the method for producing the etch stop layer. In atomic layer doping, the metering and the vertical positioning of the dopant layer are adjusted with atomic layer accuracy. This atomic layer accuracy of introducing the doping as an etch stop layer offers the advantage to adjust the thickness of the emitter layer to be etched with atomic layer accuracy According to the invention, the atomic layer doping is introduced during the deposition of the emitter layer.
Die Merkmale der Erfindung gehen außer aus den Ansprüchen auch aus der Beschreibung und aus den Zeichnungen hervor, wobei die einzelnen Merkmale jeweils für sich allein oder zu mehreren in Form von Unterkombinationen schutzfähige Ausführungen darstellen, für die hier
Schutz beansprucht wird. Ausführungsbeispiele der Erfindung sind in den Zeichnungen dargestellt und werden im folgenden näher erläutert.In addition to the claims, the features of the invention also emerge from the description and from the drawings, the individual features each representing embodiments which can be protected individually or in groups in the form of sub-combinations, for the here Protection is claimed. Embodiments of the invention are shown in the drawings and are explained in more detail below.
Die Zeichnungen zeigen:The drawings show:
Fig. 1 Schematische Darstellung eines Bipolartransistors während der Herstellung Vers, a Fig. 2 Schematische Darstellung eines Bipolartransistors während der Herstellung Vers, bFig. 1 Schematic representation of a bipolar transistor during the manufacture vers, a Fig. 2 Schematic representation of a bipolar transistor during the manufacture vers, b
Beispiel 1 : Die Erfindung wird nun am Beispiel der Herstellung eines Bipolartransistors beschrieben. Fig. 1 zeigt die Realisierung der naßchemischen Abdunnung der Silizium-Deckelschicht 3+9 im aktiven Emittergebiet 7 eines Bipolartransistors mit Basisanschluß auf dem Feldisolationsgebiet. Eine Epitaxieschichtfolge, bestehend aus Pufferschicht 1, in-situ dotierter Basisschicht 2 und Deckelschicht 3+9, in der sich eine Ätzstoppschicht 5 befindet, bedeckt das Gebiet des zukünftigen Emitters als einkristalliner Schichtstapel 1; 2; 3; 5; 9 und einen Teil des Feldisolationsgebietes 6 als polykristalliner Schichtstapel 1/1; 2/1; 3/1; 5/1; 9/1. Die strukturierte Epitaxieschicht ist mit einem Dielektrikum 4 bedeckt, das nur im Bereich des aktiven Emittergebietes 7 entfernt wurde. Die Dotierungsdosis der Ätzstoppschicht 5 im Deckel, erzeugt mittels ALD, ist kleiner als eine Monolage des jeweiligen Dotanden, so daß die darüberliegende Deckelschicht 9 einkristallin gewachsen ist.Example 1: The invention will now be described using the example of the production of a bipolar transistor. 1 shows the implementation of the wet chemical thinning of the silicon cover layer 3 + 9 in the active emitter region 7 of a bipolar transistor with a base connection in the field insulation region. An epitaxial layer sequence, consisting of buffer layer 1, in-situ doped base layer 2 and cover layer 3 + 9, in which there is an etching stop layer 5, covers the area of the future emitter as a single-crystal layer stack 1; 2; 3; 5; 9 and part of the field isolation region 6 as a polycrystalline layer stack 1/1; 2/1; 3/1; 5/1; 9/1. The structured epitaxial layer is covered with a dielectric 4, which was only removed in the area of the active emitter region 7. The doping dose of the etch stop layer 5 in the lid, produced by means of ALD, is smaller than a monolayer of the respective dopant, so that the lid layer 9 lying above it has grown single-crystal.
Mit Hilfe bekannter naßchemischer Ätzmittel, die Silizium hochselektiv zum Dielektrikum 4 und zur Ätzstoppschicht 5 abtragen, wird im aktiven Emittergebiet die Deckelschicht teilweise entfernt. Mittels ebenfalls bekannter naßchemischer Ätzmittel kann die Ätzstoppschicht 5 entfernt werden.With the help of known wet chemical etchants, which remove silicon highly selectively with respect to the dielectric 4 and the etch stop layer 5, the cover layer is partially removed in the active emitter region. The etching stop layer 5 can be removed by means of likewise known wet chemical etching agents.
Beispiel 2:Example 2:
Fig. 2 zeigt eine weitere Variante der naßchemischen Abdunnung der Silizium- Deckelschicht 3+8 im aktiven Emittergebiet 7 eines Bipolartransistors mit Basisanschluß auf dem Feldisolationsgebiet 6.2 shows a further variant of the wet chemical thinning of the silicon cover layer 3 + 8 in the active emitter region 7 of a bipolar transistor with a base connection on the field insulation region 6.
Eine Epitaxieschichtfolge, bestehend aus Pufferschicht 1, in-situ dotierter Basisschicht 2 und Deckelschicht 3, in der sich eine Dotandenschicht 10 befindet, die aufgrund der Art ihrer Erzeugung bewirkt, daß die Deckelschicht 8 nach Bildung der Dotandenschicht 10
polykristallin weiterwächst, bedeckt das Gebiet des zukünftigen Emitters und einen Teil des Feldisolationsgebietes 6 als polykristalliner Schichtstapel 1/1; 2/1; 3/1; 10/1; 8/1. Die strukturierte Epitaxieschicht ist mit einem Dielektrikum 4 bedeckt, das nur im Bereich des aktiven Emittergebietes 7 entfernt wurde. Die Dotierungsdosis der Dotandenschicht 10 im Deckel, erzeugt mittels ALD, ist größer als eine Monolage des jeweiligen Dotanden mit einer Dicke kleiner als 3 nm, so daß die darüberliegende Deckelschicht 8 polykristallin wächst. Mit Hilfe bekannter naßchemischer Ätzmittel, die Poly-Silizium hochselektiv zum Dielektrikum 4 und zum kristallinen Silizium 3 abtragen, wird im aktiven Emittergebiet 7 der polykristalline Teil der Deckelschicht 8 inklusive Dotandenschicht 10 entfernt.An epitaxial layer sequence, consisting of buffer layer 1, in-situ doped base layer 2 and cover layer 3, in which there is a dopant layer 10 which, due to the nature of its production, causes the cover layer 8 after the formation of the dopant layer 10 continues to grow polycrystalline, covers the area of the future emitter and part of the field isolation area 6 as a polycrystalline layer stack 1/1; 2/1; 3/1; 10/1; 8/1. The structured epitaxial layer is covered with a dielectric 4, which was only removed in the area of the active emitter region 7. The doping dose of the dopant layer 10 in the cover, produced by means of ALD, is greater than a monolayer of the respective dopant with a thickness of less than 3 nm, so that the cover layer 8 lying above it grows polycrystalline. The polycrystalline part of the cover layer 8, including the dopant layer 10, is removed in the active emitter region 7 with the aid of known wet chemical etching agents which remove polysilicon highly selectively with respect to the dielectric 4 and the crystalline silicon 3.
In der vorliegenden Erfindung wurde anhand konkreter Ausführungsbeispiele ein Verfahren zur naßchemischen Abdunnung von Si-Schichten im aktiven Emittergebiet eines Bipolartransistors erläutert. Es sei aber vermerkt, daß die vorliegende Erfindung nicht auf die Einzelheiten der Beschreibung in den Ausführungsbeispielen eingeschränkt ist, da im Rahmen der Patentansprüche Änderungen und Abwandlungen beansprucht werden.
In the present invention, a method for wet chemical thinning of Si layers in the active emitter region of a bipolar transistor was explained using specific exemplary embodiments. However, it should be noted that the present invention is not restricted to the details of the description in the exemplary embodiments, since changes and modifications are claimed within the scope of the patent claims.
Claims
1. Verfahren zur naßchemischen Abdunnung von Siliziumschichten im aktiven Emittergebiet (7) eines Bipolartransistors, dadurch gekennzeichnet, daß eine zusätzlich mittels „Atomic Layer Doping" (ALD) in eine Deckelschicht (3+9) eingebrachte Dotierung mit einer Dicke kleiner 3 nm als Ätzstoppschicht (5) für naßchemische Ätzmittel wirkt und die Ätzstoppschicht (5) mit einem naßchemischen Ätzmittel entfernt wird.1. A process for the wet chemical thinning of silicon layers in the active emitter region (7) of a bipolar transistor, characterized in that an additional doping with a thickness of less than 3 nm as an etching stop layer is introduced into a cover layer (3 + 9) by means of “atomic layer doping” (ALD) (5) acts for wet chemical etchants and the etch stop layer (5) is removed with a wet chemical etchant.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Stärke der dotierten Ätzstopp schicht (5) kleiner als eine Monolage stark ist und das Schichtwachstum der Deckelschicht (8) über der Ätzstoppschicht (5) weiter einkristallin erfolgt, so daß ein Silizium-Ätzmittel, das einkristalline Silizium der Deckelschicht (8) hochselektiv zur Ätzstoppschicht (5) und zum Dielektrikum (4) entfernt, verwendet wird.2. The method according to claim 1, characterized in that the thickness of the doped etch stop layer (5) is less than a monolayer and the layer growth of the cover layer (8) over the etch stop layer (5) is further monocrystalline, so that a silicon etchant , the monocrystalline silicon of the cover layer (8) is removed highly selectively to the etch stop layer (5) and to the dielectric (4).
3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Dotandenschicht (10) größer als eine Monolage, jedoch kleiner 3 nm ist, so daß das Schichtwachstum über der Dotandenschicht (10) polykristallin erfolgt, ein Silizium-Ätzmittel, das das polykristalline Silizium der Deckelschicht (9) hochselektiv zum einkristallinen Silizium (3) des Deckels und zum Dielektrikum (4) entfernt, verwendet werden kann.3. The method according to claim 1, characterized in that the dopant layer (10) is larger than a monolayer, but less than 3 nm, so that the layer growth over the dopant layer (10) is polycrystalline, a silicon etchant that the polycrystalline silicon Cover layer (9) highly selectively to the single-crystal silicon (3) of the cover and to the dielectric (4) can be used.
4. Verfahren nach einem oder mehreren der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Dotandenschicht (10) zusammen mit dem polykristallinen Silizium der Deckelschicht (9) entfernt wird.
4. The method according to one or more of the preceding claims, characterized in that the dopant layer (10) is removed together with the polycrystalline silicon of the cover layer (9).
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Application Number | Priority Date | Filing Date | Title |
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DE1998145790 DE19845790B4 (en) | 1998-09-21 | 1998-09-21 | Process for the wet-chemical thinning of Si layers in the active emitter region of a bipolar transistor |
DE19845790.1 | 1998-09-21 |
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WO2000017922A1 true WO2000017922A1 (en) | 2000-03-30 |
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PCT/DE1999/003068 WO2000017922A1 (en) | 1998-09-21 | 1999-09-20 | METHOD FOR THE WET-CHEMICAL THINNING OF Si-LAYERS IN THE ACTIVE EMITTER REGION OF A BIPOLAR TRANSISTOR |
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WO (1) | WO2000017922A1 (en) |
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DE102004053393B4 (en) * | 2004-11-05 | 2007-01-11 | Atmel Germany Gmbh | Method for producing a vertically integrated cascode structure and vertically integrated cascode structure |
DE102004053394B4 (en) | 2004-11-05 | 2010-08-19 | Atmel Automotive Gmbh | Semiconductor arrangement and method for producing a semiconductor device |
DE102004055213B4 (en) | 2004-11-16 | 2009-04-09 | Atmel Germany Gmbh | Method for producing an integrated circuit on a semiconductor chip |
Citations (1)
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EP0483487A1 (en) * | 1990-10-31 | 1992-05-06 | International Business Machines Corporation | Self-aligned epitaxial base transistor and method for fabricating same |
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US5198372A (en) * | 1986-01-30 | 1993-03-30 | Texas Instruments Incorporated | Method for making a shallow junction bipolar transistor and transistor formed thereby |
US5096842A (en) * | 1988-05-16 | 1992-03-17 | Kabushiki Kaisha Toshiba | Method of fabricating bipolar transistor using self-aligned polysilicon technology |
JPH06101473B2 (en) * | 1988-12-05 | 1994-12-12 | 日本電気株式会社 | Semiconductor device |
US5024957A (en) * | 1989-02-13 | 1991-06-18 | International Business Machines Corporation | Method of fabricating a bipolar transistor with ultra-thin epitaxial base |
US5648294A (en) * | 1989-11-29 | 1997-07-15 | Texas Instruments Incorp. | Integrated circuit and method |
US5160994A (en) * | 1990-02-19 | 1992-11-03 | Nec Corporation | Heterojunction bipolar transistor with improved base layer |
JPH0669227A (en) * | 1992-05-29 | 1994-03-11 | Texas Instr Inc <Ti> | Heterojunction bipolar transistor of compound semiconductor and its manufacture |
JPH06132298A (en) * | 1992-10-14 | 1994-05-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US5593905A (en) * | 1995-02-23 | 1997-01-14 | Texas Instruments Incorporated | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
DE19533677A1 (en) * | 1995-09-12 | 1997-03-13 | Daimler Benz Ag | Method of manufacturing a heterobipolar transistor |
US5640025A (en) * | 1995-12-01 | 1997-06-17 | Motorola | High frequency semiconductor transistor |
EP0812470B1 (en) * | 1995-12-28 | 2003-03-19 | Koninklijke Philips Electronics N.V. | A method of manufacturing a self-aligned vertical bipolar transistor on an soi |
DE19609933A1 (en) * | 1996-03-14 | 1997-09-18 | Daimler Benz Ag | Method of manufacturing a heterobipolar transistor |
US5773350A (en) * | 1997-01-28 | 1998-06-30 | National Semiconductor Corporation | Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base |
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1998
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EP0483487A1 (en) * | 1990-10-31 | 1992-05-06 | International Business Machines Corporation | Self-aligned epitaxial base transistor and method for fabricating same |
Non-Patent Citations (1)
Title |
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LAN W H ET AL: "RECESSED-GATE ALGAAS/INGAAS/GAAS PSEUDORPMORPHIC HEMT WITH SI- PLANAR-DOPED ETCH STOP LAYER", ELECTRONICS LETTERS,GB,IEE STEVENAGE, vol. 31, no. 7, 30 March 1995 (1995-03-30), pages 592 - 594, XP000504333, ISSN: 0013-5194 * |
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DE19845790A1 (en) | 2000-03-23 |
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